Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

1950058

1

T8

175

T16

237

T17

126

full_word

1222304

1

T2

4

T3

2

T8

24

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3172042	1			T2	4		T3	2		T8	199
auto[TlIntgErrCmd]	108	1			T57	6		T58	6		T59	4
auto[TlIntgErrData]	107	1			T57	6		T58	5		T59	2
auto[TlIntgErrBoth]	105	1			T57	8		T58	9		T59	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

510849

1

T2

4

T3

2

T8

199

auto[1]

2661513

1

T13

218078

T14

136327

T15

627339

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	221418	1			T8	175		T16	237		T17	126
auto[TlIntgErrNone]	partial	auto[1]	1728345	1			T13	143383		T14	89549		T15	404811
auto[TlIntgErrNone]	full_word	auto[0]	289294	1			T2	4		T3	2		T8	24
auto[TlIntgErrNone]	full_word	auto[1]	932985	1			T13	74695		T14	46778		T15	222528
auto[TlIntgErrCmd]	partial	auto[0]	42	1			T57	3		T58	1		T59	1
auto[TlIntgErrCmd]	partial	auto[1]	59	1			T57	3		T58	5		T59	3
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T102	1		T107	1		T103	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T108	1		T109	1		T110	1
auto[TlIntgErrData]	partial	auto[0]	43	1			T57	4		T59	1		T102	3
auto[TlIntgErrData]	partial	auto[1]	54	1			T57	1		T58	5		T59	1
auto[TlIntgErrData]	full_word	auto[0]	3	1			T103	1		T104	1		T111	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T57	1		T102	2		T112	2
auto[TlIntgErrBoth]	partial	auto[0]	44	1			T57	6		T58	3		T59	2
auto[TlIntgErrBoth]	partial	auto[1]	53	1			T57	2		T58	5		T59	1
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T111	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T58	1		T59	1		T102	1