Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

1959003

1

T6

31

T7

33

T8

58

full_word

1241557

1

T1

4

T3

4

T6

6

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3200250	1			T1	4		T3	4		T6	37
auto[TlIntgErrCmd]	115	1			T59	3		T60	4		T61	6
auto[TlIntgErrData]	111	1			T59	5		T60	2		T61	8
auto[TlIntgErrBoth]	84	1			T59	2		T60	4		T61	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

509014

1

T1

4

T3

4

T6

37

auto[1]

2691546

1

T12

226629

T15

149468

T16

118247

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	215513	1			T6	31		T7	33		T8	58
auto[TlIntgErrNone]	partial	auto[1]	1743208	1			T12	145217		T15	99194		T16	76428
auto[TlIntgErrNone]	full_word	auto[0]	293359	1			T1	4		T3	4		T6	6
auto[TlIntgErrNone]	full_word	auto[1]	948170	1			T12	81412		T15	50274		T16	41819
auto[TlIntgErrCmd]	partial	auto[0]	49	1			T59	2		T60	2		T61	2
auto[TlIntgErrCmd]	partial	auto[1]	61	1			T59	1		T60	2		T61	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T61	1		T103	2		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T105	1		T106	1		-	-
auto[TlIntgErrData]	partial	auto[0]	47	1			T59	1		T61	6		T100	1
auto[TlIntgErrData]	partial	auto[1]	49	1			T59	4		T60	2		T61	2
auto[TlIntgErrData]	full_word	auto[0]	7	1			T100	1		T103	1		T107	1
auto[TlIntgErrData]	full_word	auto[1]	8	1			T103	1		T104	1		T108	1
auto[TlIntgErrBoth]	partial	auto[0]	30	1			T59	1		T60	2		T61	3
auto[TlIntgErrBoth]	partial	auto[1]	46	1			T59	1		T60	1		T61	2
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T60	1		T61	1		T100	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T104	1		T108	1		-	-