Unified Coverage Report :: Group :: tb.dut.u_rom_ctrl_cov_if::rom_ctrl_tlul_cg

Group : tb.dut.u_rom_ctrl_cov_if::rom_ctrl_tlul_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
75.00	75.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rom_ctrl_cov_0/rom_ctrl_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
rom_ctrl_tlul_cg	75.00	1	100	1	64	64

---

Group Instance : rom_ctrl_tlul_cg
Comment: TLUL interface behaviors

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
75.00	1	100	1	64	64

---

Summary for Group Instance rom_ctrl_tlul_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	2	6	75.00

Variables for Group Instance rom_ctrl_tlul_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regs_req_check	3	1	2	66.67	100	1	1	0
cp_rom_invalid_condition	2	1	1	50.00	100	1	1	0
cp_rom_req_check	3	0	3	100.00	100	1	1	0

Summary for Variable cp_regs_req_check

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	1	2	66.67

User Defined Bins for cp_regs_req_check

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
req_before_done	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

req_after_done

1649991

1

T2

7

T3

1

T5

48

req_and_done

2

1

T15

1

T102

1

-

-

---

Summary for Variable cp_rom_invalid_condition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	1	1	50.00

User Defined Bins for cp_rom_invalid_condition

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
check_invalid	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

check_valid

78370440

1

T1

49319

T2

546472

T3

228159

---

Summary for Variable cp_rom_req_check

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rom_req_check

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
req_after_done	1918453	1			T3	3		T4	2		T5	90
req_and_done	55	1			T4	1		T97	1		T98	1
req_before_done	134	1			T5	3		T12	6		T56	2