Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	44679	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1149634

1

T3

3

T4

10

T5

12

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	309249	1			T3	3		T4	91		T5	103
values[0x0]	434636	1			T12	25276		T15	16645		T16	17897
values[0x1]	450428	1			T12	26364		T15	17053		T16	18204

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	23534	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1170779

1

T3

3

T4

57

T5

67

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4686	1			T12	225		T15	180		T101	2
valid_sources[0x01]	5321	1			T4	24		T12	225		T15	180
valid_sources[0x02]	4733	1			T12	301		T15	185		T101	1
valid_sources[0x03]	5067	1			T12	232		T13	2		T15	145
valid_sources[0x04]	4762	1			T12	271		T15	185		T50	365
valid_sources[0x05]	5119	1			T12	318		T13	1		T15	188
valid_sources[0x06]	4575	1			T12	270		T56	2		T15	188
valid_sources[0x07]	5471	1			T12	266		T15	156		T97	20
valid_sources[0x08]	5014	1			T12	307		T15	217		T16	608
valid_sources[0x09]	4611	1			T12	229		T15	182		T101	1
valid_sources[0x0a]	5286	1			T12	199		T15	189		T50	363
valid_sources[0x0b]	4231	1			T12	280		T15	190		T101	1
valid_sources[0x0c]	4393	1			T12	218		T56	1		T15	166
valid_sources[0x0d]	4273	1			T12	262		T15	193		T99	2
valid_sources[0x0e]	4255	1			T12	381		T15	159		T16	2
valid_sources[0x0f]	4038	1			T12	203		T13	1		T15	184
valid_sources[0x10]	4140	1			T12	308		T13	1		T15	199
valid_sources[0x11]	4401	1			T12	256		T13	2		T15	143
valid_sources[0x12]	4738	1			T12	272		T15	209		T120	18
valid_sources[0x13]	4230	1			T12	257		T56	1		T13	1
valid_sources[0x14]	5550	1			T12	189		T15	183		T50	315
valid_sources[0x15]	3932	1			T12	240		T15	176		T121	1
valid_sources[0x16]	4563	1			T12	211		T15	182		T121	1
valid_sources[0x17]	4811	1			T12	320		T56	1		T15	197
valid_sources[0x18]	4162	1			T12	241		T13	1		T15	155
valid_sources[0x19]	4544	1			T12	309		T15	146		T99	2
valid_sources[0x1a]	4264	1			T12	283		T56	1		T15	200
valid_sources[0x1b]	4394	1			T12	215		T15	169		T98	22
valid_sources[0x1c]	4036	1			T12	264		T56	1		T15	175
valid_sources[0x1d]	4624	1			T4	11		T12	280		T56	1
valid_sources[0x1e]	4095	1			T12	303		T13	2		T15	170
valid_sources[0x1f]	4287	1			T4	10		T12	196		T15	186
valid_sources[0x20]	4192	1			T12	251		T13	2		T15	168
valid_sources[0x21]	4402	1			T12	271		T13	5		T15	160
valid_sources[0x22]	5591	1			T5	15		T12	255		T56	2
valid_sources[0x23]	4040	1			T12	218		T13	1		T15	161
valid_sources[0x24]	4690	1			T12	251		T15	172		T101	1
valid_sources[0x25]	4807	1			T12	273		T15	138		T16	28
valid_sources[0x26]	4438	1			T12	277		T56	2		T15	172
valid_sources[0x27]	5058	1			T12	266		T13	2		T15	154
valid_sources[0x28]	6407	1			T12	309		T13	2		T15	152
valid_sources[0x29]	4906	1			T12	255		T15	206		T50	325
valid_sources[0x2a]	4533	1			T3	1		T12	246		T15	154
valid_sources[0x2b]	5507	1			T12	286		T13	2		T15	181
valid_sources[0x2c]	4159	1			T12	249		T15	169		T16	87
valid_sources[0x2d]	4279	1			T12	305		T13	1		T15	200
valid_sources[0x2e]	4672	1			T12	318		T56	1		T15	155
valid_sources[0x2f]	5189	1			T12	268		T15	171		T121	4
valid_sources[0x30]	4059	1			T12	305		T13	1		T15	135
valid_sources[0x31]	4939	1			T12	299		T15	143		T98	13
valid_sources[0x32]	5231	1			T12	327		T15	185		T121	2
valid_sources[0x33]	4890	1			T12	371		T13	1		T15	161
valid_sources[0x34]	4411	1			T12	263		T15	197		T121	1
valid_sources[0x35]	5209	1			T12	304		T13	1		T15	160
valid_sources[0x36]	4501	1			T12	216		T56	3		T15	175
valid_sources[0x37]	4545	1			T12	277		T13	1		T15	173
valid_sources[0x38]	4750	1			T12	242		T15	181		T121	1
valid_sources[0x39]	4212	1			T12	266		T15	154		T99	3
valid_sources[0x3a]	4318	1			T12	264		T18	6		T15	200
valid_sources[0x3b]	4595	1			T12	315		T13	1		T15	173
valid_sources[0x3c]	4310	1			T12	252		T13	2		T15	172
valid_sources[0x3d]	4476	1			T12	299		T56	1		T13	1
valid_sources[0x3e]	3973	1			T12	252		T15	180		T101	1
valid_sources[0x3f]	4801	1			T12	289		T56	1		T15	166
valid_sources[0x40]	3798	1			T8	9		T12	305		T13	1
valid_sources[0x41]	4148	1			T12	222		T15	169		T121	3
valid_sources[0x42]	4128	1			T12	324		T15	199		T99	1
valid_sources[0x43]	4192	1			T12	210		T15	163		T119	9
valid_sources[0x44]	5303	1			T12	268		T15	186		T99	4
valid_sources[0x45]	3931	1			T12	256		T15	195		T99	1
valid_sources[0x46]	5461	1			T12	318		T56	1		T13	1
valid_sources[0x47]	4399	1			T12	301		T18	4		T13	2
valid_sources[0x48]	4977	1			T12	254		T15	174		T16	510
valid_sources[0x49]	5209	1			T12	299		T18	2		T13	1
valid_sources[0x4a]	4368	1			T12	245		T15	191		T99	2
valid_sources[0x4b]	5387	1			T12	250		T56	1		T15	188
valid_sources[0x4c]	5417	1			T12	219		T15	198		T101	1
valid_sources[0x4d]	4218	1			T12	317		T15	164		T99	1
valid_sources[0x4e]	4328	1			T12	313		T18	2		T15	192
valid_sources[0x4f]	5328	1			T20	6		T12	302		T13	1
valid_sources[0x50]	4384	1			T12	266		T13	3		T15	159
valid_sources[0x51]	3955	1			T12	291		T15	168		T50	351
valid_sources[0x52]	4745	1			T12	239		T56	1		T14	3
valid_sources[0x53]	4123	1			T12	328		T18	3		T56	1
valid_sources[0x54]	4057	1			T4	8		T12	286		T15	156
valid_sources[0x55]	5044	1			T12	270		T13	1		T15	172
valid_sources[0x56]	4546	1			T12	288		T15	178		T98	34
valid_sources[0x57]	4255	1			T12	234		T15	164		T101	1
valid_sources[0x58]	4385	1			T12	307		T56	1		T15	175
valid_sources[0x59]	4647	1			T12	292		T15	183		T19	6
valid_sources[0x5a]	4461	1			T12	207		T56	2		T13	1
valid_sources[0x5b]	4031	1			T12	277		T15	166		T101	1
valid_sources[0x5c]	3885	1			T12	263		T13	1		T15	176
valid_sources[0x5d]	4713	1			T12	296		T56	2		T15	161
valid_sources[0x5e]	5059	1			T12	249		T13	3		T15	180
valid_sources[0x5f]	4338	1			T12	236		T13	1		T15	169
valid_sources[0x60]	4937	1			T12	290		T15	171		T50	365
valid_sources[0x61]	4663	1			T12	259		T56	1		T13	1
valid_sources[0x62]	4273	1			T12	296		T15	183		T99	1
valid_sources[0x63]	5315	1			T12	314		T15	190		T121	2
valid_sources[0x64]	4315	1			T12	281		T13	1		T15	173
valid_sources[0x65]	5529	1			T12	287		T15	205		T16	552
valid_sources[0x66]	4137	1			T12	301		T13	2		T15	232
valid_sources[0x67]	4361	1			T12	248		T56	1		T15	145
valid_sources[0x68]	5132	1			T12	225		T15	163		T121	2
valid_sources[0x69]	5710	1			T12	246		T56	1		T15	166
valid_sources[0x6a]	5421	1			T12	247		T15	196		T99	1
valid_sources[0x6b]	4449	1			T12	266		T15	179		T50	366
valid_sources[0x6c]	5749	1			T12	236		T18	1		T15	130
valid_sources[0x6d]	4592	1			T12	226		T15	185		T101	1
valid_sources[0x6e]	3938	1			T12	254		T15	184		T101	2
valid_sources[0x6f]	4703	1			T12	267		T15	165		T121	3
valid_sources[0x70]	5009	1			T12	247		T13	1		T15	152
valid_sources[0x71]	4473	1			T12	263		T15	168		T97	21
valid_sources[0x72]	5477	1			T12	240		T56	1		T15	195
valid_sources[0x73]	5012	1			T12	259		T13	1		T15	195
valid_sources[0x74]	4351	1			T12	322		T13	1		T15	146
valid_sources[0x75]	4826	1			T12	275		T15	167		T101	1
valid_sources[0x76]	3866	1			T12	282		T13	1		T15	144
valid_sources[0x77]	4485	1			T12	260		T15	187		T101	1
valid_sources[0x78]	4050	1			T12	258		T13	2		T15	200
valid_sources[0x79]	4959	1			T12	252		T13	1		T15	194
valid_sources[0x7a]	4720	1			T12	222		T15	169		T44	1
valid_sources[0x7b]	5790	1			T12	280		T56	1		T13	2
valid_sources[0x7c]	5309	1			T12	204		T56	2		T13	1
valid_sources[0x7d]	4937	1			T12	302		T15	169		T99	1
valid_sources[0x7e]	4806	1			T7	6		T12	242		T15	161
valid_sources[0x7f]	3868	1			T12	272		T13	1		T15	169
valid_sources[0x80]	4430	1			T5	12		T12	355		T56	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

288312

1

T3

3

T4

10

T5

12

values[0x0]

all_enables

biggest_size

430683

1

T12

25076

T15

16486

T16

17748

values[0x1]

all_enables

biggest_size

430639

1

T12

25248

T15

16273

T16

17494

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	86301	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

887440

1

T1

1

T2

12

T3

14

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	240982	1			T1	1		T2	32		T3	34
values[0x0]	339857	1			T6	1		T12	19401		T27	4
values[0x1]	392902	1			T6	1		T12	22830		T27	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	38747	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

934994

1

T1

1

T2

14

T3

17

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3430	1			T12	229		T15	50		T16	96
valid_sources[0x01]	3497	1			T5	2		T12	240		T13	1
valid_sources[0x02]	3932	1			T2	3		T12	232		T14	1
valid_sources[0x03]	3781	1			T12	210		T13	1		T15	152
valid_sources[0x04]	3579	1			T12	216		T14	1		T15	17
valid_sources[0x05]	4144	1			T12	210		T47	16		T15	251
valid_sources[0x06]	3515	1			T12	215		T21	1		T43	1
valid_sources[0x07]	3974	1			T12	209		T13	1		T15	41
valid_sources[0x08]	3637	1			T5	1		T12	186		T15	119
valid_sources[0x09]	3502	1			T5	1		T12	246		T15	70
valid_sources[0x0a]	3402	1			T8	1		T12	230		T13	2
valid_sources[0x0b]	3569	1			T12	220		T49	1		T15	207
valid_sources[0x0c]	4125	1			T12	233		T15	111		T30	1
valid_sources[0x0d]	4123	1			T12	245		T21	1		T15	131
valid_sources[0x0e]	3995	1			T12	210		T15	203		T28	1
valid_sources[0x0f]	3899	1			T20	3		T12	187		T15	179
valid_sources[0x10]	3699	1			T12	231		T13	1		T15	27
valid_sources[0x11]	3922	1			T12	198		T15	49		T16	307
valid_sources[0x12]	3693	1			T12	230		T43	1		T15	101
valid_sources[0x13]	4152	1			T20	1		T12	223		T13	2
valid_sources[0x14]	3684	1			T12	212		T43	1		T14	2
valid_sources[0x15]	3361	1			T12	195		T15	150		T16	5
valid_sources[0x16]	3705	1			T20	1		T12	216		T15	155
valid_sources[0x17]	3507	1			T12	177		T15	16		T16	215
valid_sources[0x18]	3794	1			T12	181		T15	124		T16	2
valid_sources[0x19]	3859	1			T12	202		T13	2		T15	62
valid_sources[0x1a]	3995	1			T12	244		T15	142		T16	344
valid_sources[0x1b]	3534	1			T12	232		T14	1		T15	157
valid_sources[0x1c]	3632	1			T12	194		T15	113		T16	125
valid_sources[0x1d]	3966	1			T12	214		T15	132		T16	135
valid_sources[0x1e]	4380	1			T12	249		T13	1		T15	166
valid_sources[0x1f]	4005	1			T12	184		T13	1		T15	192
valid_sources[0x20]	3600	1			T12	195		T15	68		T46	2
valid_sources[0x21]	3619	1			T12	196		T21	1		T15	219
valid_sources[0x22]	3491	1			T12	194		T15	93		T100	1
valid_sources[0x23]	4433	1			T12	231		T21	1		T43	1
valid_sources[0x24]	3643	1			T5	1		T12	209		T15	160
valid_sources[0x25]	3913	1			T12	237		T15	176		T16	455
valid_sources[0x26]	3834	1			T12	208		T15	196		T16	77
valid_sources[0x27]	3952	1			T12	227		T15	148		T16	200
valid_sources[0x28]	3816	1			T12	234		T13	1		T15	85
valid_sources[0x29]	4171	1			T12	219		T15	156		T16	206
valid_sources[0x2a]	3653	1			T12	202		T13	1		T15	156
valid_sources[0x2b]	3501	1			T12	230		T15	50		T50	308
valid_sources[0x2c]	3588	1			T12	217		T13	1		T15	164
valid_sources[0x2d]	3605	1			T12	201		T15	140		T46	1
valid_sources[0x2e]	3776	1			T12	255		T15	231		T16	11
valid_sources[0x2f]	3412	1			T12	221		T13	1		T15	76
valid_sources[0x30]	3910	1			T8	3		T12	232		T43	1
valid_sources[0x31]	3647	1			T5	6		T12	220		T15	119
valid_sources[0x32]	3488	1			T12	227		T15	99		T29	1
valid_sources[0x33]	3493	1			T12	212		T15	197		T16	20
valid_sources[0x34]	3609	1			T7	2		T12	219		T15	89
valid_sources[0x35]	3985	1			T7	3		T12	209		T15	176
valid_sources[0x36]	4086	1			T12	230		T15	281		T16	3
valid_sources[0x37]	3872	1			T12	218		T13	1		T14	2
valid_sources[0x38]	3651	1			T12	230		T13	1		T15	32
valid_sources[0x39]	3489	1			T12	241		T13	1		T15	82
valid_sources[0x3a]	3868	1			T12	226		T15	159		T16	186
valid_sources[0x3b]	3879	1			T12	206		T15	138		T16	2
valid_sources[0x3c]	3290	1			T20	1		T12	208		T15	207
valid_sources[0x3d]	3861	1			T12	234		T15	81		T45	3
valid_sources[0x3e]	4169	1			T12	232		T15	218		T16	234
valid_sources[0x3f]	3546	1			T12	206		T43	3		T15	82
valid_sources[0x40]	4253	1			T12	214		T15	128		T16	780
valid_sources[0x41]	4126	1			T12	222		T13	1		T15	173
valid_sources[0x42]	3590	1			T12	209		T21	1		T15	103
valid_sources[0x43]	3663	1			T12	202		T13	1		T15	234
valid_sources[0x44]	4049	1			T12	254		T13	1		T14	2
valid_sources[0x45]	3221	1			T12	199		T15	154		T50	242
valid_sources[0x46]	4214	1			T12	226		T21	1		T14	1
valid_sources[0x47]	4287	1			T5	1		T12	239		T13	1
valid_sources[0x48]	3692	1			T12	244		T13	1		T15	113
valid_sources[0x49]	3478	1			T12	224		T15	138		T50	281
valid_sources[0x4a]	3500	1			T9	7		T12	205		T13	1
valid_sources[0x4b]	3722	1			T12	220		T21	2		T15	219
valid_sources[0x4c]	3588	1			T12	233		T15	85		T50	301
valid_sources[0x4d]	4001	1			T5	1		T12	229		T15	156
valid_sources[0x4e]	4035	1			T12	216		T43	2		T15	140
valid_sources[0x4f]	3932	1			T12	240		T15	201		T16	150
valid_sources[0x50]	3706	1			T12	229		T15	161		T16	304
valid_sources[0x51]	3532	1			T12	204		T15	293		T16	12
valid_sources[0x52]	4027	1			T12	199		T13	1		T15	114
valid_sources[0x53]	3971	1			T12	207		T21	1		T15	176
valid_sources[0x54]	3346	1			T12	208		T15	97		T50	296
valid_sources[0x55]	3540	1			T12	220		T14	1		T15	83
valid_sources[0x56]	4237	1			T31	1		T12	235		T15	201
valid_sources[0x57]	3503	1			T12	226		T13	1		T15	108
valid_sources[0x58]	3863	1			T12	215		T13	2		T15	211
valid_sources[0x59]	4663	1			T5	2		T12	203		T15	297
valid_sources[0x5a]	3463	1			T12	181		T15	45		T16	228
valid_sources[0x5b]	3272	1			T12	203		T13	1		T15	58
valid_sources[0x5c]	3994	1			T3	34		T12	219		T13	1
valid_sources[0x5d]	3337	1			T7	1		T12	225		T15	162
valid_sources[0x5e]	3489	1			T12	213		T15	110		T16	2
valid_sources[0x5f]	4006	1			T12	246		T21	1		T13	1
valid_sources[0x60]	4100	1			T12	237		T15	147		T16	91
valid_sources[0x61]	3902	1			T12	212		T15	132		T16	446
valid_sources[0x62]	3578	1			T12	204		T15	74		T45	4
valid_sources[0x63]	3787	1			T5	2		T12	208		T15	46
valid_sources[0x64]	3754	1			T12	238		T13	1		T15	127
valid_sources[0x65]	4147	1			T12	236		T43	1		T15	65
valid_sources[0x66]	4008	1			T12	224		T15	184		T16	62
valid_sources[0x67]	3593	1			T2	4		T12	217		T15	229
valid_sources[0x68]	3661	1			T12	205		T21	1		T15	116
valid_sources[0x69]	3806	1			T5	1		T20	3		T12	221
valid_sources[0x6a]	3901	1			T12	216		T43	1		T15	160
valid_sources[0x6b]	3790	1			T20	2		T11	1		T12	227
valid_sources[0x6c]	3591	1			T12	184		T15	174		T50	351
valid_sources[0x6d]	4146	1			T12	230		T15	94		T28	1
valid_sources[0x6e]	3947	1			T12	228		T21	1		T15	63
valid_sources[0x6f]	3505	1			T12	242		T13	1		T15	343
valid_sources[0x70]	4317	1			T12	246		T15	142		T16	33
valid_sources[0x71]	3663	1			T12	245		T15	137		T122	1
valid_sources[0x72]	3869	1			T5	1		T12	233		T15	101
valid_sources[0x73]	3937	1			T12	176		T13	1		T15	146
valid_sources[0x74]	3719	1			T12	182		T43	1		T15	93
valid_sources[0x75]	3989	1			T12	215		T15	102		T45	2
valid_sources[0x76]	3454	1			T12	228		T15	51		T16	147
valid_sources[0x77]	4281	1			T12	251		T15	200		T16	416
valid_sources[0x78]	4182	1			T12	225		T18	4		T15	203
valid_sources[0x79]	4886	1			T5	1		T12	230		T15	137
valid_sources[0x7a]	3533	1			T12	201		T15	117		T50	293
valid_sources[0x7b]	3709	1			T12	207		T15	380		T16	233
valid_sources[0x7c]	3478	1			T12	177		T13	1		T15	90
valid_sources[0x7d]	3826	1			T5	4		T12	223		T13	2
valid_sources[0x7e]	3798	1			T5	1		T12	210		T18	8
valid_sources[0x7f]	3740	1			T12	232		T15	267		T16	64
valid_sources[0x80]	3566	1			T12	208		T13	1		T15	166

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

222588

1

T1

1

T2

12

T3

14

values[0x0]

all_enables

biggest_size

332762

1

T12

18992

T27

2

T15

12274

values[0x1]

all_enables

biggest_size

332090

1

T12

19018

T27

1

T15

12274