Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

2108717

1

T4

81

T5

91

T9

46

full_word

1341834

1

T3

2

T4

10

T5

12

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3450251	1			T3	2		T4	91		T5	103
auto[TlIntgErrCmd]	106	1			T58	12		T59	6		T60	4
auto[TlIntgErrData]	97	1			T58	4		T59	10		T60	6
auto[TlIntgErrBoth]	97	1			T58	4		T59	4		T60	10

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

539631

1

T3

2

T4

91

T5

103

auto[1]

2910920

1

T12

166856

T15

114805

T16

117787

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	223544	1			T4	81		T5	91		T9	46
auto[TlIntgErrNone]	partial	auto[1]	1884890	1			T12	107051		T15	75445		T16	75817
auto[TlIntgErrNone]	full_word	auto[0]	315957	1			T3	2		T4	10		T5	12
auto[TlIntgErrNone]	full_word	auto[1]	1025860	1			T12	59805		T15	39360		T16	41970
auto[TlIntgErrCmd]	partial	auto[0]	41	1			T58	8		T59	1		T104	2
auto[TlIntgErrCmd]	partial	auto[1]	57	1			T58	4		T59	5		T60	3
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T60	1		T106	2		T113	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T110	1		T113	1		T114	1
auto[TlIntgErrData]	partial	auto[0]	43	1			T58	2		T59	5		T60	3
auto[TlIntgErrData]	partial	auto[1]	48	1			T58	2		T59	4		T60	3
auto[TlIntgErrData]	full_word	auto[0]	2	1			T115	1		T116	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	4	1			T59	1		T103	1		T117	2
auto[TlIntgErrBoth]	partial	auto[0]	37	1			T58	2		T59	2		T60	3
auto[TlIntgErrBoth]	partial	auto[1]	57	1			T58	1		T59	2		T60	7
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T58	1		T118	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	1	1			T112	1		-	-		-	-