Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	15349	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

25045

1

T2

5

T3

6

T5

37

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	22427	1			T2	36		T3	6		T5	364
values[0x0]	8649	1			T15	5303		T28	140		T54	2
values[0x1]	9318	1			T15	5639		T27	6		T28	134

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6829	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

33565

1

T2

22

T3

6

T5

199

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	77	1			T134	2		T135	3		T34	1
valid_sources[0x01]	91	1			T10	1		T38	1		T136	1
valid_sources[0x02]	141	1			T12	2		T70	1		T17	1
valid_sources[0x03]	91	1			T12	1		T16	1		T137	1
valid_sources[0x04]	280	1			T138	2		T139	2		T37	1
valid_sources[0x05]	365	1			T23	1		T12	4		T14	1
valid_sources[0x06]	71	1			T70	2		T34	2		T140	1
valid_sources[0x07]	115	1			T10	2		T12	1		T70	1
valid_sources[0x08]	77	1			T12	1		T134	2		T38	1
valid_sources[0x09]	104	1			T137	1		T94	4		T135	1
valid_sources[0x0a]	901	1			T14	2		T141	1		T134	1
valid_sources[0x0b]	107	1			T12	2		T137	1		T94	6
valid_sources[0x0c]	222	1			T70	1		T134	1		T139	1
valid_sources[0x0d]	108	1			T12	1		T16	5		T137	1
valid_sources[0x0e]	107	1			T3	6		T12	1		T70	3
valid_sources[0x0f]	107	1			T8	11		T10	3		T94	2
valid_sources[0x10]	673	1			T13	1		T17	2		T141	4
valid_sources[0x11]	81	1			T12	1		T70	2		T137	1
valid_sources[0x12]	122	1			T5	21		T13	1		T137	2
valid_sources[0x13]	99	1			T12	4		T70	1		T14	2
valid_sources[0x14]	110	1			T20	3		T71	1		T14	2
valid_sources[0x15]	65	1			T12	1		T14	2		T135	2
valid_sources[0x16]	90	1			T16	1		T70	1		T134	1
valid_sources[0x17]	112	1			T12	2		T137	2		T134	1
valid_sources[0x18]	79	1			T12	1		T70	1		T37	1
valid_sources[0x19]	315	1			T141	6		T135	1		T34	1
valid_sources[0x1a]	114	1			T6	15		T23	2		T12	1
valid_sources[0x1b]	139	1			T109	72		T70	2		T134	2
valid_sources[0x1c]	96	1			T10	3		T12	1		T70	1
valid_sources[0x1d]	86	1			T10	1		T12	1		T71	1
valid_sources[0x1e]	75	1			T134	1		T138	2		T139	1
valid_sources[0x1f]	96	1			T14	1		T142	11		T138	1
valid_sources[0x20]	66	1			T12	1		T13	1		T137	1
valid_sources[0x21]	94	1			T10	1		T17	2		T134	1
valid_sources[0x22]	115	1			T5	24		T12	3		T43	1
valid_sources[0x23]	95	1			T12	1		T14	1		T17	2
valid_sources[0x24]	91	1			T12	1		T71	1		T134	2
valid_sources[0x25]	91	1			T10	1		T70	1		T14	3
valid_sources[0x26]	86	1			T70	1		T14	1		T134	2
valid_sources[0x27]	80	1			T12	1		T22	1		T70	1
valid_sources[0x28]	291	1			T70	1		T14	1		T134	1
valid_sources[0x29]	249	1			T10	2		T42	6		T12	4
valid_sources[0x2a]	57	1			T70	1		T137	1		T138	1
valid_sources[0x2b]	102	1			T14	1		T137	1		T94	3
valid_sources[0x2c]	96	1			T12	1		T16	5		T70	1
valid_sources[0x2d]	115	1			T14	2		T142	11		T138	3
valid_sources[0x2e]	66	1			T12	1		T70	1		T14	2
valid_sources[0x2f]	97	1			T12	1		T14	2		T134	1
valid_sources[0x30]	155	1			T70	1		T14	1		T34	1
valid_sources[0x31]	102	1			T44	3		T70	1		T141	4
valid_sources[0x32]	79	1			T23	1		T70	1		T14	1
valid_sources[0x33]	62	1			T12	1		T137	1		T34	2
valid_sources[0x34]	624	1			T14	1		T17	1		T34	1
valid_sources[0x35]	121	1			T12	1		T14	2		T141	11
valid_sources[0x36]	77	1			T14	1		T141	4		T139	1
valid_sources[0x37]	124	1			T109	11		T13	1		T70	1
valid_sources[0x38]	85	1			T12	1		T14	1		T143	16
valid_sources[0x39]	85	1			T12	1		T70	1		T141	1
valid_sources[0x3a]	139	1			T12	2		T142	34		T139	3
valid_sources[0x3b]	83	1			T12	1		T70	2		T134	1
valid_sources[0x3c]	102	1			T12	1		T71	1		T14	1
valid_sources[0x3d]	94	1			T13	1		T14	1		T94	13
valid_sources[0x3e]	57	1			T12	1		T13	1		T71	1
valid_sources[0x3f]	158	1			T14	1		T17	2		T134	1
valid_sources[0x40]	59	1			T10	1		T12	2		T138	2
valid_sources[0x41]	638	1			T21	1		T14	1		T94	13
valid_sources[0x42]	46	1			T13	1		T139	1		T135	1
valid_sources[0x43]	112	1			T12	2		T14	1		T94	12
valid_sources[0x44]	146	1			T94	2		T141	4		T138	1
valid_sources[0x45]	101	1			T6	16		T14	2		T37	3
valid_sources[0x46]	280	1			T12	1		T13	1		T14	2
valid_sources[0x47]	90	1			T70	1		T138	3		T139	1
valid_sources[0x48]	244	1			T71	1		T142	5		T138	4
valid_sources[0x49]	70	1			T21	3		T139	1		T135	1
valid_sources[0x4a]	109	1			T5	36		T21	1		T12	2
valid_sources[0x4b]	93	1			T94	1		T141	2		T138	3
valid_sources[0x4c]	114	1			T22	2		T138	4		T140	1
valid_sources[0x4d]	149	1			T12	1		T14	1		T137	2
valid_sources[0x4e]	180	1			T23	2		T12	2		T44	1
valid_sources[0x4f]	123	1			T12	1		T70	1		T138	3
valid_sources[0x50]	103	1			T138	1		T33	20		T34	3
valid_sources[0x51]	178	1			T12	1		T14	1		T137	1
valid_sources[0x52]	110	1			T12	1		T110	1		T137	1
valid_sources[0x53]	157	1			T5	63		T12	1		T14	1
valid_sources[0x54]	84	1			T138	1		T34	1		T144	1
valid_sources[0x55]	503	1			T5	22		T8	12		T70	1
valid_sources[0x56]	107	1			T137	1		T139	1		T34	1
valid_sources[0x57]	110	1			T70	1		T139	1		T135	2
valid_sources[0x58]	290	1			T70	2		T134	1		T34	1
valid_sources[0x59]	69	1			T14	1		T141	4		T34	4
valid_sources[0x5a]	153	1			T12	2		T134	2		T135	1
valid_sources[0x5b]	99	1			T37	2		T145	2		T95	2
valid_sources[0x5c]	79	1			T14	2		T17	1		T34	2
valid_sources[0x5d]	90	1			T12	1		T13	1		T139	1
valid_sources[0x5e]	210	1			T10	1		T23	1		T12	1
valid_sources[0x5f]	77	1			T12	1		T137	1		T138	2
valid_sources[0x60]	283	1			T12	2		T109	39		T14	2
valid_sources[0x61]	64	1			T12	3		T13	1		T70	1
valid_sources[0x62]	138	1			T8	34		T70	1		T138	1
valid_sources[0x63]	701	1			T12	1		T16	1		T17	1
valid_sources[0x64]	331	1			T138	12		T34	2		T37	1
valid_sources[0x65]	95	1			T10	1		T12	1		T13	1
valid_sources[0x66]	77	1			T10	1		T137	2		T17	1
valid_sources[0x67]	359	1			T6	13		T12	1		T70	1
valid_sources[0x68]	88	1			T71	2		T70	1		T14	2
valid_sources[0x69]	70	1			T13	1		T134	1		T135	1
valid_sources[0x6a]	103	1			T14	2		T17	1		T134	2
valid_sources[0x6b]	131	1			T12	4		T14	2		T94	13
valid_sources[0x6c]	95	1			T71	1		T137	1		T134	1
valid_sources[0x6d]	385	1			T12	1		T70	1		T137	1
valid_sources[0x6e]	71	1			T12	3		T70	2		T141	5
valid_sources[0x6f]	111	1			T139	3		T135	1		T34	5
valid_sources[0x70]	58	1			T22	1		T14	2		T141	1
valid_sources[0x71]	54	1			T43	1		T135	1		T34	1
valid_sources[0x72]	126	1			T12	2		T143	11		T134	1
valid_sources[0x73]	539	1			T14	2		T142	4		T38	2
valid_sources[0x74]	100	1			T5	10		T12	1		T70	1
valid_sources[0x75]	53	1			T13	1		T14	2		T138	6
valid_sources[0x76]	99	1			T70	2		T14	2		T135	1
valid_sources[0x77]	107	1			T10	3		T12	1		T138	3
valid_sources[0x78]	534	1			T6	55		T16	1		T137	1
valid_sources[0x79]	86	1			T10	4		T23	1		T134	2
valid_sources[0x7a]	120	1			T14	3		T94	2		T141	6
valid_sources[0x7b]	254	1			T42	1		T70	1		T139	2
valid_sources[0x7c]	170	1			T10	2		T21	1		T14	2
valid_sources[0x7d]	111	1			T12	1		T70	1		T137	1
valid_sources[0x7e]	209	1			T10	2		T23	1		T12	2
valid_sources[0x7f]	112	1			T12	1		T70	1		T137	2
valid_sources[0x80]	185	1			T6	11		T12	2		T138	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7667

1

T2

5

T3

6

T5

37

values[0x0]

all_enables

biggest_size

8549

1

T15

5268

T28

139

T53

141

values[0x1]

all_enables

biggest_size

8829

1

T15

5396

T28

130

T53

133

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7815	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

33300

1

T1

3

T2

5

T3

19

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	12718	1			T2	16		T3	40		T9	1
values[0x0]	13721	1			T1	3		T4	4		T7	7
values[0x1]	14676	1			T1	4		T4	6		T7	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5420	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

35695

1

T1

3

T2

9

T3

25

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	140	1			T3	1		T16	1		T44	1
valid_sources[0x01]	132	1			T44	1		T79	8		T46	3
valid_sources[0x02]	130	1			T146	1		T15	54		T147	1
valid_sources[0x03]	148	1			T45	1		T96	1		T148	1
valid_sources[0x04]	137	1			T149	1		T145	6		T150	1
valid_sources[0x05]	153	1			T45	3		T151	1		T145	1
valid_sources[0x06]	125	1			T45	1		T149	1		T152	1
valid_sources[0x07]	144	1			T3	2		T44	1		T96	2
valid_sources[0x08]	143	1			T15	45		T62	1		T153	1
valid_sources[0x09]	113	1			T144	7		T154	1		T155	1
valid_sources[0x0a]	163	1			T69	1		T156	1		T157	12
valid_sources[0x0b]	231	1			T158	1		T159	4		T152	3
valid_sources[0x0c]	173	1			T45	2		T156	1		T146	1
valid_sources[0x0d]	139	1			T7	3		T30	1		T160	2
valid_sources[0x0e]	139	1			T40	1		T97	2		T152	1
valid_sources[0x0f]	179	1			T69	2		T161	1		T162	2
valid_sources[0x10]	121	1			T156	1		T160	1		T15	44
valid_sources[0x11]	190	1			T20	1		T163	1		T149	3
valid_sources[0x12]	181	1			T3	2		T18	6		T164	1
valid_sources[0x13]	121	1			T7	1		T46	2		T165	1
valid_sources[0x14]	134	1			T4	1		T149	1		T156	1
valid_sources[0x15]	164	1			T20	2		T163	1		T166	1
valid_sources[0x16]	157	1			T78	1		T167	6		T146	1
valid_sources[0x17]	143	1			T168	1		T51	2		T15	49
valid_sources[0x18]	194	1			T146	1		T96	1		T160	2
valid_sources[0x19]	158	1			T110	1		T78	5		T40	1
valid_sources[0x1a]	117	1			T15	38		T62	2		T169	1
valid_sources[0x1b]	151	1			T149	4		T170	1		T15	49
valid_sources[0x1c]	128	1			T151	1		T160	1		T157	1
valid_sources[0x1d]	139	1			T4	1		T45	1		T97	1
valid_sources[0x1e]	105	1			T146	1		T15	38		T153	2
valid_sources[0x1f]	152	1			T46	2		T151	1		T171	8
valid_sources[0x20]	159	1			T52	13		T146	1		T166	1
valid_sources[0x21]	110	1			T165	1		T97	1		T160	1
valid_sources[0x22]	141	1			T4	1		T71	3		T156	1
valid_sources[0x23]	132	1			T3	2		T7	3		T149	3
valid_sources[0x24]	240	1			T1	7		T3	1		T150	1
valid_sources[0x25]	133	1			T80	1		T172	4		T156	1
valid_sources[0x26]	117	1			T16	4		T167	11		T96	1
valid_sources[0x27]	135	1			T3	1		T15	40		T173	1
valid_sources[0x28]	332	1			T97	1		T51	1		T15	52
valid_sources[0x29]	165	1			T69	2		T80	1		T15	28
valid_sources[0x2a]	149	1			T46	2		T168	2		T174	1
valid_sources[0x2b]	163	1			T15	38		T175	9		T73	9
valid_sources[0x2c]	225	1			T23	1		T69	1		T96	1
valid_sources[0x2d]	181	1			T80	1		T159	5		T145	3
valid_sources[0x2e]	143	1			T3	1		T46	1		T149	1
valid_sources[0x2f]	147	1			T149	1		T48	1		T97	3
valid_sources[0x30]	175	1			T69	3		T163	1		T96	5
valid_sources[0x31]	142	1			T23	1		T69	1		T97	1
valid_sources[0x32]	143	1			T70	1		T46	1		T144	4
valid_sources[0x33]	148	1			T110	2		T77	18		T149	1
valid_sources[0x34]	153	1			T3	1		T20	2		T167	2
valid_sources[0x35]	130	1			T3	1		T78	1		T51	3
valid_sources[0x36]	164	1			T3	1		T76	6		T15	51
valid_sources[0x37]	165	1			T176	1		T15	39		T177	3
valid_sources[0x38]	241	1			T163	1		T149	1		T33	1
valid_sources[0x39]	194	1			T69	1		T178	10		T179	15
valid_sources[0x3a]	172	1			T23	1		T20	1		T45	1
valid_sources[0x3b]	121	1			T180	2		T15	43		T62	3
valid_sources[0x3c]	113	1			T3	1		T96	1		T148	1
valid_sources[0x3d]	138	1			T20	1		T15	54		T73	1
valid_sources[0x3e]	136	1			T23	1		T144	1		T146	2
valid_sources[0x3f]	129	1			T156	1		T146	1		T181	1
valid_sources[0x40]	161	1			T3	1		T149	1		T144	7
valid_sources[0x41]	147	1			T69	2		T144	1		T156	1
valid_sources[0x42]	154	1			T3	1		T4	2		T19	16
valid_sources[0x43]	153	1			T22	4		T146	1		T182	1
valid_sources[0x44]	150	1			T180	1		T183	1		T15	41
valid_sources[0x45]	165	1			T21	7		T46	2		T96	1
valid_sources[0x46]	115	1			T184	1		T176	1		T15	48
valid_sources[0x47]	255	1			T97	3		T185	6		T166	1
valid_sources[0x48]	224	1			T71	10		T156	1		T50	1
valid_sources[0x49]	195	1			T3	1		T33	2		T151	1
valid_sources[0x4a]	124	1			T44	1		T15	41		T61	2
valid_sources[0x4b]	136	1			T3	1		T69	1		T16	1
valid_sources[0x4c]	168	1			T23	1		T186	8		T146	1
valid_sources[0x4d]	143	1			T152	1		T15	41		T187	1
valid_sources[0x4e]	189	1			T110	2		T152	1		T166	1
valid_sources[0x4f]	119	1			T23	1		T165	3		T152	1
valid_sources[0x50]	150	1			T3	2		T154	1		T15	36
valid_sources[0x51]	122	1			T4	1		T20	1		T15	48
valid_sources[0x52]	121	1			T23	1		T186	20		T145	1
valid_sources[0x53]	182	1			T3	1		T21	6		T79	7
valid_sources[0x54]	195	1			T21	1		T16	10		T145	1
valid_sources[0x55]	104	1			T168	1		T97	1		T176	1
valid_sources[0x56]	135	1			T188	2		T15	55		T86	1
valid_sources[0x57]	195	1			T51	2		T189	3		T190	4
valid_sources[0x58]	132	1			T16	1		T156	1		T146	2
valid_sources[0x59]	170	1			T13	16		T191	6		T146	2
valid_sources[0x5a]	187	1			T156	1		T188	5		T15	34
valid_sources[0x5b]	119	1			T23	1		T71	3		T149	1
valid_sources[0x5c]	171	1			T21	3		T145	1		T154	1
valid_sources[0x5d]	365	1			T15	37		T192	1		T193	1
valid_sources[0x5e]	172	1			T110	7		T156	1		T145	2
valid_sources[0x5f]	186	1			T46	1		T166	1		T15	44
valid_sources[0x60]	108	1			T20	1		T166	1		T15	40
valid_sources[0x61]	222	1			T149	2		T146	1		T166	1
valid_sources[0x62]	200	1			T165	3		T156	1		T15	42
valid_sources[0x63]	131	1			T69	1		T163	1		T33	2
valid_sources[0x64]	158	1			T172	2		T149	1		T33	4
valid_sources[0x65]	172	1			T2	16		T15	48		T192	1
valid_sources[0x66]	199	1			T46	2		T194	9		T39	4
valid_sources[0x67]	147	1			T145	2		T150	2		T171	2
valid_sources[0x68]	185	1			T180	1		T149	1		T41	1
valid_sources[0x69]	105	1			T3	1		T20	1		T15	54
valid_sources[0x6a]	140	1			T45	2		T190	3		T15	46
valid_sources[0x6b]	117	1			T42	7		T16	1		T195	5
valid_sources[0x6c]	186	1			T150	1		T157	9		T15	39
valid_sources[0x6d]	332	1			T23	1		T47	1		T149	2
valid_sources[0x6e]	148	1			T146	1		T150	1		T15	41
valid_sources[0x6f]	169	1			T9	1		T20	1		T70	8
valid_sources[0x70]	185	1			T52	8		T14	64		T46	1
valid_sources[0x71]	225	1			T3	1		T45	3		T156	1
valid_sources[0x72]	158	1			T46	1		T196	5		T15	42
valid_sources[0x73]	152	1			T45	1		T163	1		T145	1
valid_sources[0x74]	97	1			T20	3		T156	1		T15	39
valid_sources[0x75]	183	1			T23	1		T149	1		T145	1
valid_sources[0x76]	139	1			T144	1		T96	3		T50	1
valid_sources[0x77]	217	1			T80	1		T166	1		T15	44
valid_sources[0x78]	143	1			T154	2		T171	4		T197	1
valid_sources[0x79]	201	1			T69	2		T145	2		T96	1
valid_sources[0x7a]	125	1			T69	1		T163	1		T144	1
valid_sources[0x7b]	124	1			T16	1		T145	1		T15	36
valid_sources[0x7c]	154	1			T44	1		T168	1		T96	1
valid_sources[0x7d]	151	1			T146	1		T152	1		T174	1
valid_sources[0x7e]	291	1			T3	1		T198	2		T171	3
valid_sources[0x7f]	152	1			T69	1		T165	5		T50	1
valid_sources[0x80]	145	1			T189	2		T15	35		T192	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7799

1

T2

5

T3

19

T10

18

values[0x0]

all_enables

biggest_size

12837

1

T1

2

T7

1

T69

5

values[0x1]

all_enables

biggest_size

12664

1

T1

1

T7

2

T79

1