Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

55663

1

T2

31

T5

327

T6

242

full_word

28715

1

T2

5

T3

4

T5

37

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	84048	1			T2	36		T3	4		T5	364
auto[TlIntgErrCmd]	108	1			T27	6		T54	3		T55	2
auto[TlIntgErrData]	110	1			T27	8		T54	3		T55	3
auto[TlIntgErrBoth]	112	1			T27	6		T54	4		T55	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26873

1

T2

36

T3

4

T5

364

auto[1]

57505

1

T15

34416

T27

10

T28

579

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	18646	1			T2	31		T5	327		T6	242
auto[TlIntgErrNone]	partial	auto[1]	36718	1			T15	21854		T28	282		T53	643
auto[TlIntgErrNone]	full_word	auto[0]	8074	1			T2	5		T3	4		T5	37
auto[TlIntgErrNone]	full_word	auto[1]	20610	1			T15	12562		T28	297		T53	337
auto[TlIntgErrCmd]	partial	auto[0]	42	1			T27	1		T54	1		T56	5
auto[TlIntgErrCmd]	partial	auto[1]	57	1			T27	4		T54	2		T55	2
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T27	1		T81	1		T124	2
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T81	1		T127	1		T129	1
auto[TlIntgErrData]	partial	auto[0]	52	1			T27	6		T54	1		T55	2
auto[TlIntgErrData]	partial	auto[1]	44	1			T27	2		T54	2		T55	1
auto[TlIntgErrData]	full_word	auto[0]	8	1			T57	1		T81	2		T130	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T122	1		T131	1		T125	2
auto[TlIntgErrBoth]	partial	auto[0]	42	1			T27	2		T54	3		T55	2
auto[TlIntgErrBoth]	partial	auto[1]	62	1			T27	4		T54	1		T55	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T81	1		T132	2		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T124	1		T125	1		T133	2