Unified Coverage Report :: Module :: rom_ctrl

Module : rom_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.99	100.00	98.28	97.26		100.00	79.41

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.99	100.00	98.28	97.26		100.00	79.41

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.99	100.00	98.28	97.26		100.00	79.41

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.20	96.89	92.28	97.68	100.00	98.62	97.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_alert_sender	100.00			100.00
gen_fsm_scramble_enabled.u_checker_fsm	96.51	100.00	98.15	90.00	100.00	100.00	90.91
gen_rom_scramble_enabled.u_rom	97.06	88.24		100.00		100.00	100.00
regs_tlul_assert_device	100.00	100.00				100.00	100.00
rom_ctrl_regs_csr_assert	100.00						100.00
rom_tlul_assert_device	99.18	100.00				100.00	97.55
u_mux	95.24	100.00	85.71			100.00
u_reg_regs	99.72	99.41	99.21	100.00		100.00	100.00
u_tl_adapter_rom	93.10	90.70	82.93	97.66		94.20	100.00
u_tl_rom_h2d_buf	100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rom_ctrl

	Line No.	Total	Covered	Percent
TOTAL		65	65	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	127	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	258	1	1	100.00
CONT_ASSIGN	313	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	425	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
CONT_ASSIGN	431	1	1	100.00
CONT_ASSIGN	432	1	1	100.00
CONT_ASSIGN	433	1	1	100.00
CONT_ASSIGN	438	1	1	100.00
CONT_ASSIGN	442	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
120	1	1
125	1	1
126	1	1
127	1	1
128	1	1
131	1	1
212	1	1
258	1	1
313	1	1
414	8	8
415	8	8
417	8	8
418	8	8
420	8	8
421	8	8
425	1	1
427	1	1
430	1	1
431	1	1
432	1	1
433	1	1
438	1	1
442	1	1

---

Cond Coverage for Module : rom_ctrl

	Total	Covered	Percent
Conditions	58	57	98.28
Logical	58	57	98.28
Non-Logical	0	0
Event	0	0

 LINE       212
 EXPRESSION (rom_tl_i.a_valid ? rom_tl_i.a_address[2+:RomIndexWidth] : '0)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       258
 EXPRESSION (bus_rom_rvalid_raw & ((!internal_alert)))
             ---------1--------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T10
1	1	Covered	T1,T3,T7

 LINE       418
 EXPRESSION (exp_digest_de && (0 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       418
 SUB-EXPRESSION (0 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       418
 EXPRESSION (exp_digest_de && (1 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       418
 SUB-EXPRESSION (1 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       418
 EXPRESSION (exp_digest_de && (2 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       418
 SUB-EXPRESSION (2 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       418
 EXPRESSION (exp_digest_de && (3 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       418
 SUB-EXPRESSION (3 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       418
 EXPRESSION (exp_digest_de && (4 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       418
 SUB-EXPRESSION (4 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       418
 EXPRESSION (exp_digest_de && (5 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       418
 SUB-EXPRESSION (5 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       418
 EXPRESSION (exp_digest_de && (6 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       418
 SUB-EXPRESSION (6 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       418
 EXPRESSION (exp_digest_de && (7 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       418
 SUB-EXPRESSION (7 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       425
 EXPRESSION (rom_integrity_error | reg_integrity_error)
             ---------1---------   ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T26,T27,T28
1	0	Not Covered

 LINE       427
 EXPRESSION (checker_alert | mux_alert)
             ------1------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T10
1	0	Covered	T1,T2,T4

 LINE       438
 EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
             ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T6,T29,T30
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T29,T30

 LINE       442
 EXPRESSION (bus_integrity_error | checker_alert | mux_alert)
             ---------1---------   ------2------   ----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T4,T10
0	1	0	Covered	T1,T2,T4
1	0	0	Covered	T26,T27,T28

---

Toggle Coverage for Module : rom_ctrl

	Total	Covered	Percent
Totals	62	56	90.32
Total Bits	2884	2805	97.26
Total Bits 0->1	1442	1402	97.23
Total Bits 1->0	1442	1403	97.30

Ports	62	56	90.32
Port Bits	2884	2805	97.26
Port Bits 0->1	1442	1402	97.23
Port Bits 1->0	1442	1403	97.30

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rom_cfg_i.cfg[3:0]	No	No		No		INPUT
rom_cfg_i.cfg_en	No	No		No		INPUT
rom_cfg_i.test	No	No		No		INPUT
rom_tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rom_tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
rom_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
rom_tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
rom_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
rom_tl_i.a_data[31:0]	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
rom_tl_i.a_mask[3:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
rom_tl_i.a_address[31:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
rom_tl_i.a_source[7:0]	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
rom_tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rom_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
rom_tl_i.a_opcode[2:0]	Yes	Yes	T1,T4,T7	Yes	T1,T2,T4	INPUT
rom_tl_i.a_valid	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
rom_tl_o.a_ready	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	OUTPUT
rom_tl_o.d_error	Yes	Yes	T7,T9,T11	Yes	T7,T9,T11	OUTPUT
rom_tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	OUTPUT
rom_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T3,T7	Yes	T1,T3,T7	OUTPUT
rom_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_data[31:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	OUTPUT
rom_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_source[7:0]	Yes	Yes	T3,T7,T8	Yes	T3,T7,T8	OUTPUT
rom_tl_o.d_size[1:0]	Yes	Yes	T3,T7,T8	Yes	T3,T7,T8	OUTPUT
rom_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_opcode[0]	Yes	Yes	*T7,*T9,*T11	Yes	T7,T9,T11	OUTPUT
rom_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_valid	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	OUTPUT
regs_tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.instr_type[3:0]	Yes	Yes	T7,T8,T9	Yes	T2,T5,T7	INPUT
regs_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_address[31:0]	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
regs_tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_opcode[2:0]	Yes	Yes	T5,T6,T7	Yes	T2,T5,T7	INPUT
regs_tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_error	Yes	Yes	T7,T9,T11	Yes	T7,T9,T11	OUTPUT
regs_tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T3,*T4	Yes	T1,T3,T4	OUTPUT
regs_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_size[1:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
regs_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
pwrmgr_data_o.good[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
pwrmgr_data_o.done[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T3,T4	OUTPUT
keymgr_data_o.valid	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	OUTPUT
keymgr_data_o.data[255:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
kmac_data_i.error	No	Yes	T2,T5,T17	No		INPUT
kmac_data_i.digest_share1[383:0]	Yes	Yes	T1,T2,T3	Yes	T1,T3,T4	INPUT
kmac_data_i.digest_share0[383:0]	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
kmac_data_i.done	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
kmac_data_i.ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
kmac_data_o.last	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
kmac_data_o.strb[7:0]	No	No		No		OUTPUT
kmac_data_o.data[38:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
kmac_data_o.data[63:39]	No	No		No		OUTPUT
kmac_data_o.valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : rom_ctrl

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	212	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	212	(rom_tl_i.a_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Module : rom_ctrl

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	34	34	100.00	27	79.41
Cover properties	0	0		0
Cover sequences	0	0		0
Total	34	34	100.00	27	79.41

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxOKnown_A	43544639	43372761	0	0
BusRomIndicesMatch_A	43531735	43365933	0	0
FpvSecCmRegWeOnehotCheck_A	43544639	80	0	0
FpvSecCmReqFifoRptrCheck_A	43544639	0	0	0
FpvSecCmReqFifoWptrCheck_A	43544639	0	0	0
FpvSecCmRspFifoRptrCheck_A	43544639	0	0	0
FpvSecCmRspFifoWptrCheck_A	43544639	0	0	0
FpvSecCmSramReqFifoRptrCheck_A	43544639	0	0	0
FpvSecCmSramReqFifoWptrCheck_A	43544639	0	0	0
KeymgrDataODataKnown_A	43544639	7679311	0	0
KeymgrDataODataKnown_AKnownEnable	43544639	43372761	0	0
KeymgrDataOValidKnown_A	43544639	43372761	0	0
KeymgrValidChk_A	43544639	7668652	0	0
KmacDataODataKnown_A	43544639	35556907	0	0
KmacDataODataKnown_AKnownEnable	43544639	43372761	0	0
KmacDataOValidKnown_A	43544639	43372761	0	0
PwrmgrDataChk_A	43544639	7668652	0	0
PwrmgrDataOKnown_A	43544639	43372761	0	0
RegsTlOAReadyKnown_A	43544639	43372761	0	0
RegsTlODDataKnown_A	43544639	1398286	0	0
RegsTlODDataKnown_AKnownEnable	43544639	43372761	0	0
RegsTlODValidKnown_A	43544639	43372761	0	0
RomTlOAReadyKnown_A	43544639	43372761	0	0
RomTlODDataKnown_A	43544639	1802910	0	0
RomTlODDataKnown_AKnownEnable	43544639	43372761	0	0
RomTlODValidKnown_A	43544639	43372761	0	0
StabilityChkKmac_A	43544639	35554303	0	0
StabilityChkkeymgr_A	43544639	7678169	0	0
TlAccessChk_A	43544639	35693450	0	0
gen_asserts_with_scrambling.FpvSecCmCheckerFsmAlert_A	43544639	80	0	0
gen_asserts_with_scrambling.FpvSecCmCompareAddrCtrCheck_A	43544639	0	0	0
gen_asserts_with_scrambling.FpvSecCmCompareFsmAlert_A	43544639	513	0	0
gen_fsm_scramble_enabled_asserts.BusLocalEscChk_A	43544639	66999	0	0
gen_fsm_scramble_enabled_asserts.InvalidStateTerminal_A	43544639	65762	0	0

AlertTxOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43544639	43372761	0	0
T1	624629	621993	0	0
T2	33050	32896	0	0
T3	68539	68232	0	0
T4	115229	113643	0	0
T5	49658	49518	0	0
T6	24912	24850	0	0
T7	372307	372206	0	0
T8	17544	17446	0	0
T9	406273	406058	0	0
T10	382231	379984	0	0

BusRomIndicesMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43531735	43365933	0	0
T1	624001	621740	0	0
T2	33050	32896	0	0
T3	68539	68232	0	0
T4	115229	113643	0	0
T5	49658	49518	0	0
T6	24912	24850	0	0
T7	372307	372206	0	0
T8	17544	17446	0	0
T9	406273	406058	0	0
T10	382153	379960	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43544639	80	0	0
T26	47097	20	0	0
T27	0	10	0	0
T28	0	10	0	0
T31	0	20	0	0
T32	0	20	0	0
T33	313201	0	0	0
T34	359769	0	0	0
T35	253671	0	0	0
T36	18522	0	0	0
T37	52201	0	0	0
T38	236902	0	0	0
T39	25975	0	0	0
T40	17817	0	0	0
T41	17174	0	0	0

FpvSecCmReqFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43544639	0	0	0

FpvSecCmReqFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43544639	0	0	0

FpvSecCmRspFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43544639	0	0	0

FpvSecCmRspFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43544639	0	0	0

FpvSecCmSramReqFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43544639	0	0	0

FpvSecCmSramReqFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43544639	0	0	0

KeymgrDataODataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43544639	7679311	0	0
T1	624629	21870	0	0
T2	33050	11	0	0
T3	68539	2415	0	0
T4	115229	330	0	0
T5	49658	281	0	0
T6	24912	289	0	0
T7	372307	207403	0	0
T8	17544	1049	0	0
T9	406273	183351	0	0
T10	382231	5762	0	0

KeymgrDataODataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	43544639	43372761	0	0
T1	624629	621993	0	0
T2	33050	32896	0	0
T3	68539	68232	0	0
T4	115229	113643	0	0
T5	49658	49518	0	0
T6	24912	24850	0	0
T7	372307	372206	0	0
T8	17544	17446	0	0
T9	406273	406058	0	0
T10	382231	379984	0	0

KeymgrDataOValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43544639	43372761	0	0
T1	624629	621993	0	0
T2	33050	32896	0	0
T3	68539	68232	0	0
T4	115229	113643	0	0
T5	49658	49518	0	0
T6	24912	24850	0	0
T7	372307	372206	0	0
T8	17544	17446	0	0
T9	406273	406058	0	0
T10	382231	379984	0	0

KeymgrValidChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43544639	7668652	0	0
T1	624629	21770	0	0
T2	33050	10	0	0
T3	68539	2411	0	0
T4	115229	288	0	0
T5	49658	280	0	0
T6	24912	288	0	0
T7	372307	207397	0	0
T8	17544	1048	0	0
T9	406273	183342	0	0
T10	382231	5567	0	0

KmacDataODataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43544639	35556907	0	0
T1	624629	598263	0	0
T2	33050	32752	0	0
T3	68539	65504	0	0
T4	115229	112697	0	0
T5	49658	49070	0	0
T6	24912	24500	0	0
T7	372307	164404	0	0
T8	17544	16376	0	0
T9	406273	222134	0	0
T10	382231	372741	0	0

KmacDataODataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	43544639	43372761	0	0
T1	624629	621993	0	0
T2	33050	32896	0	0
T3	68539	68232	0	0
T4	115229	113643	0	0
T5	49658	49518	0	0
T6	24912	24850	0	0
T7	372307	372206	0	0
T8	17544	17446	0	0
T9	406273	406058	0	0
T10	382231	379984	0	0

KmacDataOValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43544639	43372761	0	0
T1	624629	621993	0	0
T2	33050	32896	0	0
T3	68539	68232	0	0
T4	115229	113643	0	0
T5	49658	49518	0	0
T6	24912	24850	0	0
T7	372307	372206	0	0
T8	17544	17446	0	0
T9	406273	406058	0	0
T10	382231	379984	0	0

PwrmgrDataChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43544639	7668652	0	0
T1	624629	21770	0	0
T2	33050	10	0	0
T3	68539	2411	0	0
T4	115229	288	0	0
T5	49658	280	0	0
T6	24912	288	0	0
T7	372307	207397	0	0
T8	17544	1048	0	0
T9	406273	183342	0	0
T10	382231	5567	0	0

PwrmgrDataOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43544639	43372761	0	0
T1	624629	621993	0	0
T2	33050	32896	0	0
T3	68539	68232	0	0
T4	115229	113643	0	0
T5	49658	49518	0	0
T6	24912	24850	0	0
T7	372307	372206	0	0
T8	17544	17446	0	0
T9	406273	406058	0	0
T10	382231	379984	0	0

RegsTlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43544639	43372761	0	0
T1	624629	621993	0	0
T2	33050	32896	0	0
T3	68539	68232	0	0
T4	115229	113643	0	0
T5	49658	49518	0	0
T6	24912	24850	0	0
T7	372307	372206	0	0
T8	17544	17446	0	0
T9	406273	406058	0	0
T10	382231	379984	0	0

RegsTlODDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43544639	1398286	0	0
T1	624629	25	0	0
T2	33050	1	0	0
T3	68539	48	0	0
T4	115229	16	0	0
T5	49658	1	0	0
T6	24912	4	0	0
T7	372307	24689	0	0
T8	17544	16	0	0
T9	406273	18359	0	0
T10	382231	24	0	0

RegsTlODDataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	43544639	43372761	0	0
T1	624629	621993	0	0
T2	33050	32896	0	0
T3	68539	68232	0	0
T4	115229	113643	0	0
T5	49658	49518	0	0
T6	24912	24850	0	0
T7	372307	372206	0	0
T8	17544	17446	0	0
T9	406273	406058	0	0
T10	382231	379984	0	0

RegsTlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43544639	43372761	0	0
T1	624629	621993	0	0
T2	33050	32896	0	0
T3	68539	68232	0	0
T4	115229	113643	0	0
T5	49658	49518	0	0
T6	24912	24850	0	0
T7	372307	372206	0	0
T8	17544	17446	0	0
T9	406273	406058	0	0
T10	382231	379984	0	0

RomTlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43544639	43372761	0	0
T1	624629	621993	0	0
T2	33050	32896	0	0
T3	68539	68232	0	0
T4	115229	113643	0	0
T5	49658	49518	0	0
T6	24912	24850	0	0
T7	372307	372206	0	0
T8	17544	17446	0	0
T9	406273	406058	0	0
T10	382231	379984	0	0

RomTlODDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43544639	1802910	0	0
T1	624629	15	0	0
T2	33050	0	0	0
T3	68539	452	0	0
T4	115229	0	0	0
T5	49658	0	0	0
T6	24912	0	0	0
T7	372307	31967	0	0
T8	17544	34	0	0
T9	406273	101857	0	0
T10	382231	3	0	0
T11	0	59757	0	0
T13	0	334	0	0
T14	0	137001	0	0
T16	0	530	0	0

RomTlODDataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	43544639	43372761	0	0
T1	624629	621993	0	0
T2	33050	32896	0	0
T3	68539	68232	0	0
T4	115229	113643	0	0
T5	49658	49518	0	0
T6	24912	24850	0	0
T7	372307	372206	0	0
T8	17544	17446	0	0
T9	406273	406058	0	0
T10	382231	379984	0	0

RomTlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43544639	43372761	0	0
T1	624629	621993	0	0
T2	33050	32896	0	0
T3	68539	68232	0	0
T4	115229	113643	0	0
T5	49658	49518	0	0
T6	24912	24850	0	0
T7	372307	372206	0	0
T8	17544	17446	0	0
T9	406273	406058	0	0
T10	382231	379984	0	0

StabilityChkKmac_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43544639	35554303	0	0
T1	624629	598226	0	0
T2	33050	32750	0	0
T3	68539	65500	0	0
T4	115229	112677	0	0
T5	49658	49068	0	0
T6	24912	24499	0	0
T7	372307	164393	0	0
T8	17544	16375	0	0
T9	406273	222123	0	0
T10	382231	372712	0	0

StabilityChkkeymgr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43544639	7678169	0	0
T1	624629	21855	0	0
T2	33050	10	0	0
T3	68539	2411	0	0
T4	115229	324	0	0
T5	49658	280	0	0
T6	24912	288	0	0
T7	372307	207397	0	0
T8	17544	1048	0	0
T9	406273	183342	0	0
T10	382231	5751	0	0

TlAccessChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43544639	35693450	0	0
T1	624629	600123	0	0
T2	33050	32885	0	0
T3	68539	65817	0	0
T4	115229	113313	0	0
T5	49658	49237	0	0
T6	24912	24561	0	0
T7	372307	164803	0	0
T8	17544	16397	0	0
T9	406273	222707	0	0
T10	382231	374222	0	0

gen_asserts_with_scrambling.FpvSecCmCheckerFsmAlert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43544639	80	0	0
T26	47097	20	0	0
T27	0	10	0	0
T28	0	10	0	0
T31	0	20	0	0
T32	0	20	0	0
T33	313201	0	0	0
T34	359769	0	0	0
T35	253671	0	0	0
T36	18522	0	0	0
T37	52201	0	0	0
T38	236902	0	0	0
T39	25975	0	0	0
T40	17817	0	0	0
T41	17174	0	0	0

gen_asserts_with_scrambling.FpvSecCmCompareAddrCtrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43544639	0	0	0

gen_asserts_with_scrambling.FpvSecCmCompareFsmAlert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43544639	513	0	0
T1	624629	15	0	0
T2	33050	0	0	0
T3	68539	0	0	0
T4	115229	0	0	0
T5	49658	0	0	0
T6	24912	0	0	0
T7	372307	0	0	0
T8	17544	0	0	0
T9	406273	0	0	0
T10	382231	5	0	0
T24	0	5	0	0
T25	0	5	0	0
T26	0	20	0	0
T33	0	5	0	0
T38	0	5	0	0
T42	0	5	0	0
T43	0	10	0	0
T44	0	11	0	0

gen_fsm_scramble_enabled_asserts.BusLocalEscChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43544639	66999	0	0
T1	624629	808	0	0
T2	33050	33	0	0
T3	68539	0	0	0
T4	115229	486	0	0
T5	49658	36	0	0
T6	24912	0	0	0
T7	372307	0	0	0
T8	17544	0	0	0
T9	406273	0	0	0
T10	382231	874	0	0
T17	0	36	0	0
T23	0	35	0	0
T24	0	612	0	0
T45	0	85	0	0
T46	0	32	0	0

gen_fsm_scramble_enabled_asserts.InvalidStateTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43544639	65762	0	0
T1	624629	785	0	0
T2	33050	32	0	0
T3	68539	0	0	0
T4	115229	472	0	0
T5	49658	35	0	0
T6	24912	0	0	0
T7	372307	0	0	0
T8	17544	0	0	0
T9	406273	0	0	0
T10	382231	855	0	0
T17	0	35	0	0
T23	0	34	0	0
T24	0	597	0	0
T45	0	84	0	0
T46	0	31	0	0