Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	30460	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

266251

1

T1

5

T2

1907

T5

6553

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	93848	1			T1	32		T2	550		T5	2324
values[0x0]	99770	1			T2	726		T5	2450		T6	4066
values[0x1]	103093	1			T2	757		T5	2533		T6	4206

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14252	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

282459

1

T1

23

T2

1967

T5

6952

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1002	1			T2	4		T5	21		T6	55
valid_sources[0x01]	1159	1			T2	4		T5	27		T6	49
valid_sources[0x02]	934	1			T2	20		T5	23		T6	41
valid_sources[0x03]	994	1			T2	1		T5	26		T6	46
valid_sources[0x04]	1512	1			T2	10		T5	26		T6	39
valid_sources[0x05]	963	1			T2	6		T5	36		T6	41
valid_sources[0x06]	1850	1			T2	3		T5	33		T6	44
valid_sources[0x07]	1261	1			T5	37		T6	36		T11	290
valid_sources[0x08]	1129	1			T2	26		T5	31		T6	42
valid_sources[0x09]	1889	1			T2	11		T5	27		T6	44
valid_sources[0x0a]	1052	1			T2	6		T5	33		T6	40
valid_sources[0x0b]	1050	1			T2	6		T5	33		T6	42
valid_sources[0x0c]	1115	1			T2	4		T5	34		T6	50
valid_sources[0x0d]	1076	1			T2	12		T5	27		T6	57
valid_sources[0x0e]	1077	1			T2	19		T5	31		T6	51
valid_sources[0x0f]	1022	1			T2	7		T5	23		T6	53
valid_sources[0x10]	973	1			T2	12		T5	38		T6	43
valid_sources[0x11]	1110	1			T2	2		T5	36		T6	46
valid_sources[0x12]	1028	1			T2	5		T5	20		T6	51
valid_sources[0x13]	1410	1			T2	6		T5	20		T6	51
valid_sources[0x14]	1316	1			T2	7		T5	25		T6	46
valid_sources[0x15]	972	1			T2	6		T5	17		T6	49
valid_sources[0x16]	1064	1			T2	5		T5	29		T6	47
valid_sources[0x17]	982	1			T2	9		T5	21		T6	47
valid_sources[0x18]	1298	1			T2	6		T5	25		T6	48
valid_sources[0x19]	1153	1			T2	8		T5	30		T6	56
valid_sources[0x1a]	1013	1			T2	1		T5	23		T6	56
valid_sources[0x1b]	1016	1			T2	39		T5	18		T6	44
valid_sources[0x1c]	1180	1			T2	8		T5	36		T6	41
valid_sources[0x1d]	1158	1			T2	16		T5	26		T6	31
valid_sources[0x1e]	1635	1			T2	4		T5	34		T6	38
valid_sources[0x1f]	1046	1			T2	4		T5	20		T6	45
valid_sources[0x20]	1142	1			T2	4		T5	34		T6	33
valid_sources[0x21]	1002	1			T2	8		T5	30		T6	41
valid_sources[0x22]	990	1			T2	5		T5	30		T6	38
valid_sources[0x23]	1003	1			T2	10		T5	23		T6	49
valid_sources[0x24]	1630	1			T2	12		T5	28		T6	46
valid_sources[0x25]	1052	1			T2	11		T5	30		T6	46
valid_sources[0x26]	1123	1			T2	7		T5	29		T6	44
valid_sources[0x27]	1081	1			T2	8		T5	23		T6	41
valid_sources[0x28]	1275	1			T2	11		T5	28		T6	55
valid_sources[0x29]	1033	1			T2	6		T5	31		T6	37
valid_sources[0x2a]	1206	1			T2	4		T5	20		T6	55
valid_sources[0x2b]	1099	1			T2	1		T5	24		T6	41
valid_sources[0x2c]	1018	1			T2	15		T5	23		T6	41
valid_sources[0x2d]	1014	1			T2	5		T5	38		T6	37
valid_sources[0x2e]	1272	1			T2	6		T5	31		T6	43
valid_sources[0x2f]	971	1			T2	11		T5	26		T6	40
valid_sources[0x30]	1163	1			T2	2		T5	33		T6	42
valid_sources[0x31]	1023	1			T2	1		T5	27		T6	57
valid_sources[0x32]	1004	1			T5	31		T6	38		T9	1
valid_sources[0x33]	1100	1			T2	16		T5	31		T6	48
valid_sources[0x34]	974	1			T2	1		T5	25		T6	36
valid_sources[0x35]	1044	1			T2	1		T5	28		T6	50
valid_sources[0x36]	1340	1			T2	1		T5	35		T6	34
valid_sources[0x37]	941	1			T1	4		T2	5		T5	23
valid_sources[0x38]	1030	1			T2	8		T5	20		T6	40
valid_sources[0x39]	983	1			T2	6		T5	38		T6	56
valid_sources[0x3a]	1034	1			T2	18		T5	28		T6	37
valid_sources[0x3b]	1012	1			T2	1		T5	32		T6	50
valid_sources[0x3c]	1101	1			T2	25		T5	22		T6	53
valid_sources[0x3d]	1125	1			T2	3		T5	27		T6	45
valid_sources[0x3e]	1418	1			T5	39		T6	46		T13	28
valid_sources[0x3f]	1097	1			T2	2		T5	32		T6	52
valid_sources[0x40]	984	1			T2	2		T5	22		T6	38
valid_sources[0x41]	1017	1			T2	11		T5	24		T6	47
valid_sources[0x42]	1036	1			T2	14		T5	23		T6	49
valid_sources[0x43]	1020	1			T2	20		T5	33		T6	45
valid_sources[0x44]	1901	1			T2	13		T5	22		T6	41
valid_sources[0x45]	1039	1			T2	27		T5	30		T6	43
valid_sources[0x46]	1351	1			T2	6		T5	24		T6	49
valid_sources[0x47]	1179	1			T2	3		T5	34		T6	37
valid_sources[0x48]	973	1			T2	6		T5	33		T6	40
valid_sources[0x49]	2256	1			T2	3		T5	32		T6	47
valid_sources[0x4a]	1048	1			T2	8		T5	31		T6	54
valid_sources[0x4b]	1439	1			T2	10		T5	37		T6	47
valid_sources[0x4c]	1183	1			T2	11		T5	37		T6	38
valid_sources[0x4d]	1036	1			T2	18		T5	22		T6	40
valid_sources[0x4e]	1169	1			T2	8		T5	23		T6	47
valid_sources[0x4f]	1029	1			T2	1		T5	30		T6	52
valid_sources[0x50]	1953	1			T2	5		T5	27		T6	43
valid_sources[0x51]	1628	1			T2	17		T5	30		T6	50
valid_sources[0x52]	1442	1			T2	22		T5	21		T6	37
valid_sources[0x53]	1613	1			T5	28		T6	62		T13	11
valid_sources[0x54]	1096	1			T2	5		T5	33		T6	31
valid_sources[0x55]	1002	1			T2	1		T5	27		T6	40
valid_sources[0x56]	984	1			T2	3		T5	27		T6	43
valid_sources[0x57]	975	1			T2	4		T5	23		T6	47
valid_sources[0x58]	1415	1			T2	13		T5	23		T6	42
valid_sources[0x59]	1209	1			T2	13		T5	29		T6	56
valid_sources[0x5a]	967	1			T2	5		T5	26		T6	51
valid_sources[0x5b]	940	1			T2	2		T5	19		T6	37
valid_sources[0x5c]	1032	1			T2	11		T5	28		T6	43
valid_sources[0x5d]	995	1			T2	24		T5	26		T6	40
valid_sources[0x5e]	1012	1			T2	3		T5	29		T6	38
valid_sources[0x5f]	2316	1			T2	6		T5	36		T6	59
valid_sources[0x60]	1042	1			T2	8		T5	33		T6	49
valid_sources[0x61]	1057	1			T2	6		T5	30		T6	37
valid_sources[0x62]	1318	1			T2	3		T5	32		T6	47
valid_sources[0x63]	1516	1			T2	1		T5	41		T6	43
valid_sources[0x64]	1047	1			T2	13		T5	15		T6	43
valid_sources[0x65]	1057	1			T2	24		T5	26		T6	43
valid_sources[0x66]	1049	1			T2	11		T5	27		T6	44
valid_sources[0x67]	997	1			T2	3		T5	25		T6	38
valid_sources[0x68]	1061	1			T2	14		T5	38		T6	32
valid_sources[0x69]	1217	1			T2	7		T5	22		T6	44
valid_sources[0x6a]	1302	1			T2	1		T5	24		T6	45
valid_sources[0x6b]	976	1			T2	9		T5	24		T6	52
valid_sources[0x6c]	1169	1			T2	4		T5	43		T6	61
valid_sources[0x6d]	1058	1			T2	2		T5	18		T6	48
valid_sources[0x6e]	1068	1			T2	9		T5	36		T6	55
valid_sources[0x6f]	976	1			T2	7		T5	21		T6	44
valid_sources[0x70]	1064	1			T2	2		T5	25		T6	44
valid_sources[0x71]	1104	1			T2	8		T5	37		T6	45
valid_sources[0x72]	1630	1			T2	3		T5	21		T6	53
valid_sources[0x73]	1124	1			T5	31		T6	47		T13	24
valid_sources[0x74]	1216	1			T2	8		T5	25		T6	56
valid_sources[0x75]	936	1			T2	3		T5	24		T6	41
valid_sources[0x76]	1048	1			T2	4		T5	17		T6	46
valid_sources[0x77]	1014	1			T2	4		T5	41		T6	42
valid_sources[0x78]	979	1			T2	7		T5	24		T6	40
valid_sources[0x79]	956	1			T2	2		T5	29		T6	48
valid_sources[0x7a]	1066	1			T5	29		T6	43		T13	19
valid_sources[0x7b]	1196	1			T2	2		T5	21		T6	43
valid_sources[0x7c]	1009	1			T2	15		T5	26		T6	38
valid_sources[0x7d]	1095	1			T2	7		T5	29		T6	48
valid_sources[0x7e]	985	1			T2	5		T5	21		T6	44
valid_sources[0x7f]	1125	1			T2	5		T5	24		T6	30
valid_sources[0x80]	1312	1			T2	9		T5	24		T6	42

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

68862

1

T1

5

T2

453

T5

1714

values[0x0]

all_enables

biggest_size

98872

1

T2

721

T5

2424

T6

4038

values[0x1]

all_enables

biggest_size

98517

1

T2

733

T5

2415

T6

4058

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	27598	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

233781

1

T1

7

T2

1125

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	71082	1			T1	16		T2	332		T3	1
values[0x0]	88700	1			T2	416		T5	2004		T6	3034
values[0x1]	101597	1			T2	513		T5	2286		T6	3465

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14798	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

246581

1

T1

10

T2

1194

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1324	1			T5	16		T6	40		T11	22
valid_sources[0x01]	1162	1			T5	12		T6	38		T13	10
valid_sources[0x02]	957	1			T5	25		T6	28		T11	110
valid_sources[0x03]	982	1			T5	22		T6	41		T11	56
valid_sources[0x04]	830	1			T5	30		T6	27		T11	3
valid_sources[0x05]	1061	1			T5	23		T6	25		T11	6
valid_sources[0x06]	1017	1			T5	18		T6	29		T13	18
valid_sources[0x07]	979	1			T5	25		T6	24		T13	42
valid_sources[0x08]	1059	1			T5	22		T6	32		T9	1
valid_sources[0x09]	980	1			T5	31		T6	46		T9	1
valid_sources[0x0a]	1054	1			T5	35		T6	25		T11	3
valid_sources[0x0b]	1055	1			T2	4		T5	22		T6	30
valid_sources[0x0c]	1036	1			T5	25		T6	32		T13	26
valid_sources[0x0d]	1158	1			T5	20		T6	28		T11	158
valid_sources[0x0e]	1196	1			T5	27		T6	36		T7	1
valid_sources[0x0f]	1101	1			T1	4		T5	29		T6	38
valid_sources[0x10]	1003	1			T5	17		T6	39		T11	1
valid_sources[0x11]	932	1			T5	17		T6	41		T11	2
valid_sources[0x12]	772	1			T5	19		T6	45		T7	1
valid_sources[0x13]	870	1			T5	27		T6	39		T11	4
valid_sources[0x14]	798	1			T5	16		T6	34		T11	2
valid_sources[0x15]	750	1			T5	11		T6	31		T13	28
valid_sources[0x16]	850	1			T5	21		T6	38		T11	1
valid_sources[0x17]	1007	1			T5	26		T6	44		T11	55
valid_sources[0x18]	1050	1			T5	30		T6	33		T11	30
valid_sources[0x19]	956	1			T5	18		T6	33		T11	4
valid_sources[0x1a]	996	1			T5	20		T6	30		T11	2
valid_sources[0x1b]	849	1			T5	35		T6	24		T11	2
valid_sources[0x1c]	955	1			T5	22		T6	30		T11	4
valid_sources[0x1d]	993	1			T5	19		T6	40		T11	1
valid_sources[0x1e]	917	1			T5	14		T6	31		T11	1
valid_sources[0x1f]	796	1			T5	18		T6	31		T11	5
valid_sources[0x20]	1099	1			T5	22		T6	24		T11	4
valid_sources[0x21]	921	1			T5	22		T6	41		T11	4
valid_sources[0x22]	1316	1			T5	20		T6	38		T11	107
valid_sources[0x23]	1064	1			T5	28		T6	43		T11	1
valid_sources[0x24]	1000	1			T5	26		T6	33		T11	2
valid_sources[0x25]	955	1			T5	25		T6	33		T13	24
valid_sources[0x26]	1059	1			T2	3		T5	28		T6	40
valid_sources[0x27]	1393	1			T5	16		T6	26		T11	99
valid_sources[0x28]	968	1			T5	13		T6	46		T11	3
valid_sources[0x29]	951	1			T5	28		T6	37		T11	224
valid_sources[0x2a]	959	1			T2	15		T5	32		T6	32
valid_sources[0x2b]	744	1			T4	1		T5	29		T6	28
valid_sources[0x2c]	1376	1			T5	29		T6	27		T11	237
valid_sources[0x2d]	875	1			T5	24		T6	38		T13	2
valid_sources[0x2e]	1117	1			T5	17		T6	39		T11	7
valid_sources[0x2f]	1219	1			T5	26		T6	26		T13	11
valid_sources[0x30]	1056	1			T5	28		T6	28		T11	5
valid_sources[0x31]	1172	1			T5	23		T6	29		T11	5
valid_sources[0x32]	978	1			T5	18		T6	41		T11	4
valid_sources[0x33]	1256	1			T5	25		T6	36		T11	2
valid_sources[0x34]	927	1			T5	25		T6	28		T11	32
valid_sources[0x35]	1175	1			T2	1		T5	26		T6	29
valid_sources[0x36]	1083	1			T5	15		T6	28		T11	1
valid_sources[0x37]	1010	1			T5	13		T6	33		T11	1
valid_sources[0x38]	832	1			T5	20		T6	35		T11	51
valid_sources[0x39]	1578	1			T5	20		T6	36		T10	1
valid_sources[0x3a]	748	1			T5	23		T6	35		T13	17
valid_sources[0x3b]	869	1			T5	20		T6	28		T13	6
valid_sources[0x3c]	1241	1			T5	29		T6	37		T11	2
valid_sources[0x3d]	1027	1			T5	22		T6	28		T11	2
valid_sources[0x3e]	902	1			T5	22		T6	42		T11	3
valid_sources[0x3f]	1128	1			T2	41		T5	25		T6	31
valid_sources[0x40]	795	1			T5	29		T6	31		T11	5
valid_sources[0x41]	982	1			T1	1		T5	30		T6	30
valid_sources[0x42]	989	1			T2	114		T5	30		T6	28
valid_sources[0x43]	816	1			T5	19		T6	30		T13	2
valid_sources[0x44]	1075	1			T5	23		T6	38		T47	19
valid_sources[0x45]	1291	1			T5	25		T6	25		T11	18
valid_sources[0x46]	866	1			T5	12		T6	39		T13	35
valid_sources[0x47]	936	1			T2	150		T5	20		T6	38
valid_sources[0x48]	1165	1			T5	21		T6	32		T11	6
valid_sources[0x49]	1245	1			T2	1		T5	20		T6	31
valid_sources[0x4a]	955	1			T5	28		T6	32		T13	43
valid_sources[0x4b]	823	1			T5	24		T6	30		T11	6
valid_sources[0x4c]	1079	1			T5	16		T6	32		T11	107
valid_sources[0x4d]	1098	1			T5	22		T6	46		T11	2
valid_sources[0x4e]	1095	1			T5	19		T6	31		T11	62
valid_sources[0x4f]	1095	1			T5	26		T6	38		T11	3
valid_sources[0x50]	992	1			T5	28		T6	34		T11	2
valid_sources[0x51]	912	1			T5	19		T6	52		T11	19
valid_sources[0x52]	851	1			T5	21		T6	41		T11	13
valid_sources[0x53]	855	1			T5	20		T6	28		T9	2
valid_sources[0x54]	1052	1			T5	31		T6	32		T11	108
valid_sources[0x55]	1062	1			T5	28		T6	39		T11	1
valid_sources[0x56]	770	1			T5	19		T6	36		T9	1
valid_sources[0x57]	907	1			T5	19		T6	32		T13	34
valid_sources[0x58]	1118	1			T5	31		T6	36		T11	191
valid_sources[0x59]	1212	1			T5	27		T6	25		T9	1
valid_sources[0x5a]	803	1			T5	33		T6	35		T11	3
valid_sources[0x5b]	1048	1			T5	28		T6	32		T7	1
valid_sources[0x5c]	984	1			T5	16		T6	42		T11	1
valid_sources[0x5d]	1116	1			T5	24		T6	26		T9	1
valid_sources[0x5e]	918	1			T5	22		T6	31		T11	3
valid_sources[0x5f]	825	1			T5	25		T6	33		T13	6
valid_sources[0x60]	901	1			T5	31		T6	33		T11	2
valid_sources[0x61]	825	1			T5	26		T6	34		T11	1
valid_sources[0x62]	1233	1			T5	22		T6	31		T11	172
valid_sources[0x63]	1150	1			T5	21		T6	36		T11	55
valid_sources[0x64]	925	1			T2	30		T5	21		T6	28
valid_sources[0x65]	1691	1			T5	16		T6	39		T11	48
valid_sources[0x66]	1021	1			T5	29		T6	31		T7	1
valid_sources[0x67]	736	1			T2	13		T5	32		T6	35
valid_sources[0x68]	826	1			T5	17		T6	42		T11	4
valid_sources[0x69]	1023	1			T5	21		T6	37		T11	202
valid_sources[0x6a]	1136	1			T5	25		T6	39		T13	20
valid_sources[0x6b]	1045	1			T5	30		T6	40		T11	6
valid_sources[0x6c]	992	1			T5	23		T6	45		T13	70
valid_sources[0x6d]	754	1			T5	20		T6	33		T11	7
valid_sources[0x6e]	992	1			T5	26		T6	33		T11	55
valid_sources[0x6f]	844	1			T5	19		T6	41		T13	39
valid_sources[0x70]	1424	1			T5	15		T6	42		T11	236
valid_sources[0x71]	1050	1			T5	26		T6	36		T13	13
valid_sources[0x72]	1014	1			T5	36		T6	28		T11	3
valid_sources[0x73]	1042	1			T5	20		T6	21		T11	2
valid_sources[0x74]	856	1			T5	26		T6	33		T11	1
valid_sources[0x75]	1127	1			T2	4		T5	31		T6	44
valid_sources[0x76]	1013	1			T5	27		T6	39		T11	1
valid_sources[0x77]	883	1			T5	26		T6	29		T13	56
valid_sources[0x78]	894	1			T5	14		T6	26		T11	3
valid_sources[0x79]	1128	1			T5	32		T6	38		T11	2
valid_sources[0x7a]	812	1			T2	1		T5	29		T6	31
valid_sources[0x7b]	969	1			T5	16		T6	39		T11	7
valid_sources[0x7c]	1099	1			T5	22		T6	35		T25	1
valid_sources[0x7d]	864	1			T5	19		T6	20		T13	15
valid_sources[0x7e]	1210	1			T5	25		T6	36		T11	181
valid_sources[0x7f]	977	1			T5	30		T6	34		T13	29
valid_sources[0x80]	1050	1			T5	19		T6	22		T11	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

60598

1

T1

7

T2

294

T3

1

values[0x0]

all_enables

biggest_size

86414

1

T2

407

T5

1977

T6

2987

values[0x1]

all_enables

biggest_size

86769

1

T2

424

T5

1912

T6

3062