Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

505964

1

T1

27

T2

2973

T5

12135

full_word

311189

1

T1

5

T2

2177

T5

7544

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	816863	1			T1	32		T2	5150		T5	19679
auto[TlIntgErrCmd]	87	1			T62	7		T63	4		T64	5
auto[TlIntgErrData]	106	1			T62	9		T63	1		T64	3
auto[TlIntgErrBoth]	97	1			T62	4		T63	5		T64	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

149183

1

T1

32

T2

924

T5

3491

auto[1]

667970

1

T2

4226

T5

16188

T6

23147

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	73583	1			T1	27		T2	420		T5	1639
auto[TlIntgErrNone]	partial	auto[1]	432109	1			T2	2553		T5	10496		T6	13807
auto[TlIntgErrNone]	full_word	auto[0]	75459	1			T1	5		T2	504		T5	1852
auto[TlIntgErrNone]	full_word	auto[1]	235712	1			T2	1673		T5	5692		T6	9340
auto[TlIntgErrCmd]	partial	auto[0]	36	1			T62	1		T63	1		T64	2
auto[TlIntgErrCmd]	partial	auto[1]	46	1			T62	6		T63	3		T64	2
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T123	1		T124	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T64	1		T122	1		T124	1
auto[TlIntgErrData]	partial	auto[0]	59	1			T62	5		T63	1		T64	2
auto[TlIntgErrData]	partial	auto[1]	36	1			T62	4		T121	4		T116	1
auto[TlIntgErrData]	full_word	auto[0]	5	1			T64	1		T125	1		T126	2
auto[TlIntgErrData]	full_word	auto[1]	6	1			T127	2		T128	1		T129	2
auto[TlIntgErrBoth]	partial	auto[0]	38	1			T62	1		T63	2		T121	1
auto[TlIntgErrBoth]	partial	auto[1]	57	1			T62	3		T63	3		T64	2
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T124	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	1	1			T124	1		-	-		-	-