Unified Coverage Report :: Module :: rom_ctrl_regs_csr_assert_fpv

Module : rom_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rom_ctrl_csr_assert_0/rom_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rom_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rom_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.99	100.00	98.28	97.26		100.00	79.41	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rom_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	49747665	370359	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49747665	370359	0	0
T2	116623	1904	0	0
T3	49956	0	0	0
T4	33152	0	0	0
T5	357750	9101	0	0
T6	472383	13132	0	0
T7	24942	0	0	0
T8	25937	0	0	0
T9	50562	0	0	0
T10	16752	0	0	0
T11	337803	12476	0	0
T13	0	7859	0	0
T17	0	1875	0	0
T47	0	12641	0	0
T59	0	16620	0	0
T60	0	4472	0	0
T61	0	5069	0	0