| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 97.51 | 96.89 | 92.28 | 97.68 | 100.00 | 98.62 | 98.05 | 99.06 |
| T307 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_alert_test.1634867589 | Aug 21 08:13:40 AM UTC 24 | Aug 21 08:13:52 AM UTC 24 | 174483095 ps | ||
| T308 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_max_throughput_chk.3350515805 | Aug 21 08:13:40 AM UTC 24 | Aug 21 08:13:53 AM UTC 24 | 919955183 ps | ||
| T67 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2256359786 | Aug 21 08:09:12 AM UTC 24 | Aug 21 08:13:53 AM UTC 24 | 17311830118 ps | ||
| T309 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1713618294 | Aug 21 08:10:12 AM UTC 24 | Aug 21 08:13:54 AM UTC 24 | 46656869130 ps | ||
| T310 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2650329042 | Aug 21 08:08:19 AM UTC 24 | Aug 21 08:13:55 AM UTC 24 | 9734000353 ps | ||
| T311 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all.3463878069 | Aug 21 08:12:56 AM UTC 24 | Aug 21 08:13:56 AM UTC 24 | 1551015418 ps | ||
| T312 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.3054497455 | Aug 21 08:12:10 AM UTC 24 | Aug 21 08:13:58 AM UTC 24 | 7703087752 ps | ||
| T313 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.3933866430 | Aug 21 08:11:25 AM UTC 24 | Aug 21 08:13:58 AM UTC 24 | 56323932636 ps | ||
| T314 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_max_throughput_chk.3981234865 | Aug 21 08:13:46 AM UTC 24 | Aug 21 08:13:59 AM UTC 24 | 264082628 ps | ||
| T315 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_kmac_err_chk.932576891 | Aug 21 08:13:33 AM UTC 24 | Aug 21 08:14:00 AM UTC 24 | 2059057495 ps | ||
| T316 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_kmac_err_chk.2487370337 | Aug 21 08:13:25 AM UTC 24 | Aug 21 08:14:01 AM UTC 24 | 1829932050 ps | ||
| T317 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.3698721907 | Aug 21 08:09:03 AM UTC 24 | Aug 21 08:14:01 AM UTC 24 | 4249676176 ps | ||
| T318 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.3961847840 | Aug 21 08:12:21 AM UTC 24 | Aug 21 08:14:02 AM UTC 24 | 5300786335 ps | ||
| T319 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_alert_test.1455108497 | Aug 21 08:13:45 AM UTC 24 | Aug 21 08:14:02 AM UTC 24 | 998574216 ps | ||
| T320 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.2858966467 | Aug 21 08:11:31 AM UTC 24 | Aug 21 08:14:03 AM UTC 24 | 2491934913 ps | ||
| T321 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_alert_test.551561896 | Aug 21 08:13:50 AM UTC 24 | Aug 21 08:14:05 AM UTC 24 | 1029950778 ps | ||
| T322 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_kmac_err_chk.78129990 | Aug 21 08:13:43 AM UTC 24 | Aug 21 08:14:06 AM UTC 24 | 2145649166 ps | ||
| T323 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.1536984895 | Aug 21 08:09:48 AM UTC 24 | Aug 21 08:14:06 AM UTC 24 | 23460039926 ps | ||
| T324 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all.3442475513 | Aug 21 08:13:40 AM UTC 24 | Aug 21 08:14:06 AM UTC 24 | 1064667005 ps | ||
| T325 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.1443447329 | Aug 21 08:12:54 AM UTC 24 | Aug 21 08:14:09 AM UTC 24 | 1335749035 ps | ||
| T326 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.1262706732 | Aug 21 08:10:28 AM UTC 24 | Aug 21 08:14:09 AM UTC 24 | 4517172756 ps | ||
| T327 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_kmac_err_chk.3756384635 | Aug 21 08:13:47 AM UTC 24 | Aug 21 08:14:11 AM UTC 24 | 663594273 ps | ||
| T328 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.2099736591 | Aug 21 08:12:30 AM UTC 24 | Aug 21 08:14:15 AM UTC 24 | 2000670948 ps | ||
| T329 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all.2690464485 | Aug 21 08:13:46 AM UTC 24 | Aug 21 08:14:16 AM UTC 24 | 536794213 ps | ||
| T330 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.2547858596 | Aug 21 08:08:59 AM UTC 24 | Aug 21 08:14:25 AM UTC 24 | 11345218191 ps | ||
| T331 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.2179579228 | Aug 21 08:13:11 AM UTC 24 | Aug 21 08:14:31 AM UTC 24 | 1063049624 ps | ||
| T332 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.1439355224 | Aug 21 08:11:55 AM UTC 24 | Aug 21 08:14:39 AM UTC 24 | 9408665420 ps | ||
| T333 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.224323621 | Aug 21 08:09:43 AM UTC 24 | Aug 21 08:14:44 AM UTC 24 | 4985689130 ps | ||
| T334 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.3601066694 | Aug 21 08:13:01 AM UTC 24 | Aug 21 08:14:57 AM UTC 24 | 2025271662 ps | ||
| T335 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.3131554555 | Aug 21 08:08:50 AM UTC 24 | Aug 21 08:14:58 AM UTC 24 | 24076982170 ps | ||
| T336 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.2316591355 | Aug 21 08:09:31 AM UTC 24 | Aug 21 08:15:04 AM UTC 24 | 6518728664 ps | ||
| T337 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.2075191230 | Aug 21 08:10:36 AM UTC 24 | Aug 21 08:15:21 AM UTC 24 | 7256260284 ps | ||
| T338 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.3955704691 | Aug 21 08:11:10 AM UTC 24 | Aug 21 08:15:24 AM UTC 24 | 55501377466 ps | ||
| T339 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3207962602 | Aug 21 08:09:40 AM UTC 24 | Aug 21 08:15:29 AM UTC 24 | 4531728216 ps | ||
| T340 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.3796532636 | Aug 21 08:12:25 AM UTC 24 | Aug 21 08:15:31 AM UTC 24 | 2227489789 ps | ||
| T341 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.2847524238 | Aug 21 08:12:58 AM UTC 24 | Aug 21 08:15:36 AM UTC 24 | 9317458062 ps | ||
| T342 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.2830370255 | Aug 21 08:11:28 AM UTC 24 | Aug 21 08:15:37 AM UTC 24 | 7587455730 ps | ||
| T343 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.1074776521 | Aug 21 08:10:50 AM UTC 24 | Aug 21 08:15:40 AM UTC 24 | 15686850369 ps | ||
| T344 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.3752490829 | Aug 21 08:12:34 AM UTC 24 | Aug 21 08:15:41 AM UTC 24 | 2085588848 ps | ||
| T345 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.2590762224 | Aug 21 08:13:16 AM UTC 24 | Aug 21 08:15:41 AM UTC 24 | 3549438786 ps | ||
| T346 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.862261529 | Aug 21 08:12:14 AM UTC 24 | Aug 21 08:15:41 AM UTC 24 | 3734889838 ps | ||
| T347 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.619447186 | Aug 21 08:13:47 AM UTC 24 | Aug 21 08:15:51 AM UTC 24 | 7786220634 ps | ||
| T348 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.638133077 | Aug 21 08:08:52 AM UTC 24 | Aug 21 08:16:04 AM UTC 24 | 19367194831 ps | ||
| T349 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.2057834522 | Aug 21 08:12:17 AM UTC 24 | Aug 21 08:16:26 AM UTC 24 | 5131249202 ps | ||
| T350 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.1568777201 | Aug 21 08:13:25 AM UTC 24 | Aug 21 08:16:37 AM UTC 24 | 5301953087 ps | ||
| T351 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.257320114 | Aug 21 08:13:45 AM UTC 24 | Aug 21 08:16:38 AM UTC 24 | 7928236607 ps | ||
| T352 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.643948197 | Aug 21 08:12:12 AM UTC 24 | Aug 21 08:16:42 AM UTC 24 | 5138397461 ps | ||
| T353 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.285760910 | Aug 21 08:11:44 AM UTC 24 | Aug 21 08:16:44 AM UTC 24 | 17734785833 ps | ||
| T354 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.4138680347 | Aug 21 08:11:31 AM UTC 24 | Aug 21 08:16:46 AM UTC 24 | 14549761455 ps | ||
| T20 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.3720426936 | Aug 21 08:13:50 AM UTC 24 | Aug 21 08:16:52 AM UTC 24 | 12405609332 ps | ||
| T355 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.594521962 | Aug 21 08:13:24 AM UTC 24 | Aug 21 08:16:52 AM UTC 24 | 15446687467 ps | ||
| T356 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1097008615 | Aug 21 08:13:08 AM UTC 24 | Aug 21 08:16:53 AM UTC 24 | 42146846634 ps | ||
| T357 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.3604352620 | Aug 21 08:13:15 AM UTC 24 | Aug 21 08:17:08 AM UTC 24 | 16946222684 ps | ||
| T160 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.1257898969 | Aug 21 08:13:36 AM UTC 24 | Aug 21 08:17:11 AM UTC 24 | 3288302827 ps | ||
| T358 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.1217882188 | Aug 21 08:10:17 AM UTC 24 | Aug 21 08:17:25 AM UTC 24 | 191476594234 ps | ||
| T359 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.2921385996 | Aug 21 08:11:59 AM UTC 24 | Aug 21 08:17:30 AM UTC 24 | 17750177059 ps | ||
| T360 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.2738618754 | Aug 21 08:12:46 AM UTC 24 | Aug 21 08:17:36 AM UTC 24 | 9252055824 ps | ||
| T361 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.2659858981 | Aug 21 08:13:30 AM UTC 24 | Aug 21 08:17:59 AM UTC 24 | 21908155486 ps | ||
| T362 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.2345723679 | Aug 21 08:11:54 AM UTC 24 | Aug 21 08:18:03 AM UTC 24 | 4768567062 ps | ||
| T363 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3891655618 | Aug 21 08:08:19 AM UTC 24 | Aug 21 08:18:31 AM UTC 24 | 119298909285 ps | ||
| T364 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1499760136 | Aug 21 08:10:56 AM UTC 24 | Aug 21 08:18:33 AM UTC 24 | 12228127117 ps | ||
| T365 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3245215155 | Aug 21 08:13:41 AM UTC 24 | Aug 21 08:19:23 AM UTC 24 | 14955505144 ps | ||
| T366 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.782704590 | Aug 21 08:12:42 AM UTC 24 | Aug 21 08:21:59 AM UTC 24 | 31387420388 ps | ||
| T367 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3378848592 | Aug 21 08:13:55 AM UTC 24 | Aug 21 08:14:06 AM UTC 24 | 664726977 ps | ||
| T368 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3542817503 | Aug 21 08:13:57 AM UTC 24 | Aug 21 08:14:06 AM UTC 24 | 175244173 ps | ||
| T85 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2269988467 | Aug 21 08:13:57 AM UTC 24 | Aug 21 08:14:10 AM UTC 24 | 177534866 ps | ||
| T86 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_rw.482069976 | Aug 21 08:13:59 AM UTC 24 | Aug 21 08:14:12 AM UTC 24 | 3103153598 ps | ||
| T87 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3265989292 | Aug 21 08:14:02 AM UTC 24 | Aug 21 08:14:13 AM UTC 24 | 719476086 ps | ||
| T369 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3137369577 | Aug 21 08:13:54 AM UTC 24 | Aug 21 08:14:14 AM UTC 24 | 1275212060 ps | ||
| T88 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.280431117 | Aug 21 08:14:01 AM UTC 24 | Aug 21 08:14:14 AM UTC 24 | 1031735034 ps | ||
| T370 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_walk.944070323 | Aug 21 08:14:04 AM UTC 24 | Aug 21 08:14:16 AM UTC 24 | 170974493 ps | ||
| T131 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1031219459 | Aug 21 08:14:00 AM UTC 24 | Aug 21 08:14:16 AM UTC 24 | 3539049157 ps | ||
| T89 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2693592925 | Aug 21 08:14:02 AM UTC 24 | Aug 21 08:14:18 AM UTC 24 | 1081097738 ps | ||
| T371 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2205980949 | Aug 21 08:14:03 AM UTC 24 | Aug 21 08:14:18 AM UTC 24 | 249504653 ps | ||
| T90 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1638162395 | Aug 21 08:14:08 AM UTC 24 | Aug 21 08:14:18 AM UTC 24 | 312021013 ps | ||
| T132 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2655616455 | Aug 21 08:14:08 AM UTC 24 | Aug 21 08:14:20 AM UTC 24 | 3306457806 ps | ||
| T372 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.4035920630 | Aug 21 08:14:06 AM UTC 24 | Aug 21 08:14:20 AM UTC 24 | 988652642 ps | ||
| T124 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1666761895 | Aug 21 08:14:08 AM UTC 24 | Aug 21 08:14:20 AM UTC 24 | 612744005 ps | ||
| T373 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1176610439 | Aug 21 08:14:08 AM UTC 24 | Aug 21 08:14:21 AM UTC 24 | 952980419 ps | ||
| T374 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_walk.4060021229 | Aug 21 08:14:13 AM UTC 24 | Aug 21 08:14:22 AM UTC 24 | 169063376 ps | ||
| T375 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.158064103 | Aug 21 08:14:10 AM UTC 24 | Aug 21 08:14:25 AM UTC 24 | 1348394472 ps | ||
| T91 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3569142221 | Aug 21 08:14:17 AM UTC 24 | Aug 21 08:14:28 AM UTC 24 | 989782038 ps | ||
| T376 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.4280710931 | Aug 21 08:14:17 AM UTC 24 | Aug 21 08:14:29 AM UTC 24 | 344139458 ps | ||
| T133 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3508660077 | Aug 21 08:14:16 AM UTC 24 | Aug 21 08:14:30 AM UTC 24 | 204575235 ps | ||
| T377 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_rw.92225740 | Aug 21 08:14:15 AM UTC 24 | Aug 21 08:14:30 AM UTC 24 | 3637961752 ps | ||
| T378 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3115697502 | Aug 21 08:14:14 AM UTC 24 | Aug 21 08:14:30 AM UTC 24 | 699081178 ps | ||
| T379 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_errors.445854370 | Aug 21 08:14:11 AM UTC 24 | Aug 21 08:14:30 AM UTC 24 | 1540720970 ps | ||
| T92 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2218068720 | Aug 21 08:14:07 AM UTC 24 | Aug 21 08:14:32 AM UTC 24 | 271094984 ps | ||
| T93 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.4110737108 | Aug 21 08:14:17 AM UTC 24 | Aug 21 08:14:33 AM UTC 24 | 250179620 ps | ||
| T380 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_mem_walk.174400058 | Aug 21 08:14:21 AM UTC 24 | Aug 21 08:14:34 AM UTC 24 | 339795630 ps | ||
| T381 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.145502527 | Aug 21 08:14:14 AM UTC 24 | Aug 21 08:14:35 AM UTC 24 | 2065576050 ps | ||
| T382 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3374922093 | Aug 21 08:14:21 AM UTC 24 | Aug 21 08:14:36 AM UTC 24 | 260988495 ps | ||
| T383 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_tl_errors.629011415 | Aug 21 08:14:20 AM UTC 24 | Aug 21 08:14:36 AM UTC 24 | 1650555863 ps | ||
| T384 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.461287022 | Aug 21 08:14:21 AM UTC 24 | Aug 21 08:14:37 AM UTC 24 | 351103398 ps | ||
| T125 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3348852968 | Aug 21 08:14:26 AM UTC 24 | Aug 21 08:14:38 AM UTC 24 | 377462346 ps | ||
| T94 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_rw.4158906954 | Aug 21 08:14:22 AM UTC 24 | Aug 21 08:14:38 AM UTC 24 | 983190661 ps | ||
| T385 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1000153290 | Aug 21 08:14:31 AM UTC 24 | Aug 21 08:14:40 AM UTC 24 | 353226633 ps | ||
| T386 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.740827830 | Aug 21 08:14:25 AM UTC 24 | Aug 21 08:14:40 AM UTC 24 | 251765737 ps | ||
| T387 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.383515327 | Aug 21 08:14:28 AM UTC 24 | Aug 21 08:14:40 AM UTC 24 | 522115467 ps | ||
| T95 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3069261809 | Aug 21 08:13:53 AM UTC 24 | Aug 21 08:14:41 AM UTC 24 | 3743474255 ps | ||
| T388 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1492105823 | Aug 21 08:14:23 AM UTC 24 | Aug 21 08:14:41 AM UTC 24 | 2014386743 ps | ||
| T389 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_mem_walk.4061342616 | Aug 21 08:14:31 AM UTC 24 | Aug 21 08:14:42 AM UTC 24 | 495207630 ps | ||
| T390 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1297903589 | Aug 21 08:14:32 AM UTC 24 | Aug 21 08:14:45 AM UTC 24 | 1454682305 ps | ||
| T391 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2463093448 | Aug 21 08:14:30 AM UTC 24 | Aug 21 08:14:48 AM UTC 24 | 307414230 ps | ||
| T392 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1780636362 | Aug 21 08:14:34 AM UTC 24 | Aug 21 08:14:49 AM UTC 24 | 954083641 ps | ||
| T393 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.759639487 | Aug 21 08:14:37 AM UTC 24 | Aug 21 08:14:50 AM UTC 24 | 177202750 ps | ||
| T101 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2679234132 | Aug 21 08:14:36 AM UTC 24 | Aug 21 08:14:51 AM UTC 24 | 496217571 ps | ||
| T102 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.217598387 | Aug 21 08:14:31 AM UTC 24 | Aug 21 08:14:52 AM UTC 24 | 2260314343 ps | ||
| T394 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1813931918 | Aug 21 08:14:38 AM UTC 24 | Aug 21 08:14:52 AM UTC 24 | 331979503 ps | ||
| T395 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_csr_rw.4110414835 | Aug 21 08:14:39 AM UTC 24 | Aug 21 08:14:53 AM UTC 24 | 171841706 ps | ||
| T126 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.4084085720 | Aug 21 08:14:39 AM UTC 24 | Aug 21 08:14:53 AM UTC 24 | 182537401 ps | ||
| T396 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_csr_rw.571014936 | Aug 21 08:14:41 AM UTC 24 | Aug 21 08:14:54 AM UTC 24 | 167742514 ps | ||
| T397 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.4059959574 | Aug 21 08:14:40 AM UTC 24 | Aug 21 08:14:55 AM UTC 24 | 1093877257 ps | ||
| T127 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1015809406 | Aug 21 08:14:36 AM UTC 24 | Aug 21 08:14:56 AM UTC 24 | 729429983 ps | ||
| T398 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.983171365 | Aug 21 08:14:45 AM UTC 24 | Aug 21 08:14:57 AM UTC 24 | 254281975 ps | ||
| T128 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2256918861 | Aug 21 08:14:43 AM UTC 24 | Aug 21 08:14:58 AM UTC 24 | 508036980 ps | ||
| T399 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2024495947 | Aug 21 08:14:49 AM UTC 24 | Aug 21 08:15:03 AM UTC 24 | 1177857903 ps | ||
| T400 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3565591128 | Aug 21 08:14:55 AM UTC 24 | Aug 21 08:15:03 AM UTC 24 | 687957432 ps | ||
| T401 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_tl_errors.4291071519 | Aug 21 08:14:41 AM UTC 24 | Aug 21 08:15:04 AM UTC 24 | 251123174 ps | ||
| T402 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3756142311 | Aug 21 08:14:53 AM UTC 24 | Aug 21 08:15:05 AM UTC 24 | 1008688374 ps | ||
| T129 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.785286520 | Aug 21 08:14:52 AM UTC 24 | Aug 21 08:15:05 AM UTC 24 | 261790436 ps | ||
| T403 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2213975261 | Aug 21 08:14:51 AM UTC 24 | Aug 21 08:15:06 AM UTC 24 | 994973106 ps | ||
| T404 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_tl_errors.4211300695 | Aug 21 08:14:54 AM UTC 24 | Aug 21 08:15:07 AM UTC 24 | 167778754 ps | ||
| T405 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3647413849 | Aug 21 08:14:56 AM UTC 24 | Aug 21 08:15:09 AM UTC 24 | 262794123 ps | ||
| T103 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_csr_rw.4267533218 | Aug 21 08:14:58 AM UTC 24 | Aug 21 08:15:10 AM UTC 24 | 690069946 ps | ||
| T406 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2488030372 | Aug 21 08:14:58 AM UTC 24 | Aug 21 08:15:11 AM UTC 24 | 1375170017 ps | ||
| T130 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2755022111 | Aug 21 08:14:56 AM UTC 24 | Aug 21 08:15:12 AM UTC 24 | 2051510560 ps | ||
| T407 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1208779238 | Aug 21 08:15:05 AM UTC 24 | Aug 21 08:15:13 AM UTC 24 | 174614182 ps | ||
| T408 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2549471051 | Aug 21 08:15:05 AM UTC 24 | Aug 21 08:15:18 AM UTC 24 | 645904856 ps | ||
| T409 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.483576556 | Aug 21 08:15:07 AM UTC 24 | Aug 21 08:15:20 AM UTC 24 | 168412582 ps | ||
| T104 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1214501911 | Aug 21 08:15:06 AM UTC 24 | Aug 21 08:15:21 AM UTC 24 | 884069768 ps | ||
| T111 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1548978025 | Aug 21 08:14:10 AM UTC 24 | Aug 21 08:15:22 AM UTC 24 | 3975648497 ps | ||
| T410 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2226720085 | Aug 21 08:15:11 AM UTC 24 | Aug 21 08:15:23 AM UTC 24 | 573723894 ps | ||
| T112 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.4024562982 | Aug 21 08:14:02 AM UTC 24 | Aug 21 08:15:23 AM UTC 24 | 7564556709 ps | ||
| T411 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1572512549 | Aug 21 08:15:07 AM UTC 24 | Aug 21 08:15:23 AM UTC 24 | 1468917339 ps | ||
| T412 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2446597202 | Aug 21 08:15:05 AM UTC 24 | Aug 21 08:15:24 AM UTC 24 | 988685056 ps | ||
| T413 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_rw.361550379 | Aug 21 08:15:12 AM UTC 24 | Aug 21 08:15:26 AM UTC 24 | 176584218 ps | ||
| T414 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3059879631 | Aug 21 08:15:18 AM UTC 24 | Aug 21 08:15:29 AM UTC 24 | 348756612 ps | ||
| T113 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.269547463 | Aug 21 08:14:18 AM UTC 24 | Aug 21 08:15:30 AM UTC 24 | 1573339685 ps | ||
| T415 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2345372024 | Aug 21 08:15:14 AM UTC 24 | Aug 21 08:15:34 AM UTC 24 | 512838000 ps | ||
| T157 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.997216665 | Aug 21 08:14:37 AM UTC 24 | Aug 21 08:15:35 AM UTC 24 | 4479314016 ps | ||
| T416 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2529420591 | Aug 21 08:15:23 AM UTC 24 | Aug 21 08:15:35 AM UTC 24 | 1268845681 ps | ||
| T417 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1465476743 | Aug 21 08:15:24 AM UTC 24 | Aug 21 08:15:35 AM UTC 24 | 498517316 ps | ||
| T418 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_errors.740411038 | Aug 21 08:15:21 AM UTC 24 | Aug 21 08:15:37 AM UTC 24 | 1501858366 ps | ||
| T419 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2899646196 | Aug 21 08:15:24 AM UTC 24 | Aug 21 08:15:37 AM UTC 24 | 774832592 ps | ||
| T105 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2747622758 | Aug 21 08:14:41 AM UTC 24 | Aug 21 08:15:39 AM UTC 24 | 9359482039 ps | ||
| T420 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_rw.984722851 | Aug 21 08:15:27 AM UTC 24 | Aug 21 08:15:39 AM UTC 24 | 325558603 ps | ||
| T421 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2686078803 | Aug 21 08:15:29 AM UTC 24 | Aug 21 08:15:42 AM UTC 24 | 529502093 ps | ||
| T422 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2422727265 | Aug 21 08:15:25 AM UTC 24 | Aug 21 08:15:42 AM UTC 24 | 252575916 ps | ||
| T106 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.2415699831 | Aug 21 08:14:30 AM UTC 24 | Aug 21 08:15:43 AM UTC 24 | 1537783992 ps | ||
| T423 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3908389392 | Aug 21 08:15:29 AM UTC 24 | Aug 21 08:15:45 AM UTC 24 | 983892265 ps | ||
| T424 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2721814846 | Aug 21 08:15:32 AM UTC 24 | Aug 21 08:15:47 AM UTC 24 | 172714757 ps | ||
| T425 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_rw.421376111 | Aug 21 08:15:39 AM UTC 24 | Aug 21 08:15:48 AM UTC 24 | 1101195171 ps | ||
| T426 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3431553123 | Aug 21 08:15:36 AM UTC 24 | Aug 21 08:15:49 AM UTC 24 | 385894648 ps | ||
| T427 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_rw.4208576597 | Aug 21 08:15:35 AM UTC 24 | Aug 21 08:15:49 AM UTC 24 | 518016051 ps | ||
| T428 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_errors.895217523 | Aug 21 08:15:38 AM UTC 24 | Aug 21 08:15:52 AM UTC 24 | 498119711 ps | ||
| T429 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3533900467 | Aug 21 08:14:46 AM UTC 24 | Aug 21 08:15:53 AM UTC 24 | 1587461880 ps | ||
| T430 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.4129941208 | Aug 21 08:15:40 AM UTC 24 | Aug 21 08:15:53 AM UTC 24 | 174519373 ps | ||
| T431 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3017936686 | Aug 21 08:15:40 AM UTC 24 | Aug 21 08:15:53 AM UTC 24 | 1036307443 ps | ||
| T432 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2346506336 | Aug 21 08:14:57 AM UTC 24 | Aug 21 08:15:54 AM UTC 24 | 4470406357 ps | ||
| T433 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2789486969 | Aug 21 08:15:42 AM UTC 24 | Aug 21 08:15:54 AM UTC 24 | 167368311 ps | ||
| T434 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1494888091 | Aug 21 08:15:36 AM UTC 24 | Aug 21 08:15:55 AM UTC 24 | 171302342 ps | ||
| T435 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3948750017 | Aug 21 08:15:43 AM UTC 24 | Aug 21 08:15:57 AM UTC 24 | 1242667668 ps | ||
| T436 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1623471455 | Aug 21 08:15:43 AM UTC 24 | Aug 21 08:15:58 AM UTC 24 | 188136658 ps | ||
| T437 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_rw.821884051 | Aug 21 08:15:48 AM UTC 24 | Aug 21 08:15:58 AM UTC 24 | 173688236 ps | ||
| T79 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2861180373 | Aug 21 08:14:20 AM UTC 24 | Aug 21 08:15:59 AM UTC 24 | 2112913114 ps | ||
| T438 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.4047119476 | Aug 21 08:15:49 AM UTC 24 | Aug 21 08:16:00 AM UTC 24 | 168513351 ps | ||
| T107 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.866399700 | Aug 21 08:15:21 AM UTC 24 | Aug 21 08:16:00 AM UTC 24 | 1421645181 ps | ||
| T439 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2507754854 | Aug 21 08:15:42 AM UTC 24 | Aug 21 08:16:01 AM UTC 24 | 4116910205 ps | ||
| T440 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3304868604 | Aug 21 08:15:51 AM UTC 24 | Aug 21 08:16:01 AM UTC 24 | 170901132 ps | ||
| T441 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_errors.880273627 | Aug 21 08:15:53 AM UTC 24 | Aug 21 08:16:06 AM UTC 24 | 615369281 ps | ||
| T442 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1941641803 | Aug 21 08:15:46 AM UTC 24 | Aug 21 08:16:08 AM UTC 24 | 249705484 ps | ||
| T443 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2289048476 | Aug 21 08:15:58 AM UTC 24 | Aug 21 08:16:09 AM UTC 24 | 169323005 ps | ||
| T444 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2674621575 | Aug 21 08:14:53 AM UTC 24 | Aug 21 08:16:09 AM UTC 24 | 1035048845 ps | ||
| T445 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_rw.389836244 | Aug 21 08:15:54 AM UTC 24 | Aug 21 08:16:09 AM UTC 24 | 252556534 ps | ||
| T108 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1549000922 | Aug 21 08:15:05 AM UTC 24 | Aug 21 08:16:10 AM UTC 24 | 4036403369 ps | ||
| T446 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.598900549 | Aug 21 08:15:55 AM UTC 24 | Aug 21 08:16:12 AM UTC 24 | 270792469 ps | ||
| T447 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.878375641 | Aug 21 08:15:59 AM UTC 24 | Aug 21 08:16:12 AM UTC 24 | 3378374046 ps | ||
| T448 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_errors.221219542 | Aug 21 08:15:56 AM UTC 24 | Aug 21 08:16:13 AM UTC 24 | 467899694 ps | ||
| T449 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.971373100 | Aug 21 08:15:54 AM UTC 24 | Aug 21 08:16:13 AM UTC 24 | 702302730 ps | ||
| T450 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1363366447 | Aug 21 08:16:00 AM UTC 24 | Aug 21 08:16:16 AM UTC 24 | 306666786 ps | ||
| T80 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.13666591 | Aug 21 08:14:41 AM UTC 24 | Aug 21 08:16:18 AM UTC 24 | 322333101 ps | ||
| T451 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.4045198227 | Aug 21 08:15:24 AM UTC 24 | Aug 21 08:16:21 AM UTC 24 | 4297898542 ps | ||
| T81 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1607080116 | Aug 21 08:14:58 AM UTC 24 | Aug 21 08:16:26 AM UTC 24 | 1041948090 ps | ||
| T452 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.125083600 | Aug 21 08:15:10 AM UTC 24 | Aug 21 08:16:26 AM UTC 24 | 3117459685 ps | ||
| T453 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1943458851 | Aug 21 08:15:30 AM UTC 24 | Aug 21 08:16:28 AM UTC 24 | 7863809542 ps | ||
| T454 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1576721963 | Aug 21 08:15:43 AM UTC 24 | Aug 21 08:16:31 AM UTC 24 | 4215450823 ps | ||
| T142 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2608953691 | Aug 21 08:14:51 AM UTC 24 | Aug 21 08:16:33 AM UTC 24 | 385243586 ps | ||
| T137 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.916529196 | Aug 21 08:14:12 AM UTC 24 | Aug 21 08:16:49 AM UTC 24 | 385024753 ps | ||
| T139 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2083746767 | Aug 21 08:15:25 AM UTC 24 | Aug 21 08:16:50 AM UTC 24 | 1310187107 ps | ||
| T138 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3125863544 | Aug 21 08:13:55 AM UTC 24 | Aug 21 08:16:53 AM UTC 24 | 570603587 ps | ||
| T455 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1630283369 | Aug 21 08:15:37 AM UTC 24 | Aug 21 08:16:57 AM UTC 24 | 1625378991 ps | ||
| T109 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1959520687 | Aug 21 08:15:52 AM UTC 24 | Aug 21 08:16:58 AM UTC 24 | 1576405943 ps | ||
| T110 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2988208582 | Aug 21 08:15:55 AM UTC 24 | Aug 21 08:17:05 AM UTC 24 | 5423097626 ps | ||
| T140 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3843039379 | Aug 21 08:15:34 AM UTC 24 | Aug 21 08:17:05 AM UTC 24 | 1472335149 ps | ||
| T456 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2684931503 | Aug 21 08:15:22 AM UTC 24 | Aug 21 08:17:06 AM UTC 24 | 685252073 ps | ||
| T141 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1794858214 | Aug 21 08:14:38 AM UTC 24 | Aug 21 08:17:13 AM UTC 24 | 1451465018 ps | ||
| T144 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2955840267 | Aug 21 08:14:03 AM UTC 24 | Aug 21 08:17:13 AM UTC 24 | 2295217937 ps | ||
| T457 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.4155226173 | Aug 21 08:15:41 AM UTC 24 | Aug 21 08:17:14 AM UTC 24 | 11611266956 ps | ||
| T147 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3112346436 | Aug 21 08:15:42 AM UTC 24 | Aug 21 08:17:16 AM UTC 24 | 4544547063 ps | ||
| T145 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3886792642 | Aug 21 08:15:48 AM UTC 24 | Aug 21 08:17:20 AM UTC 24 | 603928343 ps | ||
| T148 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.685282989 | Aug 21 08:14:54 AM UTC 24 | Aug 21 08:17:33 AM UTC 24 | 816095988 ps | ||
| T151 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1700095328 | Aug 21 08:14:30 AM UTC 24 | Aug 21 08:17:38 AM UTC 24 | 695075223 ps | ||
| T146 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2123845649 | Aug 21 08:15:54 AM UTC 24 | Aug 21 08:17:57 AM UTC 24 | 398711563 ps | ||
| T458 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2625860874 | Aug 21 08:15:06 AM UTC 24 | Aug 21 08:18:00 AM UTC 24 | 1257654459 ps | ||
| T149 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3741493123 | Aug 21 08:15:12 AM UTC 24 | Aug 21 08:18:04 AM UTC 24 | 492047517 ps | ||
| T143 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2664225745 | Aug 21 08:15:39 AM UTC 24 | Aug 21 08:18:44 AM UTC 24 | 806622648 ps | ||
| T150 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.942539406 | Aug 21 08:15:58 AM UTC 24 | Aug 21 08:18:44 AM UTC 24 | 4746842031 ps |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_smoke.603321760 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 876171362 ps |
| CPU time | 9.42 seconds |
| Started | Aug 21 08:08:19 AM UTC 24 |
| Finished | Aug 21 08:08:29 AM UTC 24 |
| Peak memory | 225472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=603321760 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s cratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.603321760 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.3282156973 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 2573037644 ps |
| CPU time | 31.57 seconds |
| Started | Aug 21 08:08:30 AM UTC 24 |
| Finished | Aug 21 08:09:16 AM UTC 24 |
| Peak memory | 243152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_n s=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3282156973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_ 64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all_with_rand_reset.3282156973 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_kmac_err_chk.3012744340 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 342643441 ps |
| CPU time | 17.3 seconds |
| Started | Aug 21 08:08:19 AM UTC 24 |
| Finished | Aug 21 08:08:37 AM UTC 24 |
| Peak memory | 228624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3012744340 -assert nopostproc +UVM_ TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.3012744340 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.3861036741 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 4485525350 ps |
| CPU time | 271.39 seconds |
| Started | Aug 21 08:08:19 AM UTC 24 |
| Finished | Aug 21 08:12:54 AM UTC 24 |
| Peak memory | 250656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3861036 741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 1.rom_ctrl_corrupt_sig_fatal_chk.3861036741 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all.426089749 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 792079582 ps |
| CPU time | 33.56 seconds |
| Started | Aug 21 08:08:19 AM UTC 24 |
| Finished | Aug 21 08:08:54 AM UTC 24 |
| Peak memory | 228648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10 000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim .tcl +ntb_random_seed=426089749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 1.rom_ctrl_stress_all.426089749 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_kmac_err_chk.3323959499 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 495897833 ps |
| CPU time | 19.88 seconds |
| Started | Aug 21 08:08:19 AM UTC 24 |
| Finished | Aug 21 08:08:40 AM UTC 24 |
| Peak memory | 228624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3323959499 -assert nopostproc +UVM_ TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.3323959499 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.2980804805 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 3603766749 ps |
| CPU time | 29.13 seconds |
| Started | Aug 21 08:08:19 AM UTC 24 |
| Finished | Aug 21 08:08:50 AM UTC 24 |
| Peak memory | 230888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_n s=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2980804805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_ 64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all_with_rand_reset.2980804805 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_sec_cm.174543797 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 634362093 ps |
| CPU time | 138 seconds |
| Started | Aug 21 08:08:23 AM UTC 24 |
| Finished | Aug 21 08:10:54 AM UTC 24 |
| Peak memory | 256384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=174543797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_se c_cm.174543797 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_sec_cm/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.638133077 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 19367194831 ps |
| CPU time | 425.2 seconds |
| Started | Aug 21 08:08:52 AM UTC 24 |
| Finished | Aug 21 08:16:04 AM UTC 24 |
| Peak memory | 257652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=6381330 77 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 12.rom_ctrl_corrupt_sig_fatal_chk.638133077 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1794858214 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 1451465018 ps |
| CPU time | 152.14 seconds |
| Started | Aug 21 08:14:38 AM UTC 24 |
| Finished | Aug 21 08:17:13 AM UTC 24 |
| Peak memory | 229060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=17 94858214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 5.rom_ctrl_tl_intg_err.1794858214 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all.1715150636 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 3221936984 ps |
| CPU time | 31.16 seconds |
| Started | Aug 21 08:08:19 AM UTC 24 |
| Finished | Aug 21 08:08:52 AM UTC 24 |
| Peak memory | 228680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10 000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim .tcl +ntb_random_seed=1715150636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 2.rom_ctrl_stress_all.1715150636 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.2720840283 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 2517071556 ps |
| CPU time | 110.49 seconds |
| Started | Aug 21 08:08:19 AM UTC 24 |
| Finished | Aug 21 08:10:12 AM UTC 24 |
| Peak memory | 246540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_n s=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2720840283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_ 64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all_with_rand_reset.2720840283 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all.3879632279 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 1119404253 ps |
| CPU time | 36.89 seconds |
| Started | Aug 21 08:08:23 AM UTC 24 |
| Finished | Aug 21 08:09:11 AM UTC 24 |
| Peak memory | 228708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10 000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim .tcl +ntb_random_seed=3879632279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 3.rom_ctrl_stress_all.3879632279 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_alert_test.2614621082 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 953324043 ps |
| CPU time | 8.63 seconds |
| Started | Aug 21 08:08:19 AM UTC 24 |
| Finished | Aug 21 08:08:29 AM UTC 24 |
| Peak memory | 227996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=261462108 2 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_ alert_test.2614621082 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2269988467 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 177534866 ps |
| CPU time | 11.72 seconds |
| Started | Aug 21 08:13:57 AM UTC 24 |
| Finished | Aug 21 08:14:10 AM UTC 24 |
| Peak memory | 221756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=22699 88467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0 .rom_ctrl_csr_hw_reset.2269988467 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.942539406 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 4746842031 ps |
| CPU time | 162.76 seconds |
| Started | Aug 21 08:15:58 AM UTC 24 |
| Finished | Aug 21 08:18:44 AM UTC 24 |
| Peak memory | 229200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=94 2539406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_intg_err.942539406 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_kmac_err_chk.3885911190 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 2465133727 ps |
| CPU time | 23.64 seconds |
| Started | Aug 21 08:08:50 AM UTC 24 |
| Finished | Aug 21 08:09:15 AM UTC 24 |
| Peak memory | 228600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3885911190 -assert nopostproc +UVM_ TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.3885911190 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all.130091792 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 5918788758 ps |
| CPU time | 27.22 seconds |
| Started | Aug 21 08:08:29 AM UTC 24 |
| Finished | Aug 21 08:08:58 AM UTC 24 |
| Peak memory | 228948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10 000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim .tcl +ntb_random_seed=130091792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 8.rom_ctrl_stress_all.130091792 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3069261809 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 3743474255 ps |
| CPU time | 46.65 seconds |
| Started | Aug 21 08:13:53 AM UTC 24 |
| Finished | Aug 21 08:14:41 AM UTC 24 |
| Peak memory | 229428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed =3069261809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 0.rom_ctrl_passthru_mem_tl_intg_err.3069261809 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3843039379 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 1472335149 ps |
| CPU time | 88.79 seconds |
| Started | Aug 21 08:15:34 AM UTC 24 |
| Finished | Aug 21 08:17:05 AM UTC 24 |
| Peak memory | 223856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=38 43039379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 14.rom_ctrl_tl_intg_err.3843039379 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all.1512626405 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 536441904 ps |
| CPU time | 21.42 seconds |
| Started | Aug 21 08:08:40 AM UTC 24 |
| Finished | Aug 21 08:09:03 AM UTC 24 |
| Peak memory | 227516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10 000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim .tcl +ntb_random_seed=1512626405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 10.rom_ctrl_stress_all.1512626405 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3741493123 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 492047517 ps |
| CPU time | 168.47 seconds |
| Started | Aug 21 08:15:12 AM UTC 24 |
| Finished | Aug 21 08:18:04 AM UTC 24 |
| Peak memory | 229332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=37 41493123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 11.rom_ctrl_tl_intg_err.3741493123 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.4045198227 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 4297898542 ps |
| CPU time | 55.99 seconds |
| Started | Aug 21 08:15:24 AM UTC 24 |
| Finished | Aug 21 08:16:21 AM UTC 24 |
| Peak memory | 229304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed =4045198227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 13.rom_ctrl_passthru_mem_tl_intg_err.4045198227 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all.131796503 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 2430997383 ps |
| CPU time | 30.97 seconds |
| Started | Aug 21 08:08:23 AM UTC 24 |
| Finished | Aug 21 08:09:16 AM UTC 24 |
| Peak memory | 228712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10 000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim .tcl +ntb_random_seed=131796503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 6.rom_ctrl_stress_all.131796503 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_alert_test.3095780699 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 989772792 ps |
| CPU time | 8.71 seconds |
| Started | Aug 21 08:08:19 AM UTC 24 |
| Finished | Aug 21 08:08:39 AM UTC 24 |
| Peak memory | 227808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=309578069 9 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_ alert_test.3095780699 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_max_throughput_chk.247541042 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 1701989496 ps |
| CPU time | 15.48 seconds |
| Started | Aug 21 08:10:44 AM UTC 24 |
| Finished | Aug 21 08:11:01 AM UTC 24 |
| Peak memory | 227372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=247541042 -assert no postproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_thr oughput_chk.247541042 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/29.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.1839299365 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 25016620802 ps |
| CPU time | 127.43 seconds |
| Started | Aug 21 08:09:21 AM UTC 24 |
| Finished | Aug 21 08:11:31 AM UTC 24 |
| Peak memory | 240864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_n s=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1839299365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_ 64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all_with_rand_reset.1839299365 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all.3442492505 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 1600401438 ps |
| CPU time | 49.41 seconds |
| Started | Aug 21 08:08:28 AM UTC 24 |
| Finished | Aug 21 08:09:19 AM UTC 24 |
| Peak memory | 227756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10 000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim .tcl +ntb_random_seed=3442492505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 7.rom_ctrl_stress_all.3442492505 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all.1311918984 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 540584277 ps |
| CPU time | 21.01 seconds |
| Started | Aug 21 08:08:19 AM UTC 24 |
| Finished | Aug 21 08:08:41 AM UTC 24 |
| Peak memory | 228716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10 000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim .tcl +ntb_random_seed=1311918984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 0.rom_ctrl_stress_all.1311918984 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.280431117 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 1031735034 ps |
| CPU time | 11.07 seconds |
| Started | Aug 21 08:14:01 AM UTC 24 |
| Finished | Aug 21 08:14:14 AM UTC 24 |
| Peak memory | 221888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=28043 1117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0. rom_ctrl_csr_aliasing.280431117 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_csr_aliasing/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1031219459 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 3539049157 ps |
| CPU time | 14.67 seconds |
| Started | Aug 21 08:14:00 AM UTC 24 |
| Finished | Aug 21 08:14:16 AM UTC 24 |
| Peak memory | 221884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=10312 19459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0 .rom_ctrl_csr_bit_bash.1031219459 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3265989292 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 719476086 ps |
| CPU time | 9.3 seconds |
| Started | Aug 21 08:14:02 AM UTC 24 |
| Finished | Aug 21 08:14:13 AM UTC 24 |
| Peak memory | 229276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opent itan/hw/dv/tools/sim.tcl +ntb_random_seed=3265989292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage /cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.3265989292 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_rw.482069976 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 3103153598 ps |
| CPU time | 11.35 seconds |
| Started | Aug 21 08:13:59 AM UTC 24 |
| Finished | Aug 21 08:14:12 AM UTC 24 |
| Peak memory | 222000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=482069976 - assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ct rl_csr_rw.482069976 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3542817503 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 175244173 ps |
| CPU time | 7.65 seconds |
| Started | Aug 21 08:13:57 AM UTC 24 |
| Finished | Aug 21 08:14:06 AM UTC 24 |
| Peak memory | 221612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_ seed=3542817503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_partial_access.3542817503 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_mem_partial_access/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3378848592 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 664726977 ps |
| CPU time | 9.79 seconds |
| Started | Aug 21 08:13:55 AM UTC 24 |
| Finished | Aug 21 08:14:06 AM UTC 24 |
| Peak memory | 221756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=33788 48592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0 .rom_ctrl_mem_walk.3378848592 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_mem_walk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2693592925 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 1081097738 ps |
| CPU time | 13.65 seconds |
| Started | Aug 21 08:14:02 AM UTC 24 |
| Finished | Aug 21 08:14:18 AM UTC 24 |
| Peak memory | 221808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_rando m_seed=2693592925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 0.rom_ctrl_same_csr_outstanding.2693592925 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3137369577 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 1275212060 ps |
| CPU time | 18.32 seconds |
| Started | Aug 21 08:13:54 AM UTC 24 |
| Finished | Aug 21 08:14:14 AM UTC 24 |
| Peak memory | 229056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3137369577 -as sert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl _tl_errors.3137369577 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3125863544 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 570603587 ps |
| CPU time | 175.08 seconds |
| Started | Aug 21 08:13:55 AM UTC 24 |
| Finished | Aug 21 08:16:53 AM UTC 24 |
| Peak memory | 225916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=31 25863544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 0.rom_ctrl_tl_intg_err.3125863544 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2655616455 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 3306457806 ps |
| CPU time | 10.93 seconds |
| Started | Aug 21 08:14:08 AM UTC 24 |
| Finished | Aug 21 08:14:20 AM UTC 24 |
| Peak memory | 221884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=26556 16455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1 .rom_ctrl_csr_aliasing.2655616455 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_csr_aliasing/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1176610439 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 952980419 ps |
| CPU time | 12.42 seconds |
| Started | Aug 21 08:14:08 AM UTC 24 |
| Finished | Aug 21 08:14:21 AM UTC 24 |
| Peak memory | 221780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=11766 10439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1 .rom_ctrl_csr_bit_bash.1176610439 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2218068720 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 271094984 ps |
| CPU time | 22.66 seconds |
| Started | Aug 21 08:14:07 AM UTC 24 |
| Finished | Aug 21 08:14:32 AM UTC 24 |
| Peak memory | 223868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=22180 68720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1 .rom_ctrl_csr_hw_reset.2218068720 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.158064103 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 1348394472 ps |
| CPU time | 14.3 seconds |
| Started | Aug 21 08:14:10 AM UTC 24 |
| Finished | Aug 21 08:14:25 AM UTC 24 |
| Peak memory | 229280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opent itan/hw/dv/tools/sim.tcl +ntb_random_seed=158064103 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/ cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.158064103 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1638162395 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 312021013 ps |
| CPU time | 9.47 seconds |
| Started | Aug 21 08:14:08 AM UTC 24 |
| Finished | Aug 21 08:14:18 AM UTC 24 |
| Peak memory | 221896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1638162395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c trl_csr_rw.1638162395 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.4035920630 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 988652642 ps |
| CPU time | 11.6 seconds |
| Started | Aug 21 08:14:06 AM UTC 24 |
| Finished | Aug 21 08:14:20 AM UTC 24 |
| Peak memory | 221680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_ seed=4035920630 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_partial_access.4035920630 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_mem_partial_access/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_walk.944070323 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 170974493 ps |
| CPU time | 10.29 seconds |
| Started | Aug 21 08:14:04 AM UTC 24 |
| Finished | Aug 21 08:14:16 AM UTC 24 |
| Peak memory | 221816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=94407 0323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1. rom_ctrl_mem_walk.944070323 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_mem_walk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.4024562982 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 7564556709 ps |
| CPU time | 77.86 seconds |
| Started | Aug 21 08:14:02 AM UTC 24 |
| Finished | Aug 21 08:15:23 AM UTC 24 |
| Peak memory | 229296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed =4024562982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 1.rom_ctrl_passthru_mem_tl_intg_err.4024562982 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1666761895 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 612744005 ps |
| CPU time | 11.44 seconds |
| Started | Aug 21 08:14:08 AM UTC 24 |
| Finished | Aug 21 08:14:20 AM UTC 24 |
| Peak memory | 221936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_rando m_seed=1666761895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 1.rom_ctrl_same_csr_outstanding.1666761895 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2205980949 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 249504653 ps |
| CPU time | 13.07 seconds |
| Started | Aug 21 08:14:03 AM UTC 24 |
| Finished | Aug 21 08:14:18 AM UTC 24 |
| Peak memory | 229372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2205980949 -as sert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl _tl_errors.2205980949 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2955840267 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 2295217937 ps |
| CPU time | 185.67 seconds |
| Started | Aug 21 08:14:03 AM UTC 24 |
| Finished | Aug 21 08:17:13 AM UTC 24 |
| Peak memory | 224060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=29 55840267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 1.rom_ctrl_tl_intg_err.2955840267 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1572512549 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 1468917339 ps |
| CPU time | 15.2 seconds |
| Started | Aug 21 08:15:07 AM UTC 24 |
| Finished | Aug 21 08:15:23 AM UTC 24 |
| Peak memory | 228084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opent itan/hw/dv/tools/sim.tcl +ntb_random_seed=1572512549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage /cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.1572512549 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1214501911 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 884069768 ps |
| CPU time | 13.67 seconds |
| Started | Aug 21 08:15:06 AM UTC 24 |
| Finished | Aug 21 08:15:21 AM UTC 24 |
| Peak memory | 221812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1214501911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ ctrl_csr_rw.1214501911 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1549000922 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 4036403369 ps |
| CPU time | 63.63 seconds |
| Started | Aug 21 08:15:05 AM UTC 24 |
| Finished | Aug 21 08:16:10 AM UTC 24 |
| Peak memory | 226008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed =1549000922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 10.rom_ctrl_passthru_mem_tl_intg_err.1549000922 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.483576556 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 168412582 ps |
| CPU time | 12.47 seconds |
| Started | Aug 21 08:15:07 AM UTC 24 |
| Finished | Aug 21 08:15:20 AM UTC 24 |
| Peak memory | 223852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_rando m_seed=483576556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_same_csr_outstanding.483576556 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2446597202 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 988685056 ps |
| CPU time | 18.55 seconds |
| Started | Aug 21 08:15:05 AM UTC 24 |
| Finished | Aug 21 08:15:24 AM UTC 24 |
| Peak memory | 228012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2446597202 -as sert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctr l_tl_errors.2446597202 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2625860874 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 1257654459 ps |
| CPU time | 171.52 seconds |
| Started | Aug 21 08:15:06 AM UTC 24 |
| Finished | Aug 21 08:18:00 AM UTC 24 |
| Peak memory | 225904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=26 25860874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 10.rom_ctrl_tl_intg_err.2625860874 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3059879631 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 348756612 ps |
| CPU time | 9.18 seconds |
| Started | Aug 21 08:15:18 AM UTC 24 |
| Finished | Aug 21 08:15:29 AM UTC 24 |
| Peak memory | 229400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opent itan/hw/dv/tools/sim.tcl +ntb_random_seed=3059879631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage /cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.3059879631 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_rw.361550379 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 176584218 ps |
| CPU time | 12.61 seconds |
| Started | Aug 21 08:15:12 AM UTC 24 |
| Finished | Aug 21 08:15:26 AM UTC 24 |
| Peak memory | 221876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=361550379 - assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_c trl_csr_rw.361550379 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.125083600 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 3117459685 ps |
| CPU time | 74.28 seconds |
| Started | Aug 21 08:15:10 AM UTC 24 |
| Finished | Aug 21 08:16:26 AM UTC 24 |
| Peak memory | 226076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed =125083600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 11.rom_ctrl_passthru_mem_tl_intg_err.125083600 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2345372024 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 512838000 ps |
| CPU time | 18.43 seconds |
| Started | Aug 21 08:15:14 AM UTC 24 |
| Finished | Aug 21 08:15:34 AM UTC 24 |
| Peak memory | 223856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_rando m_seed=2345372024 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 11.rom_ctrl_same_csr_outstanding.2345372024 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2226720085 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 573723894 ps |
| CPU time | 10.49 seconds |
| Started | Aug 21 08:15:11 AM UTC 24 |
| Finished | Aug 21 08:15:23 AM UTC 24 |
| Peak memory | 228056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2226720085 -as sert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctr l_tl_errors.2226720085 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1465476743 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 498517316 ps |
| CPU time | 10.57 seconds |
| Started | Aug 21 08:15:24 AM UTC 24 |
| Finished | Aug 21 08:15:35 AM UTC 24 |
| Peak memory | 227808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opent itan/hw/dv/tools/sim.tcl +ntb_random_seed=1465476743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage /cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.1465476743 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2529420591 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 1268845681 ps |
| CPU time | 11.62 seconds |
| Started | Aug 21 08:15:23 AM UTC 24 |
| Finished | Aug 21 08:15:35 AM UTC 24 |
| Peak memory | 221940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2529420591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ ctrl_csr_rw.2529420591 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.866399700 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 1421645181 ps |
| CPU time | 37.36 seconds |
| Started | Aug 21 08:15:21 AM UTC 24 |
| Finished | Aug 21 08:16:00 AM UTC 24 |
| Peak memory | 225860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed =866399700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 12.rom_ctrl_passthru_mem_tl_intg_err.866399700 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2899646196 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 774832592 ps |
| CPU time | 12.64 seconds |
| Started | Aug 21 08:15:24 AM UTC 24 |
| Finished | Aug 21 08:15:37 AM UTC 24 |
| Peak memory | 222000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_rando m_seed=2899646196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 12.rom_ctrl_same_csr_outstanding.2899646196 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_errors.740411038 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 1501858366 ps |
| CPU time | 13.95 seconds |
| Started | Aug 21 08:15:21 AM UTC 24 |
| Finished | Aug 21 08:15:37 AM UTC 24 |
| Peak memory | 228784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=740411038 -ass ert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl _tl_errors.740411038 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2684931503 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 685252073 ps |
| CPU time | 102.66 seconds |
| Started | Aug 21 08:15:22 AM UTC 24 |
| Finished | Aug 21 08:17:06 AM UTC 24 |
| Peak memory | 225904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=26 84931503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 12.rom_ctrl_tl_intg_err.2684931503 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2686078803 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 529502093 ps |
| CPU time | 11.4 seconds |
| Started | Aug 21 08:15:29 AM UTC 24 |
| Finished | Aug 21 08:15:42 AM UTC 24 |
| Peak memory | 229336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opent itan/hw/dv/tools/sim.tcl +ntb_random_seed=2686078803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage /cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.2686078803 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_rw.984722851 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 325558603 ps |
| CPU time | 10.94 seconds |
| Started | Aug 21 08:15:27 AM UTC 24 |
| Finished | Aug 21 08:15:39 AM UTC 24 |
| Peak memory | 221940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=984722851 - assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_c trl_csr_rw.984722851 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3908389392 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 983892265 ps |
| CPU time | 15.28 seconds |
| Started | Aug 21 08:15:29 AM UTC 24 |
| Finished | Aug 21 08:15:45 AM UTC 24 |
| Peak memory | 221936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_rando m_seed=3908389392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 13.rom_ctrl_same_csr_outstanding.3908389392 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2422727265 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 252575916 ps |
| CPU time | 16.33 seconds |
| Started | Aug 21 08:15:25 AM UTC 24 |
| Finished | Aug 21 08:15:42 AM UTC 24 |
| Peak memory | 229380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2422727265 -as sert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctr l_tl_errors.2422727265 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2083746767 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 1310187107 ps |
| CPU time | 83.77 seconds |
| Started | Aug 21 08:15:25 AM UTC 24 |
| Finished | Aug 21 08:16:50 AM UTC 24 |
| Peak memory | 229392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=20 83746767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 13.rom_ctrl_tl_intg_err.2083746767 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3431553123 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 385894648 ps |
| CPU time | 11.71 seconds |
| Started | Aug 21 08:15:36 AM UTC 24 |
| Finished | Aug 21 08:15:49 AM UTC 24 |
| Peak memory | 229208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opent itan/hw/dv/tools/sim.tcl +ntb_random_seed=3431553123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage /cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.3431553123 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_rw.4208576597 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 518016051 ps |
| CPU time | 12.8 seconds |
| Started | Aug 21 08:15:35 AM UTC 24 |
| Finished | Aug 21 08:15:49 AM UTC 24 |
| Peak memory | 221940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4208576597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ ctrl_csr_rw.4208576597 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1943458851 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 7863809542 ps |
| CPU time | 56.2 seconds |
| Started | Aug 21 08:15:30 AM UTC 24 |
| Finished | Aug 21 08:16:28 AM UTC 24 |
| Peak memory | 228052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed =1943458851 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 14.rom_ctrl_passthru_mem_tl_intg_err.1943458851 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1494888091 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 171302342 ps |
| CPU time | 17.92 seconds |
| Started | Aug 21 08:15:36 AM UTC 24 |
| Finished | Aug 21 08:15:55 AM UTC 24 |
| Peak memory | 223720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_rando m_seed=1494888091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 14.rom_ctrl_same_csr_outstanding.1494888091 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2721814846 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 172714757 ps |
| CPU time | 13.68 seconds |
| Started | Aug 21 08:15:32 AM UTC 24 |
| Finished | Aug 21 08:15:47 AM UTC 24 |
| Peak memory | 227992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2721814846 -as sert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctr l_tl_errors.2721814846 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3017936686 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 1036307443 ps |
| CPU time | 12.43 seconds |
| Started | Aug 21 08:15:40 AM UTC 24 |
| Finished | Aug 21 08:15:53 AM UTC 24 |
| Peak memory | 228152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opent itan/hw/dv/tools/sim.tcl +ntb_random_seed=3017936686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage /cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.3017936686 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_rw.421376111 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 1101195171 ps |
| CPU time | 7.98 seconds |
| Started | Aug 21 08:15:39 AM UTC 24 |
| Finished | Aug 21 08:15:48 AM UTC 24 |
| Peak memory | 222004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=421376111 - assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_c trl_csr_rw.421376111 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1630283369 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 1625378991 ps |
| CPU time | 78.38 seconds |
| Started | Aug 21 08:15:37 AM UTC 24 |
| Finished | Aug 21 08:16:57 AM UTC 24 |
| Peak memory | 229080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed =1630283369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 15.rom_ctrl_passthru_mem_tl_intg_err.1630283369 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.4129941208 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 174519373 ps |
| CPU time | 11.63 seconds |
| Started | Aug 21 08:15:40 AM UTC 24 |
| Finished | Aug 21 08:15:53 AM UTC 24 |
| Peak memory | 223856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_rando m_seed=4129941208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 15.rom_ctrl_same_csr_outstanding.4129941208 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_errors.895217523 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 498119711 ps |
| CPU time | 13.31 seconds |
| Started | Aug 21 08:15:38 AM UTC 24 |
| Finished | Aug 21 08:15:52 AM UTC 24 |
| Peak memory | 228940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=895217523 -ass ert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl _tl_errors.895217523 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2664225745 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 806622648 ps |
| CPU time | 181.86 seconds |
| Started | Aug 21 08:15:39 AM UTC 24 |
| Finished | Aug 21 08:18:44 AM UTC 24 |
| Peak memory | 229136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=26 64225745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 15.rom_ctrl_tl_intg_err.2664225745 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1623471455 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 188136658 ps |
| CPU time | 13.22 seconds |
| Started | Aug 21 08:15:43 AM UTC 24 |
| Finished | Aug 21 08:15:58 AM UTC 24 |
| Peak memory | 228148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opent itan/hw/dv/tools/sim.tcl +ntb_random_seed=1623471455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage /cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.1623471455 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2789486969 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 167368311 ps |
| CPU time | 11.32 seconds |
| Started | Aug 21 08:15:42 AM UTC 24 |
| Finished | Aug 21 08:15:54 AM UTC 24 |
| Peak memory | 221812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2789486969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ ctrl_csr_rw.2789486969 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.4155226173 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 11611266956 ps |
| CPU time | 90.94 seconds |
| Started | Aug 21 08:15:41 AM UTC 24 |
| Finished | Aug 21 08:17:14 AM UTC 24 |
| Peak memory | 229304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed =4155226173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 16.rom_ctrl_passthru_mem_tl_intg_err.4155226173 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3948750017 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 1242667668 ps |
| CPU time | 13.04 seconds |
| Started | Aug 21 08:15:43 AM UTC 24 |
| Finished | Aug 21 08:15:57 AM UTC 24 |
| Peak memory | 221808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_rando m_seed=3948750017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 16.rom_ctrl_same_csr_outstanding.3948750017 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2507754854 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 4116910205 ps |
| CPU time | 17.74 seconds |
| Started | Aug 21 08:15:42 AM UTC 24 |
| Finished | Aug 21 08:16:01 AM UTC 24 |
| Peak memory | 228860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2507754854 -as sert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctr l_tl_errors.2507754854 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3112346436 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 4544547063 ps |
| CPU time | 91.73 seconds |
| Started | Aug 21 08:15:42 AM UTC 24 |
| Finished | Aug 21 08:17:16 AM UTC 24 |
| Peak memory | 229268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=31 12346436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 16.rom_ctrl_tl_intg_err.3112346436 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3304868604 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 170901132 ps |
| CPU time | 8.96 seconds |
| Started | Aug 21 08:15:51 AM UTC 24 |
| Finished | Aug 21 08:16:01 AM UTC 24 |
| Peak memory | 229336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opent itan/hw/dv/tools/sim.tcl +ntb_random_seed=3304868604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage /cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.3304868604 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_rw.821884051 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 173688236 ps |
| CPU time | 8.73 seconds |
| Started | Aug 21 08:15:48 AM UTC 24 |
| Finished | Aug 21 08:15:58 AM UTC 24 |
| Peak memory | 222004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=821884051 - assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_c trl_csr_rw.821884051 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1576721963 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 4215450823 ps |
| CPU time | 46.76 seconds |
| Started | Aug 21 08:15:43 AM UTC 24 |
| Finished | Aug 21 08:16:31 AM UTC 24 |
| Peak memory | 226004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed =1576721963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 17.rom_ctrl_passthru_mem_tl_intg_err.1576721963 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.4047119476 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 168513351 ps |
| CPU time | 8.67 seconds |
| Started | Aug 21 08:15:49 AM UTC 24 |
| Finished | Aug 21 08:16:00 AM UTC 24 |
| Peak memory | 221808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_rando m_seed=4047119476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 17.rom_ctrl_same_csr_outstanding.4047119476 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1941641803 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 249705484 ps |
| CPU time | 20.13 seconds |
| Started | Aug 21 08:15:46 AM UTC 24 |
| Finished | Aug 21 08:16:08 AM UTC 24 |
| Peak memory | 229244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1941641803 -as sert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctr l_tl_errors.1941641803 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3886792642 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 603928343 ps |
| CPU time | 89.11 seconds |
| Started | Aug 21 08:15:48 AM UTC 24 |
| Finished | Aug 21 08:17:20 AM UTC 24 |
| Peak memory | 223920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=38 86792642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 17.rom_ctrl_tl_intg_err.3886792642 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.598900549 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 270792469 ps |
| CPU time | 15.33 seconds |
| Started | Aug 21 08:15:55 AM UTC 24 |
| Finished | Aug 21 08:16:12 AM UTC 24 |
| Peak memory | 227992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opent itan/hw/dv/tools/sim.tcl +ntb_random_seed=598900549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/ cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.598900549 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_rw.389836244 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 252556534 ps |
| CPU time | 14.26 seconds |
| Started | Aug 21 08:15:54 AM UTC 24 |
| Finished | Aug 21 08:16:09 AM UTC 24 |
| Peak memory | 221748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=389836244 - assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_c trl_csr_rw.389836244 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1959520687 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 1576405943 ps |
| CPU time | 64.64 seconds |
| Started | Aug 21 08:15:52 AM UTC 24 |
| Finished | Aug 21 08:16:58 AM UTC 24 |
| Peak memory | 226072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed =1959520687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 18.rom_ctrl_passthru_mem_tl_intg_err.1959520687 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.971373100 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 702302730 ps |
| CPU time | 18.01 seconds |
| Started | Aug 21 08:15:54 AM UTC 24 |
| Finished | Aug 21 08:16:13 AM UTC 24 |
| Peak memory | 223980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_rando m_seed=971373100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_same_csr_outstanding.971373100 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_errors.880273627 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 615369281 ps |
| CPU time | 12.18 seconds |
| Started | Aug 21 08:15:53 AM UTC 24 |
| Finished | Aug 21 08:16:06 AM UTC 24 |
| Peak memory | 228124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=880273627 -ass ert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl _tl_errors.880273627 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2123845649 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 398711563 ps |
| CPU time | 120.36 seconds |
| Started | Aug 21 08:15:54 AM UTC 24 |
| Finished | Aug 21 08:17:57 AM UTC 24 |
| Peak memory | 229204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=21 23845649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 18.rom_ctrl_tl_intg_err.2123845649 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1363366447 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 306666786 ps |
| CPU time | 14.38 seconds |
| Started | Aug 21 08:16:00 AM UTC 24 |
| Finished | Aug 21 08:16:16 AM UTC 24 |
| Peak memory | 228020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opent itan/hw/dv/tools/sim.tcl +ntb_random_seed=1363366447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage /cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.1363366447 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2289048476 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 169323005 ps |
| CPU time | 9.62 seconds |
| Started | Aug 21 08:15:58 AM UTC 24 |
| Finished | Aug 21 08:16:09 AM UTC 24 |
| Peak memory | 221812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2289048476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ ctrl_csr_rw.2289048476 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2988208582 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 5423097626 ps |
| CPU time | 67.64 seconds |
| Started | Aug 21 08:15:55 AM UTC 24 |
| Finished | Aug 21 08:17:05 AM UTC 24 |
| Peak memory | 226136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed =2988208582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 19.rom_ctrl_passthru_mem_tl_intg_err.2988208582 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.878375641 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 3378374046 ps |
| CPU time | 11.78 seconds |
| Started | Aug 21 08:15:59 AM UTC 24 |
| Finished | Aug 21 08:16:12 AM UTC 24 |
| Peak memory | 224044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_rando m_seed=878375641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_same_csr_outstanding.878375641 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_errors.221219542 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 467899694 ps |
| CPU time | 15.9 seconds |
| Started | Aug 21 08:15:56 AM UTC 24 |
| Finished | Aug 21 08:16:13 AM UTC 24 |
| Peak memory | 229244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=221219542 -ass ert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl _tl_errors.221219542 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.4110737108 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 250179620 ps |
| CPU time | 14.58 seconds |
| Started | Aug 21 08:14:17 AM UTC 24 |
| Finished | Aug 21 08:14:33 AM UTC 24 |
| Peak memory | 221748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=41107 37108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2 .rom_ctrl_csr_aliasing.4110737108 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_csr_aliasing/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3508660077 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 204575235 ps |
| CPU time | 12.23 seconds |
| Started | Aug 21 08:14:16 AM UTC 24 |
| Finished | Aug 21 08:14:30 AM UTC 24 |
| Peak memory | 221812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=35086 60077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2 .rom_ctrl_csr_bit_bash.3508660077 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3115697502 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 699081178 ps |
| CPU time | 14.87 seconds |
| Started | Aug 21 08:14:14 AM UTC 24 |
| Finished | Aug 21 08:14:30 AM UTC 24 |
| Peak memory | 221812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=31156 97502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2 .rom_ctrl_csr_hw_reset.3115697502 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.4280710931 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 344139458 ps |
| CPU time | 10.91 seconds |
| Started | Aug 21 08:14:17 AM UTC 24 |
| Finished | Aug 21 08:14:29 AM UTC 24 |
| Peak memory | 229212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opent itan/hw/dv/tools/sim.tcl +ntb_random_seed=4280710931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage /cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.4280710931 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_rw.92225740 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 3637961752 ps |
| CPU time | 13.37 seconds |
| Started | Aug 21 08:14:15 AM UTC 24 |
| Finished | Aug 21 08:14:30 AM UTC 24 |
| Peak memory | 221960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=92225740 -a ssert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr l_csr_rw.92225740 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.145502527 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 2065576050 ps |
| CPU time | 19.66 seconds |
| Started | Aug 21 08:14:14 AM UTC 24 |
| Finished | Aug 21 08:14:35 AM UTC 24 |
| Peak memory | 221608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_ seed=145502527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null - cm_name 2.rom_ctrl_mem_partial_access.145502527 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_mem_partial_access/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_walk.4060021229 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 169063376 ps |
| CPU time | 8.24 seconds |
| Started | Aug 21 08:14:13 AM UTC 24 |
| Finished | Aug 21 08:14:22 AM UTC 24 |
| Peak memory | 221692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=40600 21229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2 .rom_ctrl_mem_walk.4060021229 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_mem_walk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1548978025 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 3975648497 ps |
| CPU time | 70.77 seconds |
| Started | Aug 21 08:14:10 AM UTC 24 |
| Finished | Aug 21 08:15:22 AM UTC 24 |
| Peak memory | 226128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed =1548978025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 2.rom_ctrl_passthru_mem_tl_intg_err.1548978025 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3569142221 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 989782038 ps |
| CPU time | 9.14 seconds |
| Started | Aug 21 08:14:17 AM UTC 24 |
| Finished | Aug 21 08:14:28 AM UTC 24 |
| Peak memory | 221808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_rando m_seed=3569142221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 2.rom_ctrl_same_csr_outstanding.3569142221 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_errors.445854370 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 1540720970 ps |
| CPU time | 18.13 seconds |
| Started | Aug 21 08:14:11 AM UTC 24 |
| Finished | Aug 21 08:14:30 AM UTC 24 |
| Peak memory | 229252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=445854370 -ass ert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_ tl_errors.445854370 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.916529196 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 385024753 ps |
| CPU time | 154.61 seconds |
| Started | Aug 21 08:14:12 AM UTC 24 |
| Finished | Aug 21 08:16:49 AM UTC 24 |
| Peak memory | 225916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=91 6529196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_intg_err.916529196 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.740827830 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 251765737 ps |
| CPU time | 13.87 seconds |
| Started | Aug 21 08:14:25 AM UTC 24 |
| Finished | Aug 21 08:14:40 AM UTC 24 |
| Peak memory | 221756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=74082 7830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3. rom_ctrl_csr_aliasing.740827830 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_csr_aliasing/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1492105823 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 2014386743 ps |
| CPU time | 16.83 seconds |
| Started | Aug 21 08:14:23 AM UTC 24 |
| Finished | Aug 21 08:14:41 AM UTC 24 |
| Peak memory | 223868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=14921 05823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3 .rom_ctrl_csr_bit_bash.1492105823 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.461287022 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 351103398 ps |
| CPU time | 14.84 seconds |
| Started | Aug 21 08:14:21 AM UTC 24 |
| Finished | Aug 21 08:14:37 AM UTC 24 |
| Peak memory | 223868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=46128 7022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3. rom_ctrl_csr_hw_reset.461287022 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.383515327 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 522115467 ps |
| CPU time | 11.11 seconds |
| Started | Aug 21 08:14:28 AM UTC 24 |
| Finished | Aug 21 08:14:40 AM UTC 24 |
| Peak memory | 225980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opent itan/hw/dv/tools/sim.tcl +ntb_random_seed=383515327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/ cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.383515327 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_rw.4158906954 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 983190661 ps |
| CPU time | 15.05 seconds |
| Started | Aug 21 08:14:22 AM UTC 24 |
| Finished | Aug 21 08:14:38 AM UTC 24 |
| Peak memory | 221952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4158906954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c trl_csr_rw.4158906954 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3374922093 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 260988495 ps |
| CPU time | 13.86 seconds |
| Started | Aug 21 08:14:21 AM UTC 24 |
| Finished | Aug 21 08:14:36 AM UTC 24 |
| Peak memory | 221680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_ seed=3374922093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_partial_access.3374922093 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_mem_partial_access/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_mem_walk.174400058 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 339795630 ps |
| CPU time | 12.54 seconds |
| Started | Aug 21 08:14:21 AM UTC 24 |
| Finished | Aug 21 08:14:34 AM UTC 24 |
| Peak memory | 221676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=17440 0058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3. rom_ctrl_mem_walk.174400058 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_mem_walk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.269547463 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 1573339685 ps |
| CPU time | 69.47 seconds |
| Started | Aug 21 08:14:18 AM UTC 24 |
| Finished | Aug 21 08:15:30 AM UTC 24 |
| Peak memory | 226076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed =269547463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 3.rom_ctrl_passthru_mem_tl_intg_err.269547463 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3348852968 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 377462346 ps |
| CPU time | 10.44 seconds |
| Started | Aug 21 08:14:26 AM UTC 24 |
| Finished | Aug 21 08:14:38 AM UTC 24 |
| Peak memory | 221808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_rando m_seed=3348852968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 3.rom_ctrl_same_csr_outstanding.3348852968 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_tl_errors.629011415 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 1650555863 ps |
| CPU time | 15.18 seconds |
| Started | Aug 21 08:14:20 AM UTC 24 |
| Finished | Aug 21 08:14:36 AM UTC 24 |
| Peak memory | 229252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=629011415 -ass ert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_ tl_errors.629011415 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2861180373 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 2112913114 ps |
| CPU time | 97.38 seconds |
| Started | Aug 21 08:14:20 AM UTC 24 |
| Finished | Aug 21 08:15:59 AM UTC 24 |
| Peak memory | 225916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=28 61180373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 3.rom_ctrl_tl_intg_err.2861180373 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2679234132 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 496217571 ps |
| CPU time | 14.07 seconds |
| Started | Aug 21 08:14:36 AM UTC 24 |
| Finished | Aug 21 08:14:51 AM UTC 24 |
| Peak memory | 221948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=26792 34132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4 .rom_ctrl_csr_aliasing.2679234132 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_csr_aliasing/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1780636362 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 954083641 ps |
| CPU time | 14.75 seconds |
| Started | Aug 21 08:14:34 AM UTC 24 |
| Finished | Aug 21 08:14:49 AM UTC 24 |
| Peak memory | 221820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=17806 36362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4 .rom_ctrl_csr_bit_bash.1780636362 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.217598387 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 2260314343 ps |
| CPU time | 19.19 seconds |
| Started | Aug 21 08:14:31 AM UTC 24 |
| Finished | Aug 21 08:14:52 AM UTC 24 |
| Peak memory | 221952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=21759 8387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4. rom_ctrl_csr_hw_reset.217598387 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.759639487 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 177202750 ps |
| CPU time | 12.23 seconds |
| Started | Aug 21 08:14:37 AM UTC 24 |
| Finished | Aug 21 08:14:50 AM UTC 24 |
| Peak memory | 225980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opent itan/hw/dv/tools/sim.tcl +ntb_random_seed=759639487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/ cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.759639487 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1297903589 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 1454682305 ps |
| CPU time | 11.52 seconds |
| Started | Aug 21 08:14:32 AM UTC 24 |
| Finished | Aug 21 08:14:45 AM UTC 24 |
| Peak memory | 221760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1297903589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c trl_csr_rw.1297903589 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1000153290 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 353226633 ps |
| CPU time | 7.31 seconds |
| Started | Aug 21 08:14:31 AM UTC 24 |
| Finished | Aug 21 08:14:40 AM UTC 24 |
| Peak memory | 221616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_ seed=1000153290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_partial_access.1000153290 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_mem_partial_access/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_mem_walk.4061342616 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 495207630 ps |
| CPU time | 10.12 seconds |
| Started | Aug 21 08:14:31 AM UTC 24 |
| Finished | Aug 21 08:14:42 AM UTC 24 |
| Peak memory | 221692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=40613 42616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4 .rom_ctrl_mem_walk.4061342616 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_mem_walk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.2415699831 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 1537783992 ps |
| CPU time | 70.77 seconds |
| Started | Aug 21 08:14:30 AM UTC 24 |
| Finished | Aug 21 08:15:43 AM UTC 24 |
| Peak memory | 225844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed =2415699831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 4.rom_ctrl_passthru_mem_tl_intg_err.2415699831 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1015809406 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 729429983 ps |
| CPU time | 18.81 seconds |
| Started | Aug 21 08:14:36 AM UTC 24 |
| Finished | Aug 21 08:14:56 AM UTC 24 |
| Peak memory | 223984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_rando m_seed=1015809406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 4.rom_ctrl_same_csr_outstanding.1015809406 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2463093448 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 307414230 ps |
| CPU time | 16.66 seconds |
| Started | Aug 21 08:14:30 AM UTC 24 |
| Finished | Aug 21 08:14:48 AM UTC 24 |
| Peak memory | 228064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2463093448 -as sert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl _tl_errors.2463093448 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1700095328 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 695075223 ps |
| CPU time | 184.21 seconds |
| Started | Aug 21 08:14:30 AM UTC 24 |
| Finished | Aug 21 08:17:38 AM UTC 24 |
| Peak memory | 229344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=17 00095328 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 4.rom_ctrl_tl_intg_err.1700095328 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.4059959574 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 1093877257 ps |
| CPU time | 13.87 seconds |
| Started | Aug 21 08:14:40 AM UTC 24 |
| Finished | Aug 21 08:14:55 AM UTC 24 |
| Peak memory | 225976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opent itan/hw/dv/tools/sim.tcl +ntb_random_seed=4059959574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage /cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.4059959574 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_csr_rw.4110414835 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 171841706 ps |
| CPU time | 12.77 seconds |
| Started | Aug 21 08:14:39 AM UTC 24 |
| Finished | Aug 21 08:14:53 AM UTC 24 |
| Peak memory | 221888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4110414835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c trl_csr_rw.4110414835 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.997216665 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 4479314016 ps |
| CPU time | 56.29 seconds |
| Started | Aug 21 08:14:37 AM UTC 24 |
| Finished | Aug 21 08:15:35 AM UTC 24 |
| Peak memory | 229312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed =997216665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 5.rom_ctrl_passthru_mem_tl_intg_err.997216665 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.4084085720 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 182537401 ps |
| CPU time | 13 seconds |
| Started | Aug 21 08:14:39 AM UTC 24 |
| Finished | Aug 21 08:14:53 AM UTC 24 |
| Peak memory | 223920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_rando m_seed=4084085720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 5.rom_ctrl_same_csr_outstanding.4084085720 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1813931918 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 331979503 ps |
| CPU time | 13.24 seconds |
| Started | Aug 21 08:14:38 AM UTC 24 |
| Finished | Aug 21 08:14:52 AM UTC 24 |
| Peak memory | 227824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1813931918 -as sert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl _tl_errors.1813931918 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.983171365 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 254281975 ps |
| CPU time | 10.61 seconds |
| Started | Aug 21 08:14:45 AM UTC 24 |
| Finished | Aug 21 08:14:57 AM UTC 24 |
| Peak memory | 229216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opent itan/hw/dv/tools/sim.tcl +ntb_random_seed=983171365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/ cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.983171365 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_csr_rw.571014936 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 167742514 ps |
| CPU time | 11.39 seconds |
| Started | Aug 21 08:14:41 AM UTC 24 |
| Finished | Aug 21 08:14:54 AM UTC 24 |
| Peak memory | 221808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=571014936 - assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ct rl_csr_rw.571014936 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2747622758 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 9359482039 ps |
| CPU time | 55.86 seconds |
| Started | Aug 21 08:14:41 AM UTC 24 |
| Finished | Aug 21 08:15:39 AM UTC 24 |
| Peak memory | 225996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed =2747622758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 6.rom_ctrl_passthru_mem_tl_intg_err.2747622758 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2256918861 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 508036980 ps |
| CPU time | 13.41 seconds |
| Started | Aug 21 08:14:43 AM UTC 24 |
| Finished | Aug 21 08:14:58 AM UTC 24 |
| Peak memory | 221808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_rando m_seed=2256918861 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 6.rom_ctrl_same_csr_outstanding.2256918861 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_tl_errors.4291071519 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 251123174 ps |
| CPU time | 21.64 seconds |
| Started | Aug 21 08:14:41 AM UTC 24 |
| Finished | Aug 21 08:15:04 AM UTC 24 |
| Peak memory | 229316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4291071519 -as sert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl _tl_errors.4291071519 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.13666591 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 322333101 ps |
| CPU time | 94.48 seconds |
| Started | Aug 21 08:14:41 AM UTC 24 |
| Finished | Aug 21 08:16:18 AM UTC 24 |
| Peak memory | 223872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=13 666591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_intg_err.13666591 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3756142311 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 1008688374 ps |
| CPU time | 11.13 seconds |
| Started | Aug 21 08:14:53 AM UTC 24 |
| Finished | Aug 21 08:15:05 AM UTC 24 |
| Peak memory | 225912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opent itan/hw/dv/tools/sim.tcl +ntb_random_seed=3756142311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage /cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.3756142311 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2213975261 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 994973106 ps |
| CPU time | 14.14 seconds |
| Started | Aug 21 08:14:51 AM UTC 24 |
| Finished | Aug 21 08:15:06 AM UTC 24 |
| Peak memory | 221888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2213975261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c trl_csr_rw.2213975261 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3533900467 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 1587461880 ps |
| CPU time | 65.35 seconds |
| Started | Aug 21 08:14:46 AM UTC 24 |
| Finished | Aug 21 08:15:53 AM UTC 24 |
| Peak memory | 229184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed =3533900467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 7.rom_ctrl_passthru_mem_tl_intg_err.3533900467 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.785286520 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 261790436 ps |
| CPU time | 12.27 seconds |
| Started | Aug 21 08:14:52 AM UTC 24 |
| Finished | Aug 21 08:15:05 AM UTC 24 |
| Peak memory | 224060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_rando m_seed=785286520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_same_csr_outstanding.785286520 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2024495947 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 1177857903 ps |
| CPU time | 13.74 seconds |
| Started | Aug 21 08:14:49 AM UTC 24 |
| Finished | Aug 21 08:15:03 AM UTC 24 |
| Peak memory | 229248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2024495947 -as sert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl _tl_errors.2024495947 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2608953691 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 385243586 ps |
| CPU time | 100.12 seconds |
| Started | Aug 21 08:14:51 AM UTC 24 |
| Finished | Aug 21 08:16:33 AM UTC 24 |
| Peak memory | 229216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=26 08953691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 7.rom_ctrl_tl_intg_err.2608953691 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3647413849 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 262794123 ps |
| CPU time | 11.44 seconds |
| Started | Aug 21 08:14:56 AM UTC 24 |
| Finished | Aug 21 08:15:09 AM UTC 24 |
| Peak memory | 227960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opent itan/hw/dv/tools/sim.tcl +ntb_random_seed=3647413849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage /cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.3647413849 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3565591128 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 687957432 ps |
| CPU time | 7.37 seconds |
| Started | Aug 21 08:14:55 AM UTC 24 |
| Finished | Aug 21 08:15:03 AM UTC 24 |
| Peak memory | 224000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3565591128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c trl_csr_rw.3565591128 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2674621575 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 1035048845 ps |
| CPU time | 74.49 seconds |
| Started | Aug 21 08:14:53 AM UTC 24 |
| Finished | Aug 21 08:16:09 AM UTC 24 |
| Peak memory | 226000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed =2674621575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 8.rom_ctrl_passthru_mem_tl_intg_err.2674621575 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2755022111 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 2051510560 ps |
| CPU time | 14.44 seconds |
| Started | Aug 21 08:14:56 AM UTC 24 |
| Finished | Aug 21 08:15:12 AM UTC 24 |
| Peak memory | 221808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_rando m_seed=2755022111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 8.rom_ctrl_same_csr_outstanding.2755022111 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_tl_errors.4211300695 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 167778754 ps |
| CPU time | 11.57 seconds |
| Started | Aug 21 08:14:54 AM UTC 24 |
| Finished | Aug 21 08:15:07 AM UTC 24 |
| Peak memory | 228128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4211300695 -as sert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl _tl_errors.4211300695 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.685282989 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 816095988 ps |
| CPU time | 156.36 seconds |
| Started | Aug 21 08:14:54 AM UTC 24 |
| Finished | Aug 21 08:17:33 AM UTC 24 |
| Peak memory | 224060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=68 5282989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_intg_err.685282989 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2549471051 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 645904856 ps |
| CPU time | 12.31 seconds |
| Started | Aug 21 08:15:05 AM UTC 24 |
| Finished | Aug 21 08:15:18 AM UTC 24 |
| Peak memory | 228016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opent itan/hw/dv/tools/sim.tcl +ntb_random_seed=2549471051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage /cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.2549471051 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_csr_rw.4267533218 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 690069946 ps |
| CPU time | 10.78 seconds |
| Started | Aug 21 08:14:58 AM UTC 24 |
| Finished | Aug 21 08:15:10 AM UTC 24 |
| Peak memory | 221760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4267533218 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c trl_csr_rw.4267533218 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2346506336 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 4470406357 ps |
| CPU time | 54.89 seconds |
| Started | Aug 21 08:14:57 AM UTC 24 |
| Finished | Aug 21 08:15:54 AM UTC 24 |
| Peak memory | 228044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed =2346506336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 9.rom_ctrl_passthru_mem_tl_intg_err.2346506336 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1208779238 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 174614182 ps |
| CPU time | 7.44 seconds |
| Started | Aug 21 08:15:05 AM UTC 24 |
| Finished | Aug 21 08:15:13 AM UTC 24 |
| Peak memory | 221808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_rando m_seed=1208779238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 9.rom_ctrl_same_csr_outstanding.1208779238 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2488030372 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 1375170017 ps |
| CPU time | 11.7 seconds |
| Started | Aug 21 08:14:58 AM UTC 24 |
| Finished | Aug 21 08:15:11 AM UTC 24 |
| Peak memory | 228192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2488030372 -as sert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl _tl_errors.2488030372 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1607080116 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 1041948090 ps |
| CPU time | 85.61 seconds |
| Started | Aug 21 08:14:58 AM UTC 24 |
| Finished | Aug 21 08:16:26 AM UTC 24 |
| Peak memory | 225916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=16 07080116 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 9.rom_ctrl_tl_intg_err.1607080116 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2650329042 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 9734000353 ps |
| CPU time | 332.17 seconds |
| Started | Aug 21 08:08:19 AM UTC 24 |
| Finished | Aug 21 08:13:55 AM UTC 24 |
| Peak memory | 261592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2650329 042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 0.rom_ctrl_corrupt_sig_fatal_chk.2650329042 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_max_throughput_chk.4241711538 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 675992310 ps |
| CPU time | 10.84 seconds |
| Started | Aug 21 08:08:19 AM UTC 24 |
| Finished | Aug 21 08:08:31 AM UTC 24 |
| Peak memory | 228568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4241711538 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_thr oughput_chk.4241711538 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_sec_cm.3958174355 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 1479503734 ps |
| CPU time | 261.78 seconds |
| Started | Aug 21 08:08:19 AM UTC 24 |
| Finished | Aug 21 08:12:45 AM UTC 24 |
| Peak memory | 259408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3958174355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_s ec_cm.3958174355 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_sec_cm/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_smoke.4022393577 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 225523575 ps |
| CPU time | 9.3 seconds |
| Started | Aug 21 08:08:19 AM UTC 24 |
| Finished | Aug 21 08:08:29 AM UTC 24 |
| Peak memory | 225392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4022393577 -assert nopostproc +UVM_ TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.4022393577 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_alert_test.4134881550 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 249806224 ps |
| CPU time | 8.56 seconds |
| Started | Aug 21 08:08:19 AM UTC 24 |
| Finished | Aug 21 08:08:29 AM UTC 24 |
| Peak memory | 227492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=413488155 0 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_ alert_test.4134881550 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_max_throughput_chk.2399863717 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 190039409 ps |
| CPU time | 9.56 seconds |
| Started | Aug 21 08:08:19 AM UTC 24 |
| Finished | Aug 21 08:08:30 AM UTC 24 |
| Peak memory | 228080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2399863717 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_thr oughput_chk.2399863717 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_sec_cm.2963547882 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 725040099 ps |
| CPU time | 247.29 seconds |
| Started | Aug 21 08:08:19 AM UTC 24 |
| Finished | Aug 21 08:12:30 AM UTC 24 |
| Peak memory | 259464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2963547882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_s ec_cm.2963547882 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_sec_cm/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_alert_test.1559925038 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 663474455 ps |
| CPU time | 11.09 seconds |
| Started | Aug 21 08:08:44 AM UTC 24 |
| Finished | Aug 21 08:08:56 AM UTC 24 |
| Peak memory | 227676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=155992503 8 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl _alert_test.1559925038 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.3994884752 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 3260273829 ps |
| CPU time | 204.16 seconds |
| Started | Aug 21 08:08:42 AM UTC 24 |
| Finished | Aug 21 08:12:11 AM UTC 24 |
| Peak memory | 259448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3994884 752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 10.rom_ctrl_corrupt_sig_fatal_chk.3994884752 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_kmac_err_chk.1650172292 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 991759608 ps |
| CPU time | 20.24 seconds |
| Started | Aug 21 08:08:42 AM UTC 24 |
| Finished | Aug 21 08:09:05 AM UTC 24 |
| Peak memory | 228040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1650172292 -assert nopostproc +UVM_ TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.1650172292 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_max_throughput_chk.1098911183 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 1056217047 ps |
| CPU time | 15.52 seconds |
| Started | Aug 21 08:08:42 AM UTC 24 |
| Finished | Aug 21 08:09:02 AM UTC 24 |
| Peak memory | 228564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1098911183 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_th roughput_chk.1098911183 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.3054689122 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 13333604680 ps |
| CPU time | 203.49 seconds |
| Started | Aug 21 08:08:42 AM UTC 24 |
| Finished | Aug 21 08:12:10 AM UTC 24 |
| Peak memory | 235032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_n s=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3054689122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_ 64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all_with_rand_reset.3054689122 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_alert_test.1977856677 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 171986588 ps |
| CPU time | 9.02 seconds |
| Started | Aug 21 08:08:50 AM UTC 24 |
| Finished | Aug 21 08:09:00 AM UTC 24 |
| Peak memory | 227676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=197785667 7 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl _alert_test.1977856677 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.3131554555 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 24076982170 ps |
| CPU time | 362.38 seconds |
| Started | Aug 21 08:08:50 AM UTC 24 |
| Finished | Aug 21 08:14:58 AM UTC 24 |
| Peak memory | 260448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3131554 555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 11.rom_ctrl_corrupt_sig_fatal_chk.3131554555 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_max_throughput_chk.177289214 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 613076152 ps |
| CPU time | 12.1 seconds |
| Started | Aug 21 08:08:50 AM UTC 24 |
| Finished | Aug 21 08:09:03 AM UTC 24 |
| Peak memory | 227440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=177289214 -assert no postproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_thr oughput_chk.177289214 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all.3524205074 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 573427208 ps |
| CPU time | 43.12 seconds |
| Started | Aug 21 08:08:44 AM UTC 24 |
| Finished | Aug 21 08:09:29 AM UTC 24 |
| Peak memory | 228820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10 000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim .tcl +ntb_random_seed=3524205074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 11.rom_ctrl_stress_all.3524205074 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.3489329968 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 5040322128 ps |
| CPU time | 195.48 seconds |
| Started | Aug 21 08:08:50 AM UTC 24 |
| Finished | Aug 21 08:12:09 AM UTC 24 |
| Peak memory | 235372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_n s=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3489329968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_ 64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all_with_rand_reset.3489329968 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_alert_test.862426292 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 252392343 ps |
| CPU time | 13.59 seconds |
| Started | Aug 21 08:08:55 AM UTC 24 |
| Finished | Aug 21 08:09:10 AM UTC 24 |
| Peak memory | 227556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=862426292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_ alert_test.862426292 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_kmac_err_chk.945037210 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 4034294789 ps |
| CPU time | 36.78 seconds |
| Started | Aug 21 08:08:53 AM UTC 24 |
| Finished | Aug 21 08:09:31 AM UTC 24 |
| Peak memory | 228688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=945037210 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.945037210 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_max_throughput_chk.263318013 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 267094990 ps |
| CPU time | 14.63 seconds |
| Started | Aug 21 08:08:52 AM UTC 24 |
| Finished | Aug 21 08:09:09 AM UTC 24 |
| Peak memory | 227808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=263318013 -assert no postproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_thr oughput_chk.263318013 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all.469386617 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 1858120182 ps |
| CPU time | 39.12 seconds |
| Started | Aug 21 08:08:52 AM UTC 24 |
| Finished | Aug 21 08:09:33 AM UTC 24 |
| Peak memory | 228568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10 000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim .tcl +ntb_random_seed=469386617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 12.rom_ctrl_stress_all.469386617 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.551759843 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 8391701697 ps |
| CPU time | 203.28 seconds |
| Started | Aug 21 08:08:55 AM UTC 24 |
| Finished | Aug 21 08:12:21 AM UTC 24 |
| Peak memory | 235180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_n s=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=551759843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_6 4kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_stress_all_with_rand_reset.551759843 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_alert_test.457204470 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 332727578 ps |
| CPU time | 10.81 seconds |
| Started | Aug 21 08:08:59 AM UTC 24 |
| Finished | Aug 21 08:09:12 AM UTC 24 |
| Peak memory | 227620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=457204470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_ alert_test.457204470 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3765463554 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 2411617904 ps |
| CPU time | 149.73 seconds |
| Started | Aug 21 08:08:57 AM UTC 24 |
| Finished | Aug 21 08:11:29 AM UTC 24 |
| Peak memory | 228460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3765463 554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 13.rom_ctrl_corrupt_sig_fatal_chk.3765463554 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_kmac_err_chk.3951982055 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 333243527 ps |
| CPU time | 20.21 seconds |
| Started | Aug 21 08:08:57 AM UTC 24 |
| Finished | Aug 21 08:09:19 AM UTC 24 |
| Peak memory | 228884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3951982055 -assert nopostproc +UVM_ TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.3951982055 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_max_throughput_chk.1444427482 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 1069546982 ps |
| CPU time | 13.46 seconds |
| Started | Aug 21 08:08:55 AM UTC 24 |
| Finished | Aug 21 08:09:10 AM UTC 24 |
| Peak memory | 228372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1444427482 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_th roughput_chk.1444427482 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all.2874224097 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 376101480 ps |
| CPU time | 45.21 seconds |
| Started | Aug 21 08:08:55 AM UTC 24 |
| Finished | Aug 21 08:09:42 AM UTC 24 |
| Peak memory | 228564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10 000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim .tcl +ntb_random_seed=2874224097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 13.rom_ctrl_stress_all.2874224097 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.234946057 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 13910171097 ps |
| CPU time | 177.43 seconds |
| Started | Aug 21 08:08:57 AM UTC 24 |
| Finished | Aug 21 08:11:58 AM UTC 24 |
| Peak memory | 246348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_n s=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=234946057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_6 4kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all_with_rand_reset.234946057 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_alert_test.3918502174 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 496444126 ps |
| CPU time | 9.46 seconds |
| Started | Aug 21 08:09:01 AM UTC 24 |
| Finished | Aug 21 08:09:12 AM UTC 24 |
| Peak memory | 228048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=391850217 4 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl _alert_test.3918502174 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.2547858596 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 11345218191 ps |
| CPU time | 320.63 seconds |
| Started | Aug 21 08:08:59 AM UTC 24 |
| Finished | Aug 21 08:14:25 AM UTC 24 |
| Peak memory | 259500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2547858 596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 14.rom_ctrl_corrupt_sig_fatal_chk.2547858596 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_kmac_err_chk.4181479613 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 691327365 ps |
| CPU time | 18.37 seconds |
| Started | Aug 21 08:09:01 AM UTC 24 |
| Finished | Aug 21 08:09:21 AM UTC 24 |
| Peak memory | 228628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4181479613 -assert nopostproc +UVM_ TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.4181479613 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_max_throughput_chk.1449980459 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 504582621 ps |
| CPU time | 13.35 seconds |
| Started | Aug 21 08:08:59 AM UTC 24 |
| Finished | Aug 21 08:09:14 AM UTC 24 |
| Peak memory | 228028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1449980459 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_th roughput_chk.1449980459 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all.1236962230 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 4599813177 ps |
| CPU time | 23.22 seconds |
| Started | Aug 21 08:08:59 AM UTC 24 |
| Finished | Aug 21 08:09:24 AM UTC 24 |
| Peak memory | 227500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10 000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim .tcl +ntb_random_seed=1236962230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 14.rom_ctrl_stress_all.1236962230 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.1569740916 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 5674569795 ps |
| CPU time | 84.95 seconds |
| Started | Aug 21 08:09:01 AM UTC 24 |
| Finished | Aug 21 08:10:28 AM UTC 24 |
| Peak memory | 235304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_n s=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1569740916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_ 64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all_with_rand_reset.1569740916 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_alert_test.370214450 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 945209510 ps |
| CPU time | 10.85 seconds |
| Started | Aug 21 08:09:06 AM UTC 24 |
| Finished | Aug 21 08:09:18 AM UTC 24 |
| Peak memory | 227492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=370214450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_ alert_test.370214450 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.3698721907 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 4249676176 ps |
| CPU time | 293.5 seconds |
| Started | Aug 21 08:09:03 AM UTC 24 |
| Finished | Aug 21 08:14:01 AM UTC 24 |
| Peak memory | 227700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3698721 907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 15.rom_ctrl_corrupt_sig_fatal_chk.3698721907 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_kmac_err_chk.739477946 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 566312680 ps |
| CPU time | 29.24 seconds |
| Started | Aug 21 08:09:04 AM UTC 24 |
| Finished | Aug 21 08:09:34 AM UTC 24 |
| Peak memory | 228624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=739477946 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.739477946 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_max_throughput_chk.1636339428 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 1291326089 ps |
| CPU time | 15.49 seconds |
| Started | Aug 21 08:09:03 AM UTC 24 |
| Finished | Aug 21 08:09:20 AM UTC 24 |
| Peak memory | 227440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1636339428 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_th roughput_chk.1636339428 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all.1644477491 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 527574725 ps |
| CPU time | 37.89 seconds |
| Started | Aug 21 08:09:03 AM UTC 24 |
| Finished | Aug 21 08:09:43 AM UTC 24 |
| Peak memory | 228644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10 000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim .tcl +ntb_random_seed=1644477491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 15.rom_ctrl_stress_all.1644477491 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.2557674780 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 2289355781 ps |
| CPU time | 108.5 seconds |
| Started | Aug 21 08:09:04 AM UTC 24 |
| Finished | Aug 21 08:10:54 AM UTC 24 |
| Peak memory | 239080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_n s=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2557674780 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_ 64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all_with_rand_reset.2557674780 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_alert_test.2113584108 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 169018598 ps |
| CPU time | 8.5 seconds |
| Started | Aug 21 08:09:12 AM UTC 24 |
| Finished | Aug 21 08:09:22 AM UTC 24 |
| Peak memory | 227856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=211358410 8 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl _alert_test.2113584108 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.1265303113 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 14690402077 ps |
| CPU time | 240.73 seconds |
| Started | Aug 21 08:09:06 AM UTC 24 |
| Finished | Aug 21 08:13:10 AM UTC 24 |
| Peak memory | 225652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1265303 113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 16.rom_ctrl_corrupt_sig_fatal_chk.1265303113 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_kmac_err_chk.2822250563 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 9417121694 ps |
| CPU time | 36.1 seconds |
| Started | Aug 21 08:09:08 AM UTC 24 |
| Finished | Aug 21 08:09:45 AM UTC 24 |
| Peak memory | 228692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2822250563 -assert nopostproc +UVM_ TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.2822250563 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_max_throughput_chk.1473280842 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 281195512 ps |
| CPU time | 18.64 seconds |
| Started | Aug 21 08:09:06 AM UTC 24 |
| Finished | Aug 21 08:09:26 AM UTC 24 |
| Peak memory | 228536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1473280842 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_th roughput_chk.1473280842 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all.3657766047 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 296362326 ps |
| CPU time | 16.69 seconds |
| Started | Aug 21 08:09:06 AM UTC 24 |
| Finished | Aug 21 08:09:24 AM UTC 24 |
| Peak memory | 228756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10 000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim .tcl +ntb_random_seed=3657766047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 16.rom_ctrl_stress_all.3657766047 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.1369945363 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 21044463434 ps |
| CPU time | 208.84 seconds |
| Started | Aug 21 08:09:10 AM UTC 24 |
| Finished | Aug 21 08:12:42 AM UTC 24 |
| Peak memory | 238168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_n s=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1369945363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_ 64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all_with_rand_reset.1369945363 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_alert_test.2931341107 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 506378985 ps |
| CPU time | 10.46 seconds |
| Started | Aug 21 08:09:16 AM UTC 24 |
| Finished | Aug 21 08:09:28 AM UTC 24 |
| Peak memory | 228000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=293134110 7 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl _alert_test.2931341107 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2256359786 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 17311830118 ps |
| CPU time | 276.95 seconds |
| Started | Aug 21 08:09:12 AM UTC 24 |
| Finished | Aug 21 08:13:53 AM UTC 24 |
| Peak memory | 259468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2256359 786 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 17.rom_ctrl_corrupt_sig_fatal_chk.2256359786 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_kmac_err_chk.2305794241 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 2063168837 ps |
| CPU time | 23.78 seconds |
| Started | Aug 21 08:09:14 AM UTC 24 |
| Finished | Aug 21 08:09:39 AM UTC 24 |
| Peak memory | 228628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2305794241 -assert nopostproc +UVM_ TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.2305794241 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_max_throughput_chk.334924449 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 356805278 ps |
| CPU time | 14.28 seconds |
| Started | Aug 21 08:09:12 AM UTC 24 |
| Finished | Aug 21 08:09:28 AM UTC 24 |
| Peak memory | 227984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=334924449 -assert no postproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_thr oughput_chk.334924449 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all.372383304 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 3239004660 ps |
| CPU time | 49.56 seconds |
| Started | Aug 21 08:09:12 AM UTC 24 |
| Finished | Aug 21 08:10:03 AM UTC 24 |
| Peak memory | 228708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10 000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim .tcl +ntb_random_seed=372383304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 17.rom_ctrl_stress_all.372383304 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.1077924011 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 3570712381 ps |
| CPU time | 264.99 seconds |
| Started | Aug 21 08:09:16 AM UTC 24 |
| Finished | Aug 21 08:13:45 AM UTC 24 |
| Peak memory | 246424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_n s=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1077924011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_ 64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.1077924011 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_alert_test.4082040973 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 356180372 ps |
| CPU time | 14.3 seconds |
| Started | Aug 21 08:09:21 AM UTC 24 |
| Finished | Aug 21 08:09:36 AM UTC 24 |
| Peak memory | 227688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=408204097 3 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl _alert_test.4082040973 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.1416670811 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 6742452734 ps |
| CPU time | 235.96 seconds |
| Started | Aug 21 08:09:19 AM UTC 24 |
| Finished | Aug 21 08:13:18 AM UTC 24 |
| Peak memory | 258516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1416670 811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 18.rom_ctrl_corrupt_sig_fatal_chk.1416670811 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_kmac_err_chk.4270565996 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 505547395 ps |
| CPU time | 25.5 seconds |
| Started | Aug 21 08:09:19 AM UTC 24 |
| Finished | Aug 21 08:09:45 AM UTC 24 |
| Peak memory | 228624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4270565996 -assert nopostproc +UVM_ TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.4270565996 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_max_throughput_chk.1864822093 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 411142863 ps |
| CPU time | 15.15 seconds |
| Started | Aug 21 08:09:19 AM UTC 24 |
| Finished | Aug 21 08:09:35 AM UTC 24 |
| Peak memory | 228316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1864822093 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_th roughput_chk.1864822093 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all.2769997817 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 1462553123 ps |
| CPU time | 26.3 seconds |
| Started | Aug 21 08:09:16 AM UTC 24 |
| Finished | Aug 21 08:09:44 AM UTC 24 |
| Peak memory | 228652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10 000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim .tcl +ntb_random_seed=2769997817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 18.rom_ctrl_stress_all.2769997817 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_alert_test.425680859 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 346675659 ps |
| CPU time | 11.76 seconds |
| Started | Aug 21 08:09:27 AM UTC 24 |
| Finished | Aug 21 08:09:40 AM UTC 24 |
| Peak memory | 227748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=425680859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_ alert_test.425680859 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.2375740780 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 9013706606 ps |
| CPU time | 260.04 seconds |
| Started | Aug 21 08:09:23 AM UTC 24 |
| Finished | Aug 21 08:13:47 AM UTC 24 |
| Peak memory | 245576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2375740 780 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 19.rom_ctrl_corrupt_sig_fatal_chk.2375740780 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_kmac_err_chk.1838442917 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 332401624 ps |
| CPU time | 24.85 seconds |
| Started | Aug 21 08:09:25 AM UTC 24 |
| Finished | Aug 21 08:09:51 AM UTC 24 |
| Peak memory | 228884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1838442917 -assert nopostproc +UVM_ TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.1838442917 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_max_throughput_chk.2080259322 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 2019752032 ps |
| CPU time | 16.81 seconds |
| Started | Aug 21 08:09:23 AM UTC 24 |
| Finished | Aug 21 08:09:41 AM UTC 24 |
| Peak memory | 228360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2080259322 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_th roughput_chk.2080259322 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all.1924354215 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 295671682 ps |
| CPU time | 17.99 seconds |
| Started | Aug 21 08:09:21 AM UTC 24 |
| Finished | Aug 21 08:09:40 AM UTC 24 |
| Peak memory | 228756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10 000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim .tcl +ntb_random_seed=1924354215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 19.rom_ctrl_stress_all.1924354215 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.1763725956 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 3792220458 ps |
| CPU time | 48.71 seconds |
| Started | Aug 21 08:09:25 AM UTC 24 |
| Finished | Aug 21 08:10:15 AM UTC 24 |
| Peak memory | 233128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_n s=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1763725956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_ 64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all_with_rand_reset.1763725956 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3891655618 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 119298909285 ps |
| CPU time | 594.57 seconds |
| Started | Aug 21 08:08:19 AM UTC 24 |
| Finished | Aug 21 08:18:31 AM UTC 24 |
| Peak memory | 230848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3891655 618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 2.rom_ctrl_corrupt_sig_fatal_chk.3891655618 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_kmac_err_chk.3640539889 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 893318203 ps |
| CPU time | 17.6 seconds |
| Started | Aug 21 08:08:19 AM UTC 24 |
| Finished | Aug 21 08:08:48 AM UTC 24 |
| Peak memory | 228816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3640539889 -assert nopostproc +UVM_ TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.3640539889 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_max_throughput_chk.3406712005 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 1078714077 ps |
| CPU time | 10.66 seconds |
| Started | Aug 21 08:08:19 AM UTC 24 |
| Finished | Aug 21 08:08:31 AM UTC 24 |
| Peak memory | 228256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3406712005 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_thr oughput_chk.3406712005 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_sec_cm.2823032177 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 503752531 ps |
| CPU time | 274.62 seconds |
| Started | Aug 21 08:08:19 AM UTC 24 |
| Finished | Aug 21 08:13:08 AM UTC 24 |
| Peak memory | 258508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2823032177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_s ec_cm.2823032177 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_sec_cm/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_smoke.2570485517 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 726860915 ps |
| CPU time | 9.21 seconds |
| Started | Aug 21 08:08:19 AM UTC 24 |
| Finished | Aug 21 08:08:30 AM UTC 24 |
| Peak memory | 225584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2570485517 -assert nopostproc +UVM_ TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.2570485517 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.1218268303 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 29380964471 ps |
| CPU time | 185.3 seconds |
| Started | Aug 21 08:08:19 AM UTC 24 |
| Finished | Aug 21 08:11:38 AM UTC 24 |
| Peak memory | 239332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_n s=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1218268303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_ 64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.1218268303 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_alert_test.3747119732 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 1032284519 ps |
| CPU time | 11.79 seconds |
| Started | Aug 21 08:09:35 AM UTC 24 |
| Finished | Aug 21 08:09:47 AM UTC 24 |
| Peak memory | 227848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=374711973 2 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl _alert_test.3747119732 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/20.rom_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.2316591355 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 6518728664 ps |
| CPU time | 327.67 seconds |
| Started | Aug 21 08:09:31 AM UTC 24 |
| Finished | Aug 21 08:15:04 AM UTC 24 |
| Peak memory | 258468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2316591 355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 20.rom_ctrl_corrupt_sig_fatal_chk.2316591355 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/20.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_kmac_err_chk.3687834692 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 664972959 ps |
| CPU time | 23.61 seconds |
| Started | Aug 21 08:09:32 AM UTC 24 |
| Finished | Aug 21 08:09:58 AM UTC 24 |
| Peak memory | 228628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3687834692 -assert nopostproc +UVM_ TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.3687834692 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/20.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_max_throughput_chk.2601431321 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 261674053 ps |
| CPU time | 15.31 seconds |
| Started | Aug 21 08:09:29 AM UTC 24 |
| Finished | Aug 21 08:09:46 AM UTC 24 |
| Peak memory | 228568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2601431321 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_th roughput_chk.2601431321 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/20.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all.1440959642 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 1545411578 ps |
| CPU time | 45.4 seconds |
| Started | Aug 21 08:09:29 AM UTC 24 |
| Finished | Aug 21 08:10:16 AM UTC 24 |
| Peak memory | 228640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10 000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim .tcl +ntb_random_seed=1440959642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 20.rom_ctrl_stress_all.1440959642 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/20.rom_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.2314068945 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 1109746901 ps |
| CPU time | 33.71 seconds |
| Started | Aug 21 08:09:34 AM UTC 24 |
| Finished | Aug 21 08:10:10 AM UTC 24 |
| Peak memory | 230824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_n s=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2314068945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_ 64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.2314068945 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/20.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_alert_test.434708003 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 172731907 ps |
| CPU time | 9.48 seconds |
| Started | Aug 21 08:09:41 AM UTC 24 |
| Finished | Aug 21 08:09:51 AM UTC 24 |
| Peak memory | 227684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=434708003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_ alert_test.434708003 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/21.rom_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3207962602 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 4531728216 ps |
| CPU time | 344.3 seconds |
| Started | Aug 21 08:09:40 AM UTC 24 |
| Finished | Aug 21 08:15:29 AM UTC 24 |
| Peak memory | 247176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3207962 602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 21.rom_ctrl_corrupt_sig_fatal_chk.3207962602 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/21.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_kmac_err_chk.762601324 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 2061181852 ps |
| CPU time | 23.26 seconds |
| Started | Aug 21 08:09:40 AM UTC 24 |
| Finished | Aug 21 08:10:04 AM UTC 24 |
| Peak memory | 228624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=762601324 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.762601324 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/21.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_max_throughput_chk.2487026027 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 187426772 ps |
| CPU time | 11.84 seconds |
| Started | Aug 21 08:09:37 AM UTC 24 |
| Finished | Aug 21 08:09:50 AM UTC 24 |
| Peak memory | 228316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2487026027 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_th roughput_chk.2487026027 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/21.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all.4134148065 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 755619416 ps |
| CPU time | 36.42 seconds |
| Started | Aug 21 08:09:37 AM UTC 24 |
| Finished | Aug 21 08:10:14 AM UTC 24 |
| Peak memory | 227772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10 000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim .tcl +ntb_random_seed=4134148065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 21.rom_ctrl_stress_all.4134148065 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/21.rom_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.2554754554 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 13945536849 ps |
| CPU time | 149.96 seconds |
| Started | Aug 21 08:09:41 AM UTC 24 |
| Finished | Aug 21 08:12:13 AM UTC 24 |
| Peak memory | 246128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_n s=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2554754554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_ 64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all_with_rand_reset.2554754554 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/21.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_alert_test.2542910687 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 175633689 ps |
| CPU time | 8.33 seconds |
| Started | Aug 21 08:09:46 AM UTC 24 |
| Finished | Aug 21 08:09:56 AM UTC 24 |
| Peak memory | 227740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=254291068 7 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl _alert_test.2542910687 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/22.rom_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.224323621 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 4985689130 ps |
| CPU time | 297 seconds |
| Started | Aug 21 08:09:43 AM UTC 24 |
| Finished | Aug 21 08:14:44 AM UTC 24 |
| Peak memory | 246584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2243236 21 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 22.rom_ctrl_corrupt_sig_fatal_chk.224323621 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/22.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_kmac_err_chk.3284909092 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 519764922 ps |
| CPU time | 24.5 seconds |
| Started | Aug 21 08:09:43 AM UTC 24 |
| Finished | Aug 21 08:10:09 AM UTC 24 |
| Peak memory | 228628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3284909092 -assert nopostproc +UVM_ TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.3284909092 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/22.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_max_throughput_chk.3367859178 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 535399271 ps |
| CPU time | 15.43 seconds |
| Started | Aug 21 08:09:42 AM UTC 24 |
| Finished | Aug 21 08:09:59 AM UTC 24 |
| Peak memory | 227440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3367859178 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_th roughput_chk.3367859178 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/22.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all.3320873626 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 6121798239 ps |
| CPU time | 60.93 seconds |
| Started | Aug 21 08:09:42 AM UTC 24 |
| Finished | Aug 21 08:10:44 AM UTC 24 |
| Peak memory | 230740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10 000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim .tcl +ntb_random_seed=3320873626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 22.rom_ctrl_stress_all.3320873626 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/22.rom_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.1900866071 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 929326193 ps |
| CPU time | 38.65 seconds |
| Started | Aug 21 08:09:45 AM UTC 24 |
| Finished | Aug 21 08:10:25 AM UTC 24 |
| Peak memory | 232872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_n s=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1900866071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_ 64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all_with_rand_reset.1900866071 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/22.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_alert_test.531853677 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 4092161085 ps |
| CPU time | 21.79 seconds |
| Started | Aug 21 08:09:53 AM UTC 24 |
| Finished | Aug 21 08:10:16 AM UTC 24 |
| Peak memory | 227620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=531853677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_ alert_test.531853677 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/23.rom_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.1536984895 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 23460039926 ps |
| CPU time | 254.2 seconds |
| Started | Aug 21 08:09:48 AM UTC 24 |
| Finished | Aug 21 08:14:06 AM UTC 24 |
| Peak memory | 248948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1536984 895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 23.rom_ctrl_corrupt_sig_fatal_chk.1536984895 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/23.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_kmac_err_chk.3575688785 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 344190011 ps |
| CPU time | 21.29 seconds |
| Started | Aug 21 08:09:50 AM UTC 24 |
| Finished | Aug 21 08:10:13 AM UTC 24 |
| Peak memory | 228624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3575688785 -assert nopostproc +UVM_ TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.3575688785 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/23.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_max_throughput_chk.3441744508 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 1031702677 ps |
| CPU time | 20.71 seconds |
| Started | Aug 21 08:09:46 AM UTC 24 |
| Finished | Aug 21 08:10:08 AM UTC 24 |
| Peak memory | 228568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3441744508 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_th roughput_chk.3441744508 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/23.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all.708982916 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 380401314 ps |
| CPU time | 39.97 seconds |
| Started | Aug 21 08:09:46 AM UTC 24 |
| Finished | Aug 21 08:10:28 AM UTC 24 |
| Peak memory | 228836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10 000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim .tcl +ntb_random_seed=708982916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 23.rom_ctrl_stress_all.708982916 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/23.rom_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.2715219551 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 22986849484 ps |
| CPU time | 115.08 seconds |
| Started | Aug 21 08:09:52 AM UTC 24 |
| Finished | Aug 21 08:11:49 AM UTC 24 |
| Peak memory | 246356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_n s=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2715219551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_ 64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all_with_rand_reset.2715219551 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/23.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_alert_test.912992397 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 168992479 ps |
| CPU time | 11.7 seconds |
| Started | Aug 21 08:10:09 AM UTC 24 |
| Finished | Aug 21 08:10:22 AM UTC 24 |
| Peak memory | 227864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=912992397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_ alert_test.912992397 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/24.rom_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.4093509026 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 1981637692 ps |
| CPU time | 141.29 seconds |
| Started | Aug 21 08:10:00 AM UTC 24 |
| Finished | Aug 21 08:12:24 AM UTC 24 |
| Peak memory | 243464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4093509 026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 24.rom_ctrl_corrupt_sig_fatal_chk.4093509026 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/24.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_kmac_err_chk.2354640445 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 339732197 ps |
| CPU time | 20.78 seconds |
| Started | Aug 21 08:10:04 AM UTC 24 |
| Finished | Aug 21 08:10:26 AM UTC 24 |
| Peak memory | 228564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2354640445 -assert nopostproc +UVM_ TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.2354640445 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/24.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_max_throughput_chk.510866722 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 259261146 ps |
| CPU time | 12.52 seconds |
| Started | Aug 21 08:09:59 AM UTC 24 |
| Finished | Aug 21 08:10:12 AM UTC 24 |
| Peak memory | 227980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=510866722 -assert no postproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_thr oughput_chk.510866722 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/24.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all.1570700083 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 1132983718 ps |
| CPU time | 16.93 seconds |
| Started | Aug 21 08:09:57 AM UTC 24 |
| Finished | Aug 21 08:10:15 AM UTC 24 |
| Peak memory | 225388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10 000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim .tcl +ntb_random_seed=1570700083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 24.rom_ctrl_stress_all.1570700083 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/24.rom_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.1207920454 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 2746399128 ps |
| CPU time | 49.35 seconds |
| Started | Aug 21 08:10:05 AM UTC 24 |
| Finished | Aug 21 08:10:56 AM UTC 24 |
| Peak memory | 231016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_n s=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1207920454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_ 64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all_with_rand_reset.1207920454 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/24.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_alert_test.3045686515 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 1127083345 ps |
| CPU time | 13.73 seconds |
| Started | Aug 21 08:10:15 AM UTC 24 |
| Finished | Aug 21 08:10:30 AM UTC 24 |
| Peak memory | 227484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=304568651 5 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl _alert_test.3045686515 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/25.rom_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1713618294 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 46656869130 ps |
| CPU time | 218.72 seconds |
| Started | Aug 21 08:10:12 AM UTC 24 |
| Finished | Aug 21 08:13:54 AM UTC 24 |
| Peak memory | 259464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1713618 294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 25.rom_ctrl_corrupt_sig_fatal_chk.1713618294 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/25.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_kmac_err_chk.1057092885 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 1376239839 ps |
| CPU time | 22.24 seconds |
| Started | Aug 21 08:10:13 AM UTC 24 |
| Finished | Aug 21 08:10:37 AM UTC 24 |
| Peak memory | 228692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1057092885 -assert nopostproc +UVM_ TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.1057092885 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/25.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_max_throughput_chk.3108232132 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 181330716 ps |
| CPU time | 15.45 seconds |
| Started | Aug 21 08:10:10 AM UTC 24 |
| Finished | Aug 21 08:10:27 AM UTC 24 |
| Peak memory | 228156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3108232132 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_th roughput_chk.3108232132 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/25.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all.3865235703 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 846191723 ps |
| CPU time | 14.64 seconds |
| Started | Aug 21 08:10:10 AM UTC 24 |
| Finished | Aug 21 08:10:26 AM UTC 24 |
| Peak memory | 228640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10 000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim .tcl +ntb_random_seed=3865235703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 25.rom_ctrl_stress_all.3865235703 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/25.rom_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.3481974000 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 16314825875 ps |
| CPU time | 177.53 seconds |
| Started | Aug 21 08:10:14 AM UTC 24 |
| Finished | Aug 21 08:13:15 AM UTC 24 |
| Peak memory | 246552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_n s=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3481974000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_ 64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all_with_rand_reset.3481974000 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/25.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_alert_test.249621565 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 690596730 ps |
| CPU time | 10.96 seconds |
| Started | Aug 21 08:10:26 AM UTC 24 |
| Finished | Aug 21 08:10:39 AM UTC 24 |
| Peak memory | 227492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=249621565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_ alert_test.249621565 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/26.rom_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.1217882188 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 191476594234 ps |
| CPU time | 423.19 seconds |
| Started | Aug 21 08:10:17 AM UTC 24 |
| Finished | Aug 21 08:17:25 AM UTC 24 |
| Peak memory | 259556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1217882 188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 26.rom_ctrl_corrupt_sig_fatal_chk.1217882188 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/26.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_kmac_err_chk.1186149709 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 519312746 ps |
| CPU time | 24.45 seconds |
| Started | Aug 21 08:10:17 AM UTC 24 |
| Finished | Aug 21 08:10:42 AM UTC 24 |
| Peak memory | 228628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1186149709 -assert nopostproc +UVM_ TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.1186149709 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/26.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_max_throughput_chk.2324907347 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 485696643 ps |
| CPU time | 15.37 seconds |
| Started | Aug 21 08:10:16 AM UTC 24 |
| Finished | Aug 21 08:10:33 AM UTC 24 |
| Peak memory | 228244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2324907347 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_th roughput_chk.2324907347 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/26.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all.728636741 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 1164714872 ps |
| CPU time | 18.98 seconds |
| Started | Aug 21 08:10:15 AM UTC 24 |
| Finished | Aug 21 08:10:36 AM UTC 24 |
| Peak memory | 228820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10 000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim .tcl +ntb_random_seed=728636741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 26.rom_ctrl_stress_all.728636741 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/26.rom_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.1802588256 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 15011944014 ps |
| CPU time | 189.02 seconds |
| Started | Aug 21 08:10:23 AM UTC 24 |
| Finished | Aug 21 08:13:35 AM UTC 24 |
| Peak memory | 235648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_n s=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1802588256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_ 64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.1802588256 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/26.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_alert_test.3865258102 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 174653971 ps |
| CPU time | 10.23 seconds |
| Started | Aug 21 08:10:31 AM UTC 24 |
| Finished | Aug 21 08:10:43 AM UTC 24 |
| Peak memory | 227484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=386525810 2 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl _alert_test.3865258102 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/27.rom_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.1262706732 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 4517172756 ps |
| CPU time | 217.01 seconds |
| Started | Aug 21 08:10:28 AM UTC 24 |
| Finished | Aug 21 08:14:09 AM UTC 24 |
| Peak memory | 257520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1262706 732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 27.rom_ctrl_corrupt_sig_fatal_chk.1262706732 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/27.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_kmac_err_chk.3860630119 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 4099010473 ps |
| CPU time | 49.45 seconds |
| Started | Aug 21 08:10:29 AM UTC 24 |
| Finished | Aug 21 08:11:21 AM UTC 24 |
| Peak memory | 228272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3860630119 -assert nopostproc +UVM_ TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.3860630119 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/27.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_max_throughput_chk.3273933612 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 178354148 ps |
| CPU time | 12.36 seconds |
| Started | Aug 21 08:10:27 AM UTC 24 |
| Finished | Aug 21 08:10:41 AM UTC 24 |
| Peak memory | 228124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3273933612 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_th roughput_chk.3273933612 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/27.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all.4136470098 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 6614049192 ps |
| CPU time | 32.25 seconds |
| Started | Aug 21 08:10:27 AM UTC 24 |
| Finished | Aug 21 08:11:01 AM UTC 24 |
| Peak memory | 228900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10 000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim .tcl +ntb_random_seed=4136470098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 27.rom_ctrl_stress_all.4136470098 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/27.rom_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.4283071637 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 8368465279 ps |
| CPU time | 107.15 seconds |
| Started | Aug 21 08:10:29 AM UTC 24 |
| Finished | Aug 21 08:12:19 AM UTC 24 |
| Peak memory | 234984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_n s=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4283071637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_ 64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all_with_rand_reset.4283071637 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/27.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_alert_test.4122203642 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 518039458 ps |
| CPU time | 14.42 seconds |
| Started | Aug 21 08:10:41 AM UTC 24 |
| Finished | Aug 21 08:10:57 AM UTC 24 |
| Peak memory | 227776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=412220364 2 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl _alert_test.4122203642 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/28.rom_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.2075191230 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 7256260284 ps |
| CPU time | 280.75 seconds |
| Started | Aug 21 08:10:36 AM UTC 24 |
| Finished | Aug 21 08:15:21 AM UTC 24 |
| Peak memory | 228404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2075191 230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 28.rom_ctrl_corrupt_sig_fatal_chk.2075191230 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/28.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_kmac_err_chk.2482593769 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 9904096520 ps |
| CPU time | 22.07 seconds |
| Started | Aug 21 08:10:37 AM UTC 24 |
| Finished | Aug 21 08:11:01 AM UTC 24 |
| Peak memory | 227756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2482593769 -assert nopostproc +UVM_ TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.2482593769 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/28.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_max_throughput_chk.2806757786 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 284978139 ps |
| CPU time | 18.35 seconds |
| Started | Aug 21 08:10:34 AM UTC 24 |
| Finished | Aug 21 08:10:54 AM UTC 24 |
| Peak memory | 228380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2806757786 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_th roughput_chk.2806757786 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/28.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all.3149359112 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 796385985 ps |
| CPU time | 16.25 seconds |
| Started | Aug 21 08:10:31 AM UTC 24 |
| Finished | Aug 21 08:10:49 AM UTC 24 |
| Peak memory | 225392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10 000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim .tcl +ntb_random_seed=3149359112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 28.rom_ctrl_stress_all.3149359112 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/28.rom_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.3684001452 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 7757667801 ps |
| CPU time | 120.35 seconds |
| Started | Aug 21 08:10:39 AM UTC 24 |
| Finished | Aug 21 08:12:42 AM UTC 24 |
| Peak memory | 234984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_n s=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3684001452 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_ 64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.3684001452 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/28.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_alert_test.858255019 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 260861868 ps |
| CPU time | 13.48 seconds |
| Started | Aug 21 08:10:55 AM UTC 24 |
| Finished | Aug 21 08:11:10 AM UTC 24 |
| Peak memory | 227720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=858255019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_ alert_test.858255019 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/29.rom_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.4180543720 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 18483192601 ps |
| CPU time | 146.06 seconds |
| Started | Aug 21 08:10:46 AM UTC 24 |
| Finished | Aug 21 08:13:15 AM UTC 24 |
| Peak memory | 244868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4180543 720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 29.rom_ctrl_corrupt_sig_fatal_chk.4180543720 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/29.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_kmac_err_chk.2474932032 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 481798868 ps |
| CPU time | 19.54 seconds |
| Started | Aug 21 08:10:49 AM UTC 24 |
| Finished | Aug 21 08:11:10 AM UTC 24 |
| Peak memory | 228628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2474932032 -assert nopostproc +UVM_ TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.2474932032 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/29.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all.1008986182 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 2349495495 ps |
| CPU time | 43.64 seconds |
| Started | Aug 21 08:10:44 AM UTC 24 |
| Finished | Aug 21 08:11:29 AM UTC 24 |
| Peak memory | 228628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10 000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim .tcl +ntb_random_seed=1008986182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 29.rom_ctrl_stress_all.1008986182 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/29.rom_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.1074776521 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 15686850369 ps |
| CPU time | 286.41 seconds |
| Started | Aug 21 08:10:50 AM UTC 24 |
| Finished | Aug 21 08:15:40 AM UTC 24 |
| Peak memory | 246356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_n s=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1074776521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_ 64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.1074776521 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/29.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_alert_test.797250690 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 1034101550 ps |
| CPU time | 8.56 seconds |
| Started | Aug 21 08:08:23 AM UTC 24 |
| Finished | Aug 21 08:08:50 AM UTC 24 |
| Peak memory | 227800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=797250690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_a lert_test.797250690 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.800587375 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 15516101552 ps |
| CPU time | 232.86 seconds |
| Started | Aug 21 08:08:23 AM UTC 24 |
| Finished | Aug 21 08:12:29 AM UTC 24 |
| Peak memory | 225648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=8005873 75 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 3.rom_ctrl_corrupt_sig_fatal_chk.800587375 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_kmac_err_chk.107309646 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 1580303292 ps |
| CPU time | 18.68 seconds |
| Started | Aug 21 08:08:23 AM UTC 24 |
| Finished | Aug 21 08:08:53 AM UTC 24 |
| Peak memory | 228452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=107309646 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.107309646 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_max_throughput_chk.3541379987 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 185089636 ps |
| CPU time | 9.47 seconds |
| Started | Aug 21 08:08:23 AM UTC 24 |
| Finished | Aug 21 08:08:43 AM UTC 24 |
| Peak memory | 227444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3541379987 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_thr oughput_chk.3541379987 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_smoke.605323260 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 337143421 ps |
| CPU time | 9.39 seconds |
| Started | Aug 21 08:08:23 AM UTC 24 |
| Finished | Aug 21 08:08:43 AM UTC 24 |
| Peak memory | 228552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=605323260 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s cratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.605323260 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.446990418 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 10020629881 ps |
| CPU time | 125.14 seconds |
| Started | Aug 21 08:08:23 AM UTC 24 |
| Finished | Aug 21 08:10:48 AM UTC 24 |
| Peak memory | 235424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_n s=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=446990418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_6 4kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all_with_rand_reset.446990418 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_alert_test.2059320521 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 255212981 ps |
| CPU time | 13.44 seconds |
| Started | Aug 21 08:11:01 AM UTC 24 |
| Finished | Aug 21 08:11:16 AM UTC 24 |
| Peak memory | 227544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=205932052 1 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl _alert_test.2059320521 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/30.rom_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1499760136 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 12228127117 ps |
| CPU time | 451.4 seconds |
| Started | Aug 21 08:10:56 AM UTC 24 |
| Finished | Aug 21 08:18:33 AM UTC 24 |
| Peak memory | 259480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1499760 136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 30.rom_ctrl_corrupt_sig_fatal_chk.1499760136 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/30.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_kmac_err_chk.71865173 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 1981872441 ps |
| CPU time | 23.31 seconds |
| Started | Aug 21 08:10:58 AM UTC 24 |
| Finished | Aug 21 08:11:23 AM UTC 24 |
| Peak memory | 228624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=71865173 -assert nopostproc +UVM_TE STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.71865173 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/30.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_max_throughput_chk.660401987 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 321870249 ps |
| CPU time | 17.52 seconds |
| Started | Aug 21 08:10:55 AM UTC 24 |
| Finished | Aug 21 08:11:14 AM UTC 24 |
| Peak memory | 228316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=660401987 -assert no postproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_thr oughput_chk.660401987 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/30.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all.2707244228 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 2072572604 ps |
| CPU time | 34.68 seconds |
| Started | Aug 21 08:10:55 AM UTC 24 |
| Finished | Aug 21 08:11:31 AM UTC 24 |
| Peak memory | 227400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10 000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim .tcl +ntb_random_seed=2707244228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 30.rom_ctrl_stress_all.2707244228 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/30.rom_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.1276141198 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 2372191675 ps |
| CPU time | 95.97 seconds |
| Started | Aug 21 08:11:01 AM UTC 24 |
| Finished | Aug 21 08:12:39 AM UTC 24 |
| Peak memory | 232936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_n s=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1276141198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_ 64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.1276141198 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/30.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_alert_test.3586270272 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 174490497 ps |
| CPU time | 9.91 seconds |
| Started | Aug 21 08:11:17 AM UTC 24 |
| Finished | Aug 21 08:11:28 AM UTC 24 |
| Peak memory | 227548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=358627027 2 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl _alert_test.3586270272 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/31.rom_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.3955704691 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 55501377466 ps |
| CPU time | 250.18 seconds |
| Started | Aug 21 08:11:10 AM UTC 24 |
| Finished | Aug 21 08:15:24 AM UTC 24 |
| Peak memory | 245956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3955704 691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 31.rom_ctrl_corrupt_sig_fatal_chk.3955704691 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/31.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_kmac_err_chk.2384085829 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 2749522799 ps |
| CPU time | 28.13 seconds |
| Started | Aug 21 08:11:11 AM UTC 24 |
| Finished | Aug 21 08:11:40 AM UTC 24 |
| Peak memory | 228692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2384085829 -assert nopostproc +UVM_ TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.2384085829 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/31.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_max_throughput_chk.3020866912 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 221168937 ps |
| CPU time | 15.79 seconds |
| Started | Aug 21 08:11:07 AM UTC 24 |
| Finished | Aug 21 08:11:24 AM UTC 24 |
| Peak memory | 228132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3020866912 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_th roughput_chk.3020866912 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/31.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_stress_all.2161724378 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 347715224 ps |
| CPU time | 33.82 seconds |
| Started | Aug 21 08:11:02 AM UTC 24 |
| Finished | Aug 21 08:11:37 AM UTC 24 |
| Peak memory | 228756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10 000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim .tcl +ntb_random_seed=2161724378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 31.rom_ctrl_stress_all.2161724378 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/31.rom_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_alert_test.3091686957 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 1904646656 ps |
| CPU time | 13.28 seconds |
| Started | Aug 21 08:11:29 AM UTC 24 |
| Finished | Aug 21 08:11:43 AM UTC 24 |
| Peak memory | 227816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=309168695 7 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl _alert_test.3091686957 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/32.rom_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.3933866430 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 56323932636 ps |
| CPU time | 150.86 seconds |
| Started | Aug 21 08:11:25 AM UTC 24 |
| Finished | Aug 21 08:13:58 AM UTC 24 |
| Peak memory | 228952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3933866 430 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 32.rom_ctrl_corrupt_sig_fatal_chk.3933866430 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/32.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_kmac_err_chk.1083885202 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 2147156854 ps |
| CPU time | 32.41 seconds |
| Started | Aug 21 08:11:25 AM UTC 24 |
| Finished | Aug 21 08:11:59 AM UTC 24 |
| Peak memory | 228884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1083885202 -assert nopostproc +UVM_ TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.1083885202 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/32.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_max_throughput_chk.2381156456 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 3982225126 ps |
| CPU time | 16.51 seconds |
| Started | Aug 21 08:11:24 AM UTC 24 |
| Finished | Aug 21 08:11:43 AM UTC 24 |
| Peak memory | 228820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2381156456 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_th roughput_chk.2381156456 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/32.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all.2778990841 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 1360662646 ps |
| CPU time | 23 seconds |
| Started | Aug 21 08:11:22 AM UTC 24 |
| Finished | Aug 21 08:11:46 AM UTC 24 |
| Peak memory | 228640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10 000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim .tcl +ntb_random_seed=2778990841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 32.rom_ctrl_stress_all.2778990841 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/32.rom_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.2830370255 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 7587455730 ps |
| CPU time | 245.73 seconds |
| Started | Aug 21 08:11:28 AM UTC 24 |
| Finished | Aug 21 08:15:37 AM UTC 24 |
| Peak memory | 246612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_n s=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2830370255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_ 64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all_with_rand_reset.2830370255 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/32.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_alert_test.3364659014 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 486968468 ps |
| CPU time | 14.41 seconds |
| Started | Aug 21 08:11:39 AM UTC 24 |
| Finished | Aug 21 08:11:54 AM UTC 24 |
| Peak memory | 227676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=336465901 4 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl _alert_test.3364659014 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/33.rom_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.4138680347 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 14549761455 ps |
| CPU time | 310.49 seconds |
| Started | Aug 21 08:11:31 AM UTC 24 |
| Finished | Aug 21 08:16:46 AM UTC 24 |
| Peak memory | 256444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4138680 347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 33.rom_ctrl_corrupt_sig_fatal_chk.4138680347 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/33.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_kmac_err_chk.2354109307 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 350829317 ps |
| CPU time | 22.22 seconds |
| Started | Aug 21 08:11:31 AM UTC 24 |
| Finished | Aug 21 08:11:55 AM UTC 24 |
| Peak memory | 228628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2354109307 -assert nopostproc +UVM_ TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.2354109307 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/33.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_max_throughput_chk.1894488072 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 365766644 ps |
| CPU time | 14.12 seconds |
| Started | Aug 21 08:11:30 AM UTC 24 |
| Finished | Aug 21 08:11:45 AM UTC 24 |
| Peak memory | 228124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1894488072 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_th roughput_chk.1894488072 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/33.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all.4078228687 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 3265438350 ps |
| CPU time | 21.36 seconds |
| Started | Aug 21 08:11:30 AM UTC 24 |
| Finished | Aug 21 08:11:53 AM UTC 24 |
| Peak memory | 225452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10 000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim .tcl +ntb_random_seed=4078228687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 33.rom_ctrl_stress_all.4078228687 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/33.rom_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.2858966467 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 2491934913 ps |
| CPU time | 149.4 seconds |
| Started | Aug 21 08:11:31 AM UTC 24 |
| Finished | Aug 21 08:14:03 AM UTC 24 |
| Peak memory | 232936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_n s=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2858966467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_ 64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all_with_rand_reset.2858966467 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/33.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_alert_test.4242200184 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 248866649 ps |
| CPU time | 8.99 seconds |
| Started | Aug 21 08:11:47 AM UTC 24 |
| Finished | Aug 21 08:11:57 AM UTC 24 |
| Peak memory | 227784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=424220018 4 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl _alert_test.4242200184 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/34.rom_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.285760910 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 17734785833 ps |
| CPU time | 296.5 seconds |
| Started | Aug 21 08:11:44 AM UTC 24 |
| Finished | Aug 21 08:16:44 AM UTC 24 |
| Peak memory | 228672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2857609 10 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 34.rom_ctrl_corrupt_sig_fatal_chk.285760910 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/34.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_kmac_err_chk.371952618 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 661248657 ps |
| CPU time | 21.14 seconds |
| Started | Aug 21 08:11:45 AM UTC 24 |
| Finished | Aug 21 08:12:07 AM UTC 24 |
| Peak memory | 228624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=371952618 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.371952618 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/34.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_max_throughput_chk.3887641493 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 1168678107 ps |
| CPU time | 11.45 seconds |
| Started | Aug 21 08:11:41 AM UTC 24 |
| Finished | Aug 21 08:11:53 AM UTC 24 |
| Peak memory | 228428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3887641493 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_th roughput_chk.3887641493 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/34.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all.625135553 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 1054516088 ps |
| CPU time | 29.63 seconds |
| Started | Aug 21 08:11:39 AM UTC 24 |
| Finished | Aug 21 08:12:09 AM UTC 24 |
| Peak memory | 228760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10 000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim .tcl +ntb_random_seed=625135553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 34.rom_ctrl_stress_all.625135553 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/34.rom_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.52602628 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 2193944897 ps |
| CPU time | 43.63 seconds |
| Started | Aug 21 08:11:46 AM UTC 24 |
| Finished | Aug 21 08:12:31 AM UTC 24 |
| Peak memory | 232928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_n s=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=52602628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64 kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.52602628 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/34.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_alert_test.2137283278 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 494183219 ps |
| CPU time | 12.72 seconds |
| Started | Aug 21 08:11:57 AM UTC 24 |
| Finished | Aug 21 08:12:11 AM UTC 24 |
| Peak memory | 227808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=213728327 8 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl _alert_test.2137283278 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/35.rom_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.2345723679 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 4768567062 ps |
| CPU time | 363.34 seconds |
| Started | Aug 21 08:11:54 AM UTC 24 |
| Finished | Aug 21 08:18:03 AM UTC 24 |
| Peak memory | 228356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2345723 679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 35.rom_ctrl_corrupt_sig_fatal_chk.2345723679 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/35.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_kmac_err_chk.3590059864 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 1979836999 ps |
| CPU time | 20.33 seconds |
| Started | Aug 21 08:11:55 AM UTC 24 |
| Finished | Aug 21 08:12:17 AM UTC 24 |
| Peak memory | 228692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3590059864 -assert nopostproc +UVM_ TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.3590059864 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/35.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_max_throughput_chk.4027757790 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 4503803912 ps |
| CPU time | 22.47 seconds |
| Started | Aug 21 08:11:53 AM UTC 24 |
| Finished | Aug 21 08:12:17 AM UTC 24 |
| Peak memory | 223408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4027757790 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_th roughput_chk.4027757790 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/35.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all.2344018867 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 1206952583 ps |
| CPU time | 21.73 seconds |
| Started | Aug 21 08:11:50 AM UTC 24 |
| Finished | Aug 21 08:12:13 AM UTC 24 |
| Peak memory | 228564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10 000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim .tcl +ntb_random_seed=2344018867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 35.rom_ctrl_stress_all.2344018867 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/35.rom_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.1439355224 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 9408665420 ps |
| CPU time | 160.61 seconds |
| Started | Aug 21 08:11:55 AM UTC 24 |
| Finished | Aug 21 08:14:39 AM UTC 24 |
| Peak memory | 235040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_n s=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1439355224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_ 64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all_with_rand_reset.1439355224 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/35.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_alert_test.474618856 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 617727050 ps |
| CPU time | 10.94 seconds |
| Started | Aug 21 08:12:11 AM UTC 24 |
| Finished | Aug 21 08:12:23 AM UTC 24 |
| Peak memory | 227492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=474618856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_ alert_test.474618856 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/36.rom_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.2921385996 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 17750177059 ps |
| CPU time | 326.29 seconds |
| Started | Aug 21 08:11:59 AM UTC 24 |
| Finished | Aug 21 08:17:30 AM UTC 24 |
| Peak memory | 259592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2921385 996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 36.rom_ctrl_corrupt_sig_fatal_chk.2921385996 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/36.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_kmac_err_chk.790729700 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 8222602310 ps |
| CPU time | 25.11 seconds |
| Started | Aug 21 08:12:08 AM UTC 24 |
| Finished | Aug 21 08:12:34 AM UTC 24 |
| Peak memory | 228476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=790729700 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.790729700 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/36.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_max_throughput_chk.2374970696 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 490867762 ps |
| CPU time | 15.14 seconds |
| Started | Aug 21 08:11:59 AM UTC 24 |
| Finished | Aug 21 08:12:16 AM UTC 24 |
| Peak memory | 228300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2374970696 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_th roughput_chk.2374970696 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/36.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all.1854982824 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 3220697174 ps |
| CPU time | 40.77 seconds |
| Started | Aug 21 08:11:59 AM UTC 24 |
| Finished | Aug 21 08:12:42 AM UTC 24 |
| Peak memory | 228700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10 000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim .tcl +ntb_random_seed=1854982824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 36.rom_ctrl_stress_all.1854982824 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/36.rom_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.3054497455 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 7703087752 ps |
| CPU time | 106.44 seconds |
| Started | Aug 21 08:12:10 AM UTC 24 |
| Finished | Aug 21 08:13:58 AM UTC 24 |
| Peak memory | 234984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_n s=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3054497455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_ 64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all_with_rand_reset.3054497455 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/36.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_alert_test.3581459739 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 261004575 ps |
| CPU time | 12.06 seconds |
| Started | Aug 21 08:12:14 AM UTC 24 |
| Finished | Aug 21 08:12:27 AM UTC 24 |
| Peak memory | 227676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=358145973 9 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl _alert_test.3581459739 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/37.rom_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.643948197 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 5138397461 ps |
| CPU time | 266.79 seconds |
| Started | Aug 21 08:12:12 AM UTC 24 |
| Finished | Aug 21 08:16:42 AM UTC 24 |
| Peak memory | 228372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=6439481 97 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 37.rom_ctrl_corrupt_sig_fatal_chk.643948197 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/37.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_kmac_err_chk.319036656 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 722469765 ps |
| CPU time | 28.98 seconds |
| Started | Aug 21 08:12:14 AM UTC 24 |
| Finished | Aug 21 08:12:44 AM UTC 24 |
| Peak memory | 228624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=319036656 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.319036656 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/37.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_max_throughput_chk.1612915343 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 622968086 ps |
| CPU time | 10.78 seconds |
| Started | Aug 21 08:12:12 AM UTC 24 |
| Finished | Aug 21 08:12:24 AM UTC 24 |
| Peak memory | 228376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1612915343 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_th roughput_chk.1612915343 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/37.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all.4060314955 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 545178298 ps |
| CPU time | 21.59 seconds |
| Started | Aug 21 08:12:11 AM UTC 24 |
| Finished | Aug 21 08:12:34 AM UTC 24 |
| Peak memory | 228644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10 000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim .tcl +ntb_random_seed=4060314955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 37.rom_ctrl_stress_all.4060314955 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/37.rom_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.862261529 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 3734889838 ps |
| CPU time | 204.16 seconds |
| Started | Aug 21 08:12:14 AM UTC 24 |
| Finished | Aug 21 08:15:41 AM UTC 24 |
| Peak memory | 245476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_n s=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=862261529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_6 4kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.862261529 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/37.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_alert_test.3884509634 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 377426949 ps |
| CPU time | 9.92 seconds |
| Started | Aug 21 08:12:22 AM UTC 24 |
| Finished | Aug 21 08:12:33 AM UTC 24 |
| Peak memory | 227484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=388450963 4 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl _alert_test.3884509634 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/38.rom_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.2057834522 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 5131249202 ps |
| CPU time | 244.83 seconds |
| Started | Aug 21 08:12:17 AM UTC 24 |
| Finished | Aug 21 08:16:26 AM UTC 24 |
| Peak memory | 244944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2057834 522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 38.rom_ctrl_corrupt_sig_fatal_chk.2057834522 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/38.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_kmac_err_chk.2831157 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 8237429450 ps |
| CPU time | 31.25 seconds |
| Started | Aug 21 08:12:20 AM UTC 24 |
| Finished | Aug 21 08:12:53 AM UTC 24 |
| Peak memory | 228756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2831157 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.2831157 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/38.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_max_throughput_chk.3118438964 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 265905733 ps |
| CPU time | 18.5 seconds |
| Started | Aug 21 08:12:17 AM UTC 24 |
| Finished | Aug 21 08:12:37 AM UTC 24 |
| Peak memory | 228444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3118438964 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_th roughput_chk.3118438964 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/38.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all.3383765123 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 479137571 ps |
| CPU time | 12.54 seconds |
| Started | Aug 21 08:12:16 AM UTC 24 |
| Finished | Aug 21 08:12:30 AM UTC 24 |
| Peak memory | 228156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10 000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim .tcl +ntb_random_seed=3383765123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 38.rom_ctrl_stress_all.3383765123 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/38.rom_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.3961847840 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 5300786335 ps |
| CPU time | 98.6 seconds |
| Started | Aug 21 08:12:21 AM UTC 24 |
| Finished | Aug 21 08:14:02 AM UTC 24 |
| Peak memory | 246360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_n s=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3961847840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_ 64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all_with_rand_reset.3961847840 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/38.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_alert_test.892808175 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 661037903 ps |
| CPU time | 11.48 seconds |
| Started | Aug 21 08:12:31 AM UTC 24 |
| Finished | Aug 21 08:12:44 AM UTC 24 |
| Peak memory | 227864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=892808175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_ alert_test.892808175 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/39.rom_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.3796532636 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 2227489789 ps |
| CPU time | 183.72 seconds |
| Started | Aug 21 08:12:25 AM UTC 24 |
| Finished | Aug 21 08:15:31 AM UTC 24 |
| Peak memory | 257420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3796532 636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 39.rom_ctrl_corrupt_sig_fatal_chk.3796532636 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/39.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_kmac_err_chk.715697357 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 1981025918 ps |
| CPU time | 25.62 seconds |
| Started | Aug 21 08:12:28 AM UTC 24 |
| Finished | Aug 21 08:12:55 AM UTC 24 |
| Peak memory | 228816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=715697357 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.715697357 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/39.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_max_throughput_chk.2511981170 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 698779883 ps |
| CPU time | 14.67 seconds |
| Started | Aug 21 08:12:24 AM UTC 24 |
| Finished | Aug 21 08:12:40 AM UTC 24 |
| Peak memory | 228652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2511981170 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_th roughput_chk.2511981170 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/39.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all.917101093 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 3787459806 ps |
| CPU time | 44.94 seconds |
| Started | Aug 21 08:12:23 AM UTC 24 |
| Finished | Aug 21 08:13:10 AM UTC 24 |
| Peak memory | 227584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10 000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim .tcl +ntb_random_seed=917101093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 39.rom_ctrl_stress_all.917101093 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/39.rom_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.2099736591 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 2000670948 ps |
| CPU time | 103.13 seconds |
| Started | Aug 21 08:12:30 AM UTC 24 |
| Finished | Aug 21 08:14:15 AM UTC 24 |
| Peak memory | 234920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_n s=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2099736591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_ 64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_stress_all_with_rand_reset.2099736591 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/39.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_alert_test.1137488396 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 249416015 ps |
| CPU time | 8.86 seconds |
| Started | Aug 21 08:08:23 AM UTC 24 |
| Finished | Aug 21 08:08:50 AM UTC 24 |
| Peak memory | 228008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=113748839 6 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_ alert_test.1137488396 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.4199031209 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 5666857651 ps |
| CPU time | 160.86 seconds |
| Started | Aug 21 08:08:23 AM UTC 24 |
| Finished | Aug 21 08:11:24 AM UTC 24 |
| Peak memory | 261584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4199031 209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 4.rom_ctrl_corrupt_sig_fatal_chk.4199031209 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_kmac_err_chk.954244569 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 534541068 ps |
| CPU time | 22.01 seconds |
| Started | Aug 21 08:08:23 AM UTC 24 |
| Finished | Aug 21 08:09:04 AM UTC 24 |
| Peak memory | 228624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=954244569 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.954244569 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_max_throughput_chk.2077409312 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 948013742 ps |
| CPU time | 13.09 seconds |
| Started | Aug 21 08:08:23 AM UTC 24 |
| Finished | Aug 21 08:08:55 AM UTC 24 |
| Peak memory | 228160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2077409312 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_thr oughput_chk.2077409312 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_sec_cm.1108321573 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 1684169067 ps |
| CPU time | 217.31 seconds |
| Started | Aug 21 08:08:23 AM UTC 24 |
| Finished | Aug 21 08:12:21 AM UTC 24 |
| Peak memory | 258516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1108321573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_s ec_cm.1108321573 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_sec_cm/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_smoke.3347601976 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 5198235371 ps |
| CPU time | 21.39 seconds |
| Started | Aug 21 08:08:23 AM UTC 24 |
| Finished | Aug 21 08:09:03 AM UTC 24 |
| Peak memory | 225444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3347601976 -assert nopostproc +UVM_ TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.3347601976 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all.92960165 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 1122686771 ps |
| CPU time | 14.57 seconds |
| Started | Aug 21 08:08:23 AM UTC 24 |
| Finished | Aug 21 08:08:56 AM UTC 24 |
| Peak memory | 225380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10 000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim .tcl +ntb_random_seed=92960165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 4.rom_ctrl_stress_all.92960165 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_alert_test.1693379539 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 689829727 ps |
| CPU time | 9.34 seconds |
| Started | Aug 21 08:12:38 AM UTC 24 |
| Finished | Aug 21 08:12:49 AM UTC 24 |
| Peak memory | 227484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=169337953 9 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl _alert_test.1693379539 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/40.rom_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.3752490829 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 2085588848 ps |
| CPU time | 183.76 seconds |
| Started | Aug 21 08:12:34 AM UTC 24 |
| Finished | Aug 21 08:15:41 AM UTC 24 |
| Peak memory | 257344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3752490 829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 40.rom_ctrl_corrupt_sig_fatal_chk.3752490829 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/40.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_kmac_err_chk.1723536311 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 1322873712 ps |
| CPU time | 24.27 seconds |
| Started | Aug 21 08:12:34 AM UTC 24 |
| Finished | Aug 21 08:13:00 AM UTC 24 |
| Peak memory | 228328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1723536311 -assert nopostproc +UVM_ TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.1723536311 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/40.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_max_throughput_chk.336680855 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 273746039 ps |
| CPU time | 10.88 seconds |
| Started | Aug 21 08:12:32 AM UTC 24 |
| Finished | Aug 21 08:12:44 AM UTC 24 |
| Peak memory | 228564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=336680855 -assert no postproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_thr oughput_chk.336680855 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/40.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all.569297059 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 844768211 ps |
| CPU time | 24.49 seconds |
| Started | Aug 21 08:12:31 AM UTC 24 |
| Finished | Aug 21 08:12:57 AM UTC 24 |
| Peak memory | 228560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10 000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim .tcl +ntb_random_seed=569297059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 40.rom_ctrl_stress_all.569297059 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/40.rom_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.2050167268 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 2574699395 ps |
| CPU time | 62.38 seconds |
| Started | Aug 21 08:12:35 AM UTC 24 |
| Finished | Aug 21 08:13:39 AM UTC 24 |
| Peak memory | 232936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_n s=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2050167268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_ 64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all_with_rand_reset.2050167268 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/40.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_alert_test.3652231889 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 689187560 ps |
| CPU time | 11.19 seconds |
| Started | Aug 21 08:12:45 AM UTC 24 |
| Finished | Aug 21 08:12:57 AM UTC 24 |
| Peak memory | 227852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=365223188 9 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl _alert_test.3652231889 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/41.rom_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.782704590 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 31387420388 ps |
| CPU time | 549.43 seconds |
| Started | Aug 21 08:12:42 AM UTC 24 |
| Finished | Aug 21 08:21:59 AM UTC 24 |
| Peak memory | 256752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=7827045 90 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 41.rom_ctrl_corrupt_sig_fatal_chk.782704590 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/41.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_kmac_err_chk.2100778671 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 8198696559 ps |
| CPU time | 36.09 seconds |
| Started | Aug 21 08:12:43 AM UTC 24 |
| Finished | Aug 21 08:13:21 AM UTC 24 |
| Peak memory | 228272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2100778671 -assert nopostproc +UVM_ TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.2100778671 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/41.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_max_throughput_chk.2758716418 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 1072249029 ps |
| CPU time | 17.7 seconds |
| Started | Aug 21 08:12:41 AM UTC 24 |
| Finished | Aug 21 08:13:00 AM UTC 24 |
| Peak memory | 228380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2758716418 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_th roughput_chk.2758716418 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/41.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all.1860286074 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 379186103 ps |
| CPU time | 21.34 seconds |
| Started | Aug 21 08:12:40 AM UTC 24 |
| Finished | Aug 21 08:13:03 AM UTC 24 |
| Peak memory | 228832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10 000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim .tcl +ntb_random_seed=1860286074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 41.rom_ctrl_stress_all.1860286074 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/41.rom_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.2564759844 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 4242628946 ps |
| CPU time | 59.12 seconds |
| Started | Aug 21 08:12:43 AM UTC 24 |
| Finished | Aug 21 08:13:44 AM UTC 24 |
| Peak memory | 234984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_n s=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2564759844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_ 64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all_with_rand_reset.2564759844 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/41.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_alert_test.507015195 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 260819756 ps |
| CPU time | 14.55 seconds |
| Started | Aug 21 08:12:55 AM UTC 24 |
| Finished | Aug 21 08:13:11 AM UTC 24 |
| Peak memory | 228000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=507015195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_ alert_test.507015195 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/42.rom_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.2738618754 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 9252055824 ps |
| CPU time | 286.21 seconds |
| Started | Aug 21 08:12:46 AM UTC 24 |
| Finished | Aug 21 08:17:36 AM UTC 24 |
| Peak memory | 258332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2738618 754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 42.rom_ctrl_corrupt_sig_fatal_chk.2738618754 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/42.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_kmac_err_chk.4036513203 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 665079561 ps |
| CPU time | 18.62 seconds |
| Started | Aug 21 08:12:50 AM UTC 24 |
| Finished | Aug 21 08:13:10 AM UTC 24 |
| Peak memory | 228816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4036513203 -assert nopostproc +UVM_ TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.4036513203 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/42.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_max_throughput_chk.3860657406 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 278492934 ps |
| CPU time | 16.33 seconds |
| Started | Aug 21 08:12:45 AM UTC 24 |
| Finished | Aug 21 08:13:02 AM UTC 24 |
| Peak memory | 228116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3860657406 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_th roughput_chk.3860657406 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/42.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all.1561801620 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 5455553509 ps |
| CPU time | 42.45 seconds |
| Started | Aug 21 08:12:45 AM UTC 24 |
| Finished | Aug 21 08:13:28 AM UTC 24 |
| Peak memory | 228772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10 000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim .tcl +ntb_random_seed=1561801620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 42.rom_ctrl_stress_all.1561801620 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/42.rom_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.1443447329 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 1335749035 ps |
| CPU time | 73.44 seconds |
| Started | Aug 21 08:12:54 AM UTC 24 |
| Finished | Aug 21 08:14:09 AM UTC 24 |
| Peak memory | 243304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_n s=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1443447329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_ 64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all_with_rand_reset.1443447329 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/42.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_alert_test.799282657 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 552497174 ps |
| CPU time | 11.65 seconds |
| Started | Aug 21 08:13:03 AM UTC 24 |
| Finished | Aug 21 08:13:16 AM UTC 24 |
| Peak memory | 227684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=799282657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_ alert_test.799282657 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/43.rom_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.2847524238 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 9317458062 ps |
| CPU time | 155.25 seconds |
| Started | Aug 21 08:12:58 AM UTC 24 |
| Finished | Aug 21 08:15:36 AM UTC 24 |
| Peak memory | 245888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2847524 238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 43.rom_ctrl_corrupt_sig_fatal_chk.2847524238 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/43.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_kmac_err_chk.2343860191 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 630033568 ps |
| CPU time | 24.27 seconds |
| Started | Aug 21 08:13:00 AM UTC 24 |
| Finished | Aug 21 08:13:26 AM UTC 24 |
| Peak memory | 228392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2343860191 -assert nopostproc +UVM_ TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.2343860191 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/43.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_max_throughput_chk.1648333507 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 183272958 ps |
| CPU time | 15.43 seconds |
| Started | Aug 21 08:12:57 AM UTC 24 |
| Finished | Aug 21 08:13:14 AM UTC 24 |
| Peak memory | 227984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1648333507 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_th roughput_chk.1648333507 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/43.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all.3463878069 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 1551015418 ps |
| CPU time | 58.53 seconds |
| Started | Aug 21 08:12:56 AM UTC 24 |
| Finished | Aug 21 08:13:56 AM UTC 24 |
| Peak memory | 228644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10 000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim .tcl +ntb_random_seed=3463878069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 43.rom_ctrl_stress_all.3463878069 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/43.rom_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.3601066694 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 2025271662 ps |
| CPU time | 113.31 seconds |
| Started | Aug 21 08:13:01 AM UTC 24 |
| Finished | Aug 21 08:14:57 AM UTC 24 |
| Peak memory | 233064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_n s=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3601066694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_ 64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all_with_rand_reset.3601066694 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/43.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_alert_test.3310814839 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 664275923 ps |
| CPU time | 11.46 seconds |
| Started | Aug 21 08:13:11 AM UTC 24 |
| Finished | Aug 21 08:13:23 AM UTC 24 |
| Peak memory | 227856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=331081483 9 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl _alert_test.3310814839 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/44.rom_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1097008615 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 42146846634 ps |
| CPU time | 221.38 seconds |
| Started | Aug 21 08:13:08 AM UTC 24 |
| Finished | Aug 21 08:16:53 AM UTC 24 |
| Peak memory | 228204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1097008 615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 44.rom_ctrl_corrupt_sig_fatal_chk.1097008615 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/44.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_kmac_err_chk.3387404470 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 353575121 ps |
| CPU time | 28.51 seconds |
| Started | Aug 21 08:13:10 AM UTC 24 |
| Finished | Aug 21 08:13:39 AM UTC 24 |
| Peak memory | 228628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3387404470 -assert nopostproc +UVM_ TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.3387404470 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/44.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_max_throughput_chk.3691637603 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 715998861 ps |
| CPU time | 15.21 seconds |
| Started | Aug 21 08:13:08 AM UTC 24 |
| Finished | Aug 21 08:13:25 AM UTC 24 |
| Peak memory | 227440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3691637603 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_th roughput_chk.3691637603 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/44.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all.3862345087 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 1142619874 ps |
| CPU time | 19.71 seconds |
| Started | Aug 21 08:13:03 AM UTC 24 |
| Finished | Aug 21 08:13:24 AM UTC 24 |
| Peak memory | 228496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10 000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim .tcl +ntb_random_seed=3862345087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 44.rom_ctrl_stress_all.3862345087 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/44.rom_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.2179579228 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 1063049624 ps |
| CPU time | 78.27 seconds |
| Started | Aug 21 08:13:11 AM UTC 24 |
| Finished | Aug 21 08:14:31 AM UTC 24 |
| Peak memory | 243112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_n s=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2179579228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_ 64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all_with_rand_reset.2179579228 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/44.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_alert_test.875449797 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 168009421 ps |
| CPU time | 8.33 seconds |
| Started | Aug 21 08:13:17 AM UTC 24 |
| Finished | Aug 21 08:13:26 AM UTC 24 |
| Peak memory | 227492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=875449797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_ alert_test.875449797 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/45.rom_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.3604352620 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 16946222684 ps |
| CPU time | 229.64 seconds |
| Started | Aug 21 08:13:15 AM UTC 24 |
| Finished | Aug 21 08:17:08 AM UTC 24 |
| Peak memory | 256224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3604352 620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 45.rom_ctrl_corrupt_sig_fatal_chk.3604352620 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/45.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_kmac_err_chk.2128919732 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 4008103030 ps |
| CPU time | 32.02 seconds |
| Started | Aug 21 08:13:16 AM UTC 24 |
| Finished | Aug 21 08:13:49 AM UTC 24 |
| Peak memory | 228392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2128919732 -assert nopostproc +UVM_ TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.2128919732 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/45.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_max_throughput_chk.476451821 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 187362619 ps |
| CPU time | 13.3 seconds |
| Started | Aug 21 08:13:12 AM UTC 24 |
| Finished | Aug 21 08:13:26 AM UTC 24 |
| Peak memory | 228132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=476451821 -assert no postproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_thr oughput_chk.476451821 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/45.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all.2353940626 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 266826830 ps |
| CPU time | 25.89 seconds |
| Started | Aug 21 08:13:12 AM UTC 24 |
| Finished | Aug 21 08:13:39 AM UTC 24 |
| Peak memory | 228500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10 000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim .tcl +ntb_random_seed=2353940626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 45.rom_ctrl_stress_all.2353940626 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/45.rom_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.2590762224 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 3549438786 ps |
| CPU time | 142.49 seconds |
| Started | Aug 21 08:13:16 AM UTC 24 |
| Finished | Aug 21 08:15:41 AM UTC 24 |
| Peak memory | 239400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_n s=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2590762224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_ 64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all_with_rand_reset.2590762224 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/45.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_alert_test.4247819213 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 857425958 ps |
| CPU time | 14.21 seconds |
| Started | Aug 21 08:13:26 AM UTC 24 |
| Finished | Aug 21 08:13:42 AM UTC 24 |
| Peak memory | 227480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=424781921 3 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl _alert_test.4247819213 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/46.rom_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.594521962 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 15446687467 ps |
| CPU time | 204.8 seconds |
| Started | Aug 21 08:13:24 AM UTC 24 |
| Finished | Aug 21 08:16:52 AM UTC 24 |
| Peak memory | 246184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=5945219 62 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 46.rom_ctrl_corrupt_sig_fatal_chk.594521962 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/46.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_kmac_err_chk.2487370337 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 1829932050 ps |
| CPU time | 33.76 seconds |
| Started | Aug 21 08:13:25 AM UTC 24 |
| Finished | Aug 21 08:14:01 AM UTC 24 |
| Peak memory | 228624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2487370337 -assert nopostproc +UVM_ TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.2487370337 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/46.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_max_throughput_chk.2589670835 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 644916891 ps |
| CPU time | 16.71 seconds |
| Started | Aug 21 08:13:22 AM UTC 24 |
| Finished | Aug 21 08:13:40 AM UTC 24 |
| Peak memory | 221488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2589670835 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_th roughput_chk.2589670835 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/46.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all.4216819584 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 1840965305 ps |
| CPU time | 23.94 seconds |
| Started | Aug 21 08:13:19 AM UTC 24 |
| Finished | Aug 21 08:13:45 AM UTC 24 |
| Peak memory | 228564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10 000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim .tcl +ntb_random_seed=4216819584 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 46.rom_ctrl_stress_all.4216819584 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/46.rom_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.1568777201 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 5301953087 ps |
| CPU time | 188.32 seconds |
| Started | Aug 21 08:13:25 AM UTC 24 |
| Finished | Aug 21 08:16:37 AM UTC 24 |
| Peak memory | 234984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_n s=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1568777201 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_ 64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all_with_rand_reset.1568777201 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/46.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_alert_test.1634867589 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 174483095 ps |
| CPU time | 11.08 seconds |
| Started | Aug 21 08:13:40 AM UTC 24 |
| Finished | Aug 21 08:13:52 AM UTC 24 |
| Peak memory | 227864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=163486758 9 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl _alert_test.1634867589 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/47.rom_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.2659858981 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 21908155486 ps |
| CPU time | 265.48 seconds |
| Started | Aug 21 08:13:30 AM UTC 24 |
| Finished | Aug 21 08:17:59 AM UTC 24 |
| Peak memory | 257452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2659858 981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 47.rom_ctrl_corrupt_sig_fatal_chk.2659858981 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/47.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_kmac_err_chk.932576891 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 2059057495 ps |
| CPU time | 26.24 seconds |
| Started | Aug 21 08:13:33 AM UTC 24 |
| Finished | Aug 21 08:14:00 AM UTC 24 |
| Peak memory | 228524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=932576891 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.932576891 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/47.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_max_throughput_chk.1004865568 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 263602457 ps |
| CPU time | 16.13 seconds |
| Started | Aug 21 08:13:27 AM UTC 24 |
| Finished | Aug 21 08:13:45 AM UTC 24 |
| Peak memory | 228116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1004865568 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_th roughput_chk.1004865568 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/47.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all.1202131200 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 5381624468 ps |
| CPU time | 20.22 seconds |
| Started | Aug 21 08:13:27 AM UTC 24 |
| Finished | Aug 21 08:13:49 AM UTC 24 |
| Peak memory | 228628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10 000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim .tcl +ntb_random_seed=1202131200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 47.rom_ctrl_stress_all.1202131200 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/47.rom_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.1257898969 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 3288302827 ps |
| CPU time | 211.73 seconds |
| Started | Aug 21 08:13:36 AM UTC 24 |
| Finished | Aug 21 08:17:11 AM UTC 24 |
| Peak memory | 239080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_n s=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1257898969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_ 64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.1257898969 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/47.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_alert_test.1455108497 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 998574216 ps |
| CPU time | 15.58 seconds |
| Started | Aug 21 08:13:45 AM UTC 24 |
| Finished | Aug 21 08:14:02 AM UTC 24 |
| Peak memory | 227676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=145510849 7 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl _alert_test.1455108497 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/48.rom_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3245215155 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 14955505144 ps |
| CPU time | 337.19 seconds |
| Started | Aug 21 08:13:41 AM UTC 24 |
| Finished | Aug 21 08:19:23 AM UTC 24 |
| Peak memory | 259224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3245215 155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 48.rom_ctrl_corrupt_sig_fatal_chk.3245215155 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/48.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_kmac_err_chk.78129990 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 2145649166 ps |
| CPU time | 21.97 seconds |
| Started | Aug 21 08:13:43 AM UTC 24 |
| Finished | Aug 21 08:14:06 AM UTC 24 |
| Peak memory | 228340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=78129990 -assert nopostproc +UVM_TE STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.78129990 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/48.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_max_throughput_chk.3350515805 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 919955183 ps |
| CPU time | 11.83 seconds |
| Started | Aug 21 08:13:40 AM UTC 24 |
| Finished | Aug 21 08:13:53 AM UTC 24 |
| Peak memory | 228388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3350515805 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_th roughput_chk.3350515805 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/48.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all.3442475513 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 1064667005 ps |
| CPU time | 25.33 seconds |
| Started | Aug 21 08:13:40 AM UTC 24 |
| Finished | Aug 21 08:14:06 AM UTC 24 |
| Peak memory | 228644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10 000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim .tcl +ntb_random_seed=3442475513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 48.rom_ctrl_stress_all.3442475513 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/48.rom_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.257320114 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 7928236607 ps |
| CPU time | 170.05 seconds |
| Started | Aug 21 08:13:45 AM UTC 24 |
| Finished | Aug 21 08:16:38 AM UTC 24 |
| Peak memory | 245220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_n s=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=257320114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_6 4kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all_with_rand_reset.257320114 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/48.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_alert_test.551561896 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 1029950778 ps |
| CPU time | 13.44 seconds |
| Started | Aug 21 08:13:50 AM UTC 24 |
| Finished | Aug 21 08:14:05 AM UTC 24 |
| Peak memory | 227628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=551561896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_ alert_test.551561896 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/49.rom_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.619447186 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 7786220634 ps |
| CPU time | 121.49 seconds |
| Started | Aug 21 08:13:47 AM UTC 24 |
| Finished | Aug 21 08:15:51 AM UTC 24 |
| Peak memory | 257616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=6194471 86 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 49.rom_ctrl_corrupt_sig_fatal_chk.619447186 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/49.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_kmac_err_chk.3756384635 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 663594273 ps |
| CPU time | 22.35 seconds |
| Started | Aug 21 08:13:47 AM UTC 24 |
| Finished | Aug 21 08:14:11 AM UTC 24 |
| Peak memory | 228360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3756384635 -assert nopostproc +UVM_ TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.3756384635 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/49.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_max_throughput_chk.3981234865 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 264082628 ps |
| CPU time | 11.8 seconds |
| Started | Aug 21 08:13:46 AM UTC 24 |
| Finished | Aug 21 08:13:59 AM UTC 24 |
| Peak memory | 228312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3981234865 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_th roughput_chk.3981234865 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/49.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all.2690464485 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 536794213 ps |
| CPU time | 28.52 seconds |
| Started | Aug 21 08:13:46 AM UTC 24 |
| Finished | Aug 21 08:14:16 AM UTC 24 |
| Peak memory | 227436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10 000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim .tcl +ntb_random_seed=2690464485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 49.rom_ctrl_stress_all.2690464485 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/49.rom_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.3720426936 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 12405609332 ps |
| CPU time | 178.1 seconds |
| Started | Aug 21 08:13:50 AM UTC 24 |
| Finished | Aug 21 08:16:52 AM UTC 24 |
| Peak memory | 246276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_n s=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3720426936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_ 64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all_with_rand_reset.3720426936 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/49.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_alert_test.1350214709 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 1028156341 ps |
| CPU time | 16.85 seconds |
| Started | Aug 21 08:08:23 AM UTC 24 |
| Finished | Aug 21 08:08:59 AM UTC 24 |
| Peak memory | 227492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=135021470 9 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_ alert_test.1350214709 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.2183273190 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 14222583685 ps |
| CPU time | 125.27 seconds |
| Started | Aug 21 08:08:23 AM UTC 24 |
| Finished | Aug 21 08:10:31 AM UTC 24 |
| Peak memory | 257336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2183273 190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 5.rom_ctrl_corrupt_sig_fatal_chk.2183273190 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_kmac_err_chk.3432353694 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 1144231258 ps |
| CPU time | 20.19 seconds |
| Started | Aug 21 08:08:23 AM UTC 24 |
| Finished | Aug 21 08:09:02 AM UTC 24 |
| Peak memory | 228816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3432353694 -assert nopostproc +UVM_ TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.3432353694 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_max_throughput_chk.1331978324 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 308136961 ps |
| CPU time | 9.37 seconds |
| Started | Aug 21 08:08:23 AM UTC 24 |
| Finished | Aug 21 08:08:34 AM UTC 24 |
| Peak memory | 227976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1331978324 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_thr oughput_chk.1331978324 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_smoke.2729678611 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 791742395 ps |
| CPU time | 11.54 seconds |
| Started | Aug 21 08:08:23 AM UTC 24 |
| Finished | Aug 21 08:08:53 AM UTC 24 |
| Peak memory | 225380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2729678611 -assert nopostproc +UVM_ TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.2729678611 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all.2167436398 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 1085698300 ps |
| CPU time | 33.24 seconds |
| Started | Aug 21 08:08:23 AM UTC 24 |
| Finished | Aug 21 08:09:08 AM UTC 24 |
| Peak memory | 228644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10 000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim .tcl +ntb_random_seed=2167436398 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 5.rom_ctrl_stress_all.2167436398 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.3892730387 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 41894355867 ps |
| CPU time | 195.18 seconds |
| Started | Aug 21 08:08:23 AM UTC 24 |
| Finished | Aug 21 08:11:59 AM UTC 24 |
| Peak memory | 241380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_n s=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3892730387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_ 64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all_with_rand_reset.3892730387 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_alert_test.2390499596 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 689229921 ps |
| CPU time | 7.44 seconds |
| Started | Aug 21 08:08:28 AM UTC 24 |
| Finished | Aug 21 08:08:37 AM UTC 24 |
| Peak memory | 227872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=239049959 6 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_ alert_test.2390499596 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3734403968 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 9437780018 ps |
| CPU time | 260.79 seconds |
| Started | Aug 21 08:08:23 AM UTC 24 |
| Finished | Aug 21 08:13:08 AM UTC 24 |
| Peak memory | 246156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3734403 968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 6.rom_ctrl_corrupt_sig_fatal_chk.3734403968 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_kmac_err_chk.3262582561 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 1974973837 ps |
| CPU time | 20.74 seconds |
| Started | Aug 21 08:08:23 AM UTC 24 |
| Finished | Aug 21 08:09:03 AM UTC 24 |
| Peak memory | 228624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3262582561 -assert nopostproc +UVM_ TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.3262582561 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_max_throughput_chk.690780140 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 363239355 ps |
| CPU time | 14.33 seconds |
| Started | Aug 21 08:08:23 AM UTC 24 |
| Finished | Aug 21 08:08:59 AM UTC 24 |
| Peak memory | 228028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=690780140 -assert no postproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_thro ughput_chk.690780140 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_smoke.3714195855 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 1067524537 ps |
| CPU time | 12.54 seconds |
| Started | Aug 21 08:08:23 AM UTC 24 |
| Finished | Aug 21 08:08:54 AM UTC 24 |
| Peak memory | 228640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3714195855 -assert nopostproc +UVM_ TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.3714195855 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.222207599 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 8816170532 ps |
| CPU time | 298.41 seconds |
| Started | Aug 21 08:08:23 AM UTC 24 |
| Finished | Aug 21 08:13:46 AM UTC 24 |
| Peak memory | 236228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_n s=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=222207599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_6 4kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all_with_rand_reset.222207599 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_alert_test.153183540 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 175023014 ps |
| CPU time | 7.29 seconds |
| Started | Aug 21 08:08:28 AM UTC 24 |
| Finished | Aug 21 08:08:37 AM UTC 24 |
| Peak memory | 227776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=153183540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_a lert_test.153183540 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.640052220 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 5249290679 ps |
| CPU time | 299.17 seconds |
| Started | Aug 21 08:08:28 AM UTC 24 |
| Finished | Aug 21 08:13:32 AM UTC 24 |
| Peak memory | 261624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=6400522 20 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 7.rom_ctrl_corrupt_sig_fatal_chk.640052220 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_kmac_err_chk.392207306 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 1979924909 ps |
| CPU time | 20.01 seconds |
| Started | Aug 21 08:08:28 AM UTC 24 |
| Finished | Aug 21 08:08:49 AM UTC 24 |
| Peak memory | 228632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=392207306 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.392207306 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_max_throughput_chk.4220067633 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 267413999 ps |
| CPU time | 10.51 seconds |
| Started | Aug 21 08:08:28 AM UTC 24 |
| Finished | Aug 21 08:08:40 AM UTC 24 |
| Peak memory | 226656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4220067633 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_thr oughput_chk.4220067633 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_smoke.922980922 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 1016885535 ps |
| CPU time | 10.61 seconds |
| Started | Aug 21 08:08:28 AM UTC 24 |
| Finished | Aug 21 08:08:41 AM UTC 24 |
| Peak memory | 225476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=922980922 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s cratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.922980922 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.163729034 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 4079630286 ps |
| CPU time | 155.28 seconds |
| Started | Aug 21 08:08:28 AM UTC 24 |
| Finished | Aug 21 08:11:06 AM UTC 24 |
| Peak memory | 245216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_n s=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=163729034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_6 4kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all_with_rand_reset.163729034 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_alert_test.1687439393 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 256599670 ps |
| CPU time | 10.24 seconds |
| Started | Aug 21 08:08:30 AM UTC 24 |
| Finished | Aug 21 08:08:52 AM UTC 24 |
| Peak memory | 227844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=168743939 3 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_ alert_test.1687439393 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.344493237 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 3331166851 ps |
| CPU time | 261.77 seconds |
| Started | Aug 21 08:08:30 AM UTC 24 |
| Finished | Aug 21 08:13:09 AM UTC 24 |
| Peak memory | 245256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3444932 37 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 8.rom_ctrl_corrupt_sig_fatal_chk.344493237 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_kmac_err_chk.667263562 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 619547176 ps |
| CPU time | 31.61 seconds |
| Started | Aug 21 08:08:30 AM UTC 24 |
| Finished | Aug 21 08:09:16 AM UTC 24 |
| Peak memory | 228820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=667263562 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.667263562 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_max_throughput_chk.186696241 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 629441268 ps |
| CPU time | 15.37 seconds |
| Started | Aug 21 08:08:30 AM UTC 24 |
| Finished | Aug 21 08:09:00 AM UTC 24 |
| Peak memory | 228492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=186696241 -assert no postproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_thro ughput_chk.186696241 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_smoke.1692753066 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 177810507 ps |
| CPU time | 9.88 seconds |
| Started | Aug 21 08:08:28 AM UTC 24 |
| Finished | Aug 21 08:08:39 AM UTC 24 |
| Peak memory | 225392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1692753066 -assert nopostproc +UVM_ TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.1692753066 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_alert_test.1722782575 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 174621018 ps |
| CPU time | 7.38 seconds |
| Started | Aug 21 08:08:40 AM UTC 24 |
| Finished | Aug 21 08:08:49 AM UTC 24 |
| Peak memory | 227492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=172278257 5 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_ alert_test.1722782575 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.126447152 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 11186841187 ps |
| CPU time | 168.88 seconds |
| Started | Aug 21 08:08:38 AM UTC 24 |
| Finished | Aug 21 08:11:31 AM UTC 24 |
| Peak memory | 228740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1264471 52 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 9.rom_ctrl_corrupt_sig_fatal_chk.126447152 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_kmac_err_chk.2081002341 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 994079291 ps |
| CPU time | 24.52 seconds |
| Started | Aug 21 08:08:38 AM UTC 24 |
| Finished | Aug 21 08:09:05 AM UTC 24 |
| Peak memory | 228624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2081002341 -assert nopostproc +UVM_ TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.2081002341 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_max_throughput_chk.48352180 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 1080303276 ps |
| CPU time | 14.84 seconds |
| Started | Aug 21 08:08:36 AM UTC 24 |
| Finished | Aug 21 08:08:55 AM UTC 24 |
| Peak memory | 228564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=48352180 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throu ghput_chk.48352180 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_smoke.4292133929 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 1164488230 ps |
| CPU time | 11.03 seconds |
| Started | Aug 21 08:08:31 AM UTC 24 |
| Finished | Aug 21 08:08:51 AM UTC 24 |
| Peak memory | 228532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4292133929 -assert nopostproc +UVM_ TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.4292133929 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all.2721593193 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 4816574680 ps |
| CPU time | 16.52 seconds |
| Started | Aug 21 08:08:31 AM UTC 24 |
| Finished | Aug 21 08:08:56 AM UTC 24 |
| Peak memory | 228628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10 000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim .tcl +ntb_random_seed=2721593193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 9.rom_ctrl_stress_all.2721593193 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.3967453544 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 7607802718 ps |
| CPU time | 166.26 seconds |
| Started | Aug 21 08:08:38 AM UTC 24 |
| Finished | Aug 21 08:11:28 AM UTC 24 |
| Peak memory | 246556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_n s=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3967453544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_ 64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all_with_rand_reset.3967453544 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_stress_all_with_rand_reset/latest |
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