Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

554781

1

T1

19

T4

99

T6

42

full_word

341976

1

T1

3

T4

11

T6

6

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	896497	1			T1	22		T4	110		T6	48
auto[TlIntgErrCmd]	73	1			T75	1		T76	2		T77	6
auto[TlIntgErrData]	99	1			T75	8		T76	3		T77	1
auto[TlIntgErrBoth]	88	1			T75	1		T76	5		T77	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

161213

1

T1

22

T4

110

T6

48

auto[1]

735544

1

T13

2956

T14

3589

T15

9720

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrCmd]]	[full_word]	[auto[1]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	78256	1			T1	19		T4	99		T6	42
auto[TlIntgErrNone]	partial	auto[1]	476282	1			T13	1997		T14	2348		T15	6255
auto[TlIntgErrNone]	full_word	auto[0]	82840	1			T1	3		T4	11		T6	6
auto[TlIntgErrNone]	full_word	auto[1]	259119	1			T13	959		T14	1241		T15	3465
auto[TlIntgErrCmd]	partial	auto[0]	26	1			T76	1		T77	2		T130	1
auto[TlIntgErrCmd]	partial	auto[1]	43	1			T75	1		T76	1		T77	4
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T131	1		T132	1		T133	1
auto[TlIntgErrData]	partial	auto[0]	47	1			T75	5		T76	2		T77	1
auto[TlIntgErrData]	partial	auto[1]	44	1			T75	3		T76	1		T130	1
auto[TlIntgErrData]	full_word	auto[0]	3	1			T134	1		T132	1		T135	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T131	1		T136	1		T137	1
auto[TlIntgErrBoth]	partial	auto[0]	34	1			T76	4		T77	1		T130	1
auto[TlIntgErrBoth]	partial	auto[1]	49	1			T75	1		T76	1		T77	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T130	1		T138	1		T139	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T77	1		T136	1		-	-