Module Definition
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Module Instance : tb.dut.gen_rom_scramble_enabled.u_rom.u_rom

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.44 83.33 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
87.50 75.00 100.00 gen_rom_scramble_enabled.u_rom


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_rom 88.89 66.67 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : prim_rom_adv
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS4033100.00

39 always_ff @(posedge clk_i or negedge rst_ni) begin 40 1/1 if (!rst_ni) begin Tests: T1 T2 T3  41 1/1 rvalid_o <= 1'b0; Tests: T1 T2 T3  42 end else begin 43 1/1 rvalid_o <= req_i; Tests: T1 T2 T3 

Branch Coverage for Module : prim_rom_adv
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 40 2 2 100.00


40 if (!rst_ni) begin -1- 41 rvalid_o <= 1'b0; ==> 42 end else begin 43 rvalid_o <= req_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : prim_rom_adv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
noXOnCsI 43652481 43652481 0 0


noXOnCsI
NameAttemptsReal SuccessesFailuresIncomplete
Total 43652481 43652481 0 0
T1 100239 100239 0 0
T2 16617 16617 0 0
T3 16569 16569 0 0
T4 53377 53377 0 0
T5 24762 24762 0 0
T6 17852 17852 0 0
T7 17644 17644 0 0
T8 17607 17607 0 0
T9 16802 16802 0 0
T10 25603 25603 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%