Line Coverage for Module :
prim_rom_adv
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 40 | 3 | 3 | 100.00 |
39 always_ff @(posedge clk_i or negedge rst_ni) begin
40 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
41 1/1 rvalid_o <= 1'b0;
Tests: T1 T2 T3
42 end else begin
43 1/1 rvalid_o <= req_i;
Tests: T1 T2 T3
Branch Coverage for Module :
prim_rom_adv
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
40 |
2 |
2 |
100.00 |
40 if (!rst_ni) begin
-1-
41 rvalid_o <= 1'b0;
==>
42 end else begin
43 rvalid_o <= req_i;
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_rom_adv
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
noXOnCsI |
43652481 |
43652481 |
0 |
0 |
noXOnCsI
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
43652481 |
43652481 |
0 |
0 |
T1 |
100239 |
100239 |
0 |
0 |
T2 |
16617 |
16617 |
0 |
0 |
T3 |
16569 |
16569 |
0 |
0 |
T4 |
53377 |
53377 |
0 |
0 |
T5 |
24762 |
24762 |
0 |
0 |
T6 |
17852 |
17852 |
0 |
0 |
T7 |
17644 |
17644 |
0 |
0 |
T8 |
17607 |
17607 |
0 |
0 |
T9 |
16802 |
16802 |
0 |
0 |
T10 |
25603 |
25603 |
0 |
0 |