Unified Coverage Report :: Module :: rom_ctrl_regs_csr_assert_fpv

Module : rom_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_rom_ctrl_csr_assert_0/rom_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rom_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rom_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.99	100.00	98.28	97.26		100.00	79.41	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rom_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	49694236	415617	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49694236	415617	0	0
T13	101309	1994	0	0
T14	76492	1570	0	0
T15	0	6658	0	0
T18	0	4661	0	0
T36	54448	0	0	0
T52	49466	0	0	0
T53	49771	0	0	0
T64	0	3224	0	0
T65	0	7383	0	0
T66	0	14589	0	0
T67	0	14959	0	0
T68	0	9857	0	0
T69	0	3973	0	0
T70	26043	0	0	0
T71	25811	0	0	0
T72	20149	0	0	0
T73	17829	0	0	0
T74	36546	0	0	0