Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

550022

1

T2

39

T3

99

T6

211

full_word

344232

1

T2

4

T3

3

T6

21

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	893954	1			T2	43		T3	102		T6	232
auto[TlIntgErrCmd]	73	1			T68	2		T69	1		T70	3
auto[TlIntgErrData]	112	1			T68	2		T69	5		T70	3
auto[TlIntgErrBoth]	115	1			T68	6		T69	4		T70	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

160847

1

T2

43

T3

102

T6

232

auto[1]

733407

1

T11

1604

T16

371

T17

9990

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	78087	1			T2	39		T3	99		T6	211
auto[TlIntgErrNone]	partial	auto[1]	471657	1			T11	872		T16	286		T17	6298
auto[TlIntgErrNone]	full_word	auto[0]	82618	1			T2	4		T3	3		T6	21
auto[TlIntgErrNone]	full_word	auto[1]	261592	1			T11	732		T16	85		T17	3692
auto[TlIntgErrCmd]	partial	auto[0]	26	1			T69	1		T70	1		T126	1
auto[TlIntgErrCmd]	partial	auto[1]	41	1			T68	2		T70	2		T126	1
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T127	4		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T132	1		T133	1		-	-
auto[TlIntgErrData]	partial	auto[0]	55	1			T68	2		T69	2		T70	2
auto[TlIntgErrData]	partial	auto[1]	48	1			T69	3		T70	1		T126	2
auto[TlIntgErrData]	full_word	auto[0]	4	1			T124	1		T127	1		T134	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T129	1		T135	1		T136	1
auto[TlIntgErrBoth]	partial	auto[0]	50	1			T68	3		T70	2		T126	4
auto[TlIntgErrBoth]	partial	auto[1]	58	1			T68	3		T69	4		T70	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T123	1		T125	1		T137	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T126	1		T131	1		T125	1