Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

526043

1

T1

36

T2

160

T3

114

full_word

330511

1

T1

3

T2

22

T3

11

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	856254	1			T1	39		T2	182		T3	125
auto[TlIntgErrCmd]	98	1			T58	3		T59	2		T60	5
auto[TlIntgErrData]	100	1			T58	4		T59	2		T100	3
auto[TlIntgErrBoth]	102	1			T58	3		T59	6		T60	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

156715

1

T1

39

T2

182

T3

125

auto[1]

699839

1

T8

2963

T11

11230

T12

9052

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	76515	1			T1	36		T2	160		T3	114
auto[TlIntgErrNone]	partial	auto[1]	449254	1			T8	1553		T11	6906		T12	5682
auto[TlIntgErrNone]	full_word	auto[0]	80057	1			T1	3		T2	22		T3	11
auto[TlIntgErrNone]	full_word	auto[1]	250428	1			T8	1410		T11	4324		T12	3370
auto[TlIntgErrCmd]	partial	auto[0]	38	1			T58	2		T59	1		T60	5
auto[TlIntgErrCmd]	partial	auto[1]	48	1			T58	1		T59	1		T100	4
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T101	1		T108	2		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	9	1			T110	1		T111	1		T112	2
auto[TlIntgErrData]	partial	auto[0]	40	1			T58	3		T100	2		T101	1
auto[TlIntgErrData]	partial	auto[1]	55	1			T58	1		T59	2		T100	1
auto[TlIntgErrData]	full_word	auto[0]	4	1			T103	1		T105	1		T113	2
auto[TlIntgErrData]	full_word	auto[1]	1	1			T107	1		-	-		-	-
auto[TlIntgErrBoth]	partial	auto[0]	54	1			T58	2		T59	3		T60	4
auto[TlIntgErrBoth]	partial	auto[1]	39	1			T58	1		T59	3		T60	1
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T114	1		T111	1		T115	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T100	1		T102	1		T116	1