Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.62 96.89 92.70 97.68 100.00 98.97 98.05 99.06


Total tests in report: 457
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
63.17 63.17 92.58 92.58 71.21 71.21 41.15 41.15 40.00 40.00 90.34 90.34 93.55 93.55 13.35 13.35 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_smoke.18884853
75.45 12.28 92.94 0.36 77.67 6.46 52.42 11.27 40.00 0.00 92.07 1.72 95.05 1.50 77.99 64.64 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.2606358269
81.23 5.78 93.54 0.60 79.21 1.54 65.82 13.39 60.00 20.00 95.17 3.10 95.50 0.45 79.39 1.41 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_kmac_err_chk.1131754839
85.55 4.32 93.54 0.00 81.60 2.39 66.02 0.20 86.67 26.67 95.52 0.34 95.65 0.15 79.86 0.47 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3864291860
89.53 3.98 93.54 0.00 86.66 5.06 85.76 19.74 86.67 0.00 95.52 0.00 95.65 0.00 82.90 3.04 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all.3739899769
91.09 1.56 93.54 0.00 87.64 0.98 88.71 2.95 93.33 6.67 95.86 0.34 95.65 0.00 82.90 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_kmac_err_chk.3477722803
92.36 1.27 96.53 2.99 89.89 2.25 89.38 0.67 93.33 0.00 96.90 1.03 95.95 0.30 84.54 1.64 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_alert_test.2092896390
93.51 1.15 96.77 0.24 90.59 0.70 89.38 0.00 93.33 0.00 97.93 1.03 95.95 0.00 90.63 6.09 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.15305614
94.65 1.14 96.89 0.12 90.73 0.14 89.38 0.00 100.00 6.67 98.28 0.34 95.95 0.00 91.33 0.70 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.4262629888
95.68 1.03 96.89 0.00 90.73 0.00 94.48 5.10 100.00 0.00 98.28 0.00 95.95 0.00 93.44 2.11 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all.3294614509
96.10 0.42 96.89 0.00 90.73 0.00 94.85 0.37 100.00 0.00 98.28 0.00 95.95 0.00 96.02 2.58 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.1574535606
96.34 0.24 96.89 0.00 90.87 0.14 96.23 1.37 100.00 0.00 98.28 0.00 96.10 0.15 96.02 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all.4227723817
96.56 0.22 96.89 0.00 91.57 0.70 96.33 0.10 100.00 0.00 98.28 0.00 96.40 0.30 96.49 0.47 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_sec_cm.90133890
96.71 0.15 96.89 0.00 91.57 0.00 96.33 0.00 100.00 0.00 98.28 0.00 97.45 1.05 96.49 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3186755137
96.82 0.11 96.89 0.00 91.99 0.42 96.33 0.00 100.00 0.00 98.62 0.34 97.45 0.00 96.49 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.1641079404
96.93 0.11 96.89 0.00 91.99 0.00 97.08 0.75 100.00 0.00 98.62 0.00 97.45 0.00 96.49 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all.1035250306
97.03 0.10 96.89 0.00 91.99 0.00 97.08 0.00 100.00 0.00 98.62 0.00 97.45 0.00 97.19 0.70 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.295756202
97.13 0.10 96.89 0.00 91.99 0.00 97.38 0.30 100.00 0.00 98.62 0.00 97.60 0.15 97.42 0.23 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_max_throughput_chk.2363018934
97.20 0.07 96.89 0.00 92.13 0.14 97.38 0.00 100.00 0.00 98.97 0.34 97.60 0.00 97.42 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_kmac_err_chk.2866567725
97.27 0.07 96.89 0.00 92.13 0.00 97.38 0.00 100.00 0.00 98.97 0.00 97.60 0.00 97.89 0.47 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.27136244
97.33 0.07 96.89 0.00 92.13 0.00 97.38 0.00 100.00 0.00 98.97 0.00 97.60 0.00 98.36 0.47 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.683675642
97.40 0.07 96.89 0.00 92.13 0.00 97.38 0.00 100.00 0.00 98.97 0.00 97.60 0.00 98.83 0.47 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.748275782
97.46 0.06 96.89 0.00 92.28 0.14 97.38 0.00 100.00 0.00 98.97 0.00 97.90 0.30 98.83 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3848400199
97.52 0.05 96.89 0.00 92.42 0.14 97.38 0.00 100.00 0.00 98.97 0.00 97.90 0.00 99.06 0.23 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.2688434630
97.56 0.04 96.89 0.00 92.70 0.28 97.38 0.00 100.00 0.00 98.97 0.00 97.90 0.00 99.06 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.2971763012
97.58 0.03 96.89 0.00 92.70 0.00 97.58 0.20 100.00 0.00 98.97 0.00 97.90 0.00 99.06 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all.4129074249
97.61 0.02 96.89 0.00 92.70 0.00 97.58 0.00 100.00 0.00 98.97 0.00 98.05 0.15 99.06 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_max_throughput_chk.1422389740
97.62 0.01 96.89 0.00 92.70 0.00 97.68 0.10 100.00 0.00 98.97 0.00 98.05 0.00 99.06 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all.2126424900

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1470383428
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2376889811
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1396604550
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1791792206
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3527634523
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1740521547
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_walk.272054938
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3317542264
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1666071678
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1516498050
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2345059253
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.178086243
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2139537593
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_rw.739584867
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3225473790
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3708163803
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.828415276
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3504259879
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2117621675
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.902878378
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2335431044
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3924658186
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3575397093
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.251413560
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3474199221
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3409561051
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.992327334
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1146035147
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.933738894
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3632649529
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3524201263
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2535898766
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3912901739
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2665685026
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1155513119
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2373064855
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2129307116
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3980980763
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3540597687
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.4081904334
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.4234126131
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3897656023
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.421347029
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2227794416
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3490303233
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1704854587
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.4074361993
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3910548481
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2325499180
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_rw.938843351
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2608243514
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.4039822368
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1426054748
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1903303050
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1168649405
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1918876882
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3189052908
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3519673445
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_errors.669307908
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2322692655
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3419829490
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1095538484
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1747172064
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.249312338
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1301351236
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1236028230
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.4249272479
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_rw.755958584
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1875605817
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1356099508
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3526533696
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2559506942
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2366178838
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1872713067
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3073040282
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3788519462
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1422085375
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.558771606
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Total test records in report: 457
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_alert_test.2092896390 Sep 01 07:04:14 AM UTC 24 Sep 01 07:04:25 AM UTC 24 1904224606 ps
T2 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_alert_test.4105478108 Sep 01 07:04:14 AM UTC 24 Sep 01 07:04:26 AM UTC 24 260609067 ps
T3 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_max_throughput_chk.2884032425 Sep 01 07:04:14 AM UTC 24 Sep 01 07:04:26 AM UTC 24 186611299 ps
T4 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_smoke.18884853 Sep 01 07:04:14 AM UTC 24 Sep 01 07:04:26 AM UTC 24 184649595 ps
T5 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_max_throughput_chk.3122762343 Sep 01 07:04:12 AM UTC 24 Sep 01 07:04:28 AM UTC 24 1066365209 ps
T6 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_smoke.3309884019 Sep 01 07:04:17 AM UTC 24 Sep 01 07:04:32 AM UTC 24 185105249 ps
T7 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_alert_test.3664284242 Sep 01 07:04:21 AM UTC 24 Sep 01 07:04:32 AM UTC 24 260601102 ps
T8 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_max_throughput_chk.4134320568 Sep 01 07:04:20 AM UTC 24 Sep 01 07:04:33 AM UTC 24 183010344 ps
T9 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_kmac_err_chk.1131754839 Sep 01 07:04:14 AM UTC 24 Sep 01 07:04:34 AM UTC 24 346232574 ps
T10 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_max_throughput_chk.2363018934 Sep 01 07:04:14 AM UTC 24 Sep 01 07:04:36 AM UTC 24 525702540 ps
T17 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_alert_test.1103086949 Sep 01 07:04:15 AM UTC 24 Sep 01 07:04:37 AM UTC 24 170797275 ps
T18 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_alert_test.2755957334 Sep 01 07:04:16 AM UTC 24 Sep 01 07:04:38 AM UTC 24 993448411 ps
T13 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_smoke.3022416946 Sep 01 07:04:12 AM UTC 24 Sep 01 07:04:38 AM UTC 24 1705533024 ps
T49 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_alert_test.3617705947 Sep 01 07:04:25 AM UTC 24 Sep 01 07:04:38 AM UTC 24 250007811 ps
T15 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_smoke.832184964 Sep 01 07:04:14 AM UTC 24 Sep 01 07:04:38 AM UTC 24 359818900 ps
T14 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_smoke.1305409215 Sep 01 07:04:23 AM UTC 24 Sep 01 07:04:39 AM UTC 24 187138511 ps
T16 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_max_throughput_chk.3726566552 Sep 01 07:04:24 AM UTC 24 Sep 01 07:04:39 AM UTC 24 3477494532 ps
T11 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all.4129074249 Sep 01 07:04:12 AM UTC 24 Sep 01 07:04:39 AM UTC 24 535568440 ps
T84 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_smoke.2967245532 Sep 01 07:04:15 AM UTC 24 Sep 01 07:04:42 AM UTC 24 3253485795 ps
T133 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_max_throughput_chk.946532807 Sep 01 07:04:15 AM UTC 24 Sep 01 07:04:42 AM UTC 24 259752588 ps
T12 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_kmac_err_chk.2056218227 Sep 01 07:04:12 AM UTC 24 Sep 01 07:04:44 AM UTC 24 1225332423 ps
T32 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all.2739544433 Sep 01 07:04:14 AM UTC 24 Sep 01 07:04:44 AM UTC 24 1566297780 ps
T59 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_smoke.1890865346 Sep 01 07:04:26 AM UTC 24 Sep 01 07:04:45 AM UTC 24 738045044 ps
T134 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_max_throughput_chk.3579873423 Sep 01 07:04:29 AM UTC 24 Sep 01 07:04:45 AM UTC 24 1013207911 ps
T88 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_alert_test.4049257125 Sep 01 07:04:28 AM UTC 24 Sep 01 07:04:45 AM UTC 24 497835917 ps
T31 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_kmac_err_chk.3477722803 Sep 01 07:04:15 AM UTC 24 Sep 01 07:04:46 AM UTC 24 1341261355 ps
T55 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_kmac_err_chk.3687697090 Sep 01 07:04:20 AM UTC 24 Sep 01 07:04:46 AM UTC 24 2061668975 ps
T101 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_smoke.183421860 Sep 01 07:04:29 AM UTC 24 Sep 01 07:04:48 AM UTC 24 1066908124 ps
T89 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_alert_test.2395082565 Sep 01 07:04:35 AM UTC 24 Sep 01 07:04:49 AM UTC 24 331744770 ps
T33 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all.3739899769 Sep 01 07:04:14 AM UTC 24 Sep 01 07:04:50 AM UTC 24 3255496068 ps
T35 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_kmac_err_chk.2081380587 Sep 01 07:04:24 AM UTC 24 Sep 01 07:04:50 AM UTC 24 4735968479 ps
T102 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_smoke.1136607224 Sep 01 07:04:37 AM UTC 24 Sep 01 07:04:51 AM UTC 24 178592873 ps
T152 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_max_throughput_chk.1967600610 Sep 01 07:04:27 AM UTC 24 Sep 01 07:04:52 AM UTC 24 3560159963 ps
T36 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_kmac_err_chk.1226120282 Sep 01 07:04:14 AM UTC 24 Sep 01 07:04:53 AM UTC 24 522552826 ps
T90 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_alert_test.3484680637 Sep 01 07:04:41 AM UTC 24 Sep 01 07:04:53 AM UTC 24 1831370454 ps
T37 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_kmac_err_chk.1665114150 Sep 01 07:04:27 AM UTC 24 Sep 01 07:04:56 AM UTC 24 1976184546 ps
T91 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_alert_test.2157254581 Sep 01 07:04:45 AM UTC 24 Sep 01 07:04:57 AM UTC 24 663476183 ps
T135 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_max_throughput_chk.443325066 Sep 01 07:04:39 AM UTC 24 Sep 01 07:04:58 AM UTC 24 273184361 ps
T34 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all.4227723817 Sep 01 07:04:24 AM UTC 24 Sep 01 07:04:58 AM UTC 24 1035771156 ps
T158 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_smoke.2261650123 Sep 01 07:04:41 AM UTC 24 Sep 01 07:04:59 AM UTC 24 210865183 ps
T161 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_alert_test.3994779567 Sep 01 07:04:48 AM UTC 24 Sep 01 07:04:59 AM UTC 24 250044575 ps
T157 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all.4027030588 Sep 01 07:04:27 AM UTC 24 Sep 01 07:05:00 AM UTC 24 1019039706 ps
T156 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_max_throughput_chk.3619136186 Sep 01 07:04:43 AM UTC 24 Sep 01 07:05:01 AM UTC 24 1223319315 ps
T136 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_max_throughput_chk.3950428958 Sep 01 07:04:47 AM UTC 24 Sep 01 07:05:01 AM UTC 24 184757397 ps
T56 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_kmac_err_chk.3686384602 Sep 01 07:04:33 AM UTC 24 Sep 01 07:05:02 AM UTC 24 1983528968 ps
T103 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all.2126424900 Sep 01 07:04:18 AM UTC 24 Sep 01 07:05:04 AM UTC 24 817156348 ps
T164 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_alert_test.2605898767 Sep 01 07:04:52 AM UTC 24 Sep 01 07:05:06 AM UTC 24 1177104419 ps
T57 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_kmac_err_chk.4224368897 Sep 01 07:04:45 AM UTC 24 Sep 01 07:05:07 AM UTC 24 1323718805 ps
T159 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_max_throughput_chk.555394924 Sep 01 07:04:50 AM UTC 24 Sep 01 07:05:08 AM UTC 24 511695010 ps
T58 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_kmac_err_chk.3607746921 Sep 01 07:04:40 AM UTC 24 Sep 01 07:05:11 AM UTC 24 1500053613 ps
T137 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_max_throughput_chk.4155194156 Sep 01 07:04:55 AM UTC 24 Sep 01 07:05:11 AM UTC 24 690054978 ps
T19 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.1574535606 Sep 01 07:04:14 AM UTC 24 Sep 01 07:05:11 AM UTC 24 3515315746 ps
T72 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all.3294614509 Sep 01 07:04:29 AM UTC 24 Sep 01 07:05:12 AM UTC 24 4395370317 ps
T73 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_max_throughput_chk.139932065 Sep 01 07:04:59 AM UTC 24 Sep 01 07:05:12 AM UTC 24 358175582 ps
T74 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_alert_test.2917445394 Sep 01 07:04:58 AM UTC 24 Sep 01 07:05:13 AM UTC 24 262767001 ps
T75 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all.1035250306 Sep 01 07:04:15 AM UTC 24 Sep 01 07:05:14 AM UTC 24 4479925870 ps
T76 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all.2624702961 Sep 01 07:04:41 AM UTC 24 Sep 01 07:05:16 AM UTC 24 4793003799 ps
T77 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_kmac_err_chk.2818973907 Sep 01 07:04:56 AM UTC 24 Sep 01 07:05:17 AM UTC 24 4717798619 ps
T78 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_alert_test.1362587958 Sep 01 07:05:01 AM UTC 24 Sep 01 07:05:17 AM UTC 24 1124857123 ps
T79 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all.1041764469 Sep 01 07:04:50 AM UTC 24 Sep 01 07:05:20 AM UTC 24 2077917695 ps
T80 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_kmac_err_chk.436210796 Sep 01 07:04:48 AM UTC 24 Sep 01 07:05:20 AM UTC 24 3533909334 ps
T167 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_kmac_err_chk.3512279216 Sep 01 07:04:52 AM UTC 24 Sep 01 07:05:20 AM UTC 24 332418951 ps
T168 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_max_throughput_chk.79519471 Sep 01 07:05:03 AM UTC 24 Sep 01 07:05:21 AM UTC 24 1173252941 ps
T160 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_alert_test.1288542569 Sep 01 07:05:09 AM UTC 24 Sep 01 07:05:22 AM UTC 24 993350033 ps
T166 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all.3945590625 Sep 01 07:04:39 AM UTC 24 Sep 01 07:05:22 AM UTC 24 551929451 ps
T169 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_kmac_err_chk.3447548273 Sep 01 07:05:00 AM UTC 24 Sep 01 07:05:23 AM UTC 24 505744548 ps
T170 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all.74483397 Sep 01 07:04:59 AM UTC 24 Sep 01 07:05:24 AM UTC 24 749773608 ps
T171 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_max_throughput_chk.631077646 Sep 01 07:05:12 AM UTC 24 Sep 01 07:05:25 AM UTC 24 1153888833 ps
T104 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all.4264196960 Sep 01 07:04:45 AM UTC 24 Sep 01 07:05:26 AM UTC 24 536682674 ps
T165 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_alert_test.46888458 Sep 01 07:05:14 AM UTC 24 Sep 01 07:05:29 AM UTC 24 367617221 ps
T20 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.2896891271 Sep 01 07:04:16 AM UTC 24 Sep 01 07:05:30 AM UTC 24 5277348818 ps
T163 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all.2386574519 Sep 01 07:05:10 AM UTC 24 Sep 01 07:05:32 AM UTC 24 1350815561 ps
T172 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all.2425990528 Sep 01 07:04:54 AM UTC 24 Sep 01 07:05:32 AM UTC 24 1115568761 ps
T173 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_max_throughput_chk.1119763959 Sep 01 07:05:16 AM UTC 24 Sep 01 07:05:32 AM UTC 24 183453485 ps
T63 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_kmac_err_chk.4286431455 Sep 01 07:05:12 AM UTC 24 Sep 01 07:05:34 AM UTC 24 736012771 ps
T174 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_kmac_err_chk.3528611581 Sep 01 07:05:05 AM UTC 24 Sep 01 07:05:34 AM UTC 24 990843597 ps
T162 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_alert_test.2541745992 Sep 01 07:05:23 AM UTC 24 Sep 01 07:05:39 AM UTC 24 253571333 ps
T21 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.2606358269 Sep 01 07:04:35 AM UTC 24 Sep 01 07:05:39 AM UTC 24 1600667673 ps
T175 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_max_throughput_chk.1139787053 Sep 01 07:05:25 AM UTC 24 Sep 01 07:05:40 AM UTC 24 187122111 ps
T176 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_max_throughput_chk.1779529492 Sep 01 07:05:21 AM UTC 24 Sep 01 07:05:41 AM UTC 24 271584283 ps
T27 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_sec_cm.90133890 Sep 01 07:04:14 AM UTC 24 Sep 01 07:06:20 AM UTC 24 1350747111 ps
T40 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_alert_test.3514050856 Sep 01 07:05:19 AM UTC 24 Sep 01 07:05:42 AM UTC 24 1971498525 ps
T41 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_kmac_err_chk.1879580370 Sep 01 07:05:23 AM UTC 24 Sep 01 07:05:43 AM UTC 24 689873689 ps
T42 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all.1017000510 Sep 01 07:05:02 AM UTC 24 Sep 01 07:05:44 AM UTC 24 3852882875 ps
T43 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_kmac_err_chk.3776261342 Sep 01 07:05:18 AM UTC 24 Sep 01 07:05:45 AM UTC 24 2060292659 ps
T44 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all.2505526221 Sep 01 07:05:23 AM UTC 24 Sep 01 07:05:45 AM UTC 24 200544450 ps
T45 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_alert_test.795126638 Sep 01 07:05:31 AM UTC 24 Sep 01 07:05:45 AM UTC 24 172721757 ps
T46 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_max_throughput_chk.1422389740 Sep 01 07:05:34 AM UTC 24 Sep 01 07:05:49 AM UTC 24 187389746 ps
T47 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.1670962716 Sep 01 07:04:48 AM UTC 24 Sep 01 07:05:49 AM UTC 24 1443972270 ps
T48 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_alert_test.1680363940 Sep 01 07:05:36 AM UTC 24 Sep 01 07:05:50 AM UTC 24 174686192 ps
T120 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all.3070543747 Sep 01 07:05:32 AM UTC 24 Sep 01 07:05:51 AM UTC 24 380706034 ps
T66 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.1474069069 Sep 01 07:05:54 AM UTC 24 Sep 01 07:07:44 AM UTC 24 1629601986 ps
T121 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all.3549606950 Sep 01 07:05:38 AM UTC 24 Sep 01 07:05:53 AM UTC 24 376036366 ps
T67 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.443707562 Sep 01 07:04:24 AM UTC 24 Sep 01 07:05:55 AM UTC 24 9396022339 ps
T122 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all.22858814 Sep 01 07:05:14 AM UTC 24 Sep 01 07:05:56 AM UTC 24 2048964567 ps
T123 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_max_throughput_chk.2847135934 Sep 01 07:05:41 AM UTC 24 Sep 01 07:05:58 AM UTC 24 261055751 ps
T124 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_alert_test.996784539 Sep 01 07:05:43 AM UTC 24 Sep 01 07:05:58 AM UTC 24 260656263 ps
T177 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_alert_test.82014019 Sep 01 07:05:47 AM UTC 24 Sep 01 07:06:01 AM UTC 24 168139938 ps
T129 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_max_throughput_chk.1369929167 Sep 01 07:05:45 AM UTC 24 Sep 01 07:06:01 AM UTC 24 369184321 ps
T178 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all.1644148819 Sep 01 07:05:21 AM UTC 24 Sep 01 07:06:02 AM UTC 24 10765771594 ps
T68 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.1048341984 Sep 01 07:04:40 AM UTC 24 Sep 01 07:06:03 AM UTC 24 7207787542 ps
T179 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_kmac_err_chk.2156598746 Sep 01 07:05:34 AM UTC 24 Sep 01 07:06:06 AM UTC 24 342818118 ps
T180 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_kmac_err_chk.858429248 Sep 01 07:05:45 AM UTC 24 Sep 01 07:06:07 AM UTC 24 524190088 ps
T181 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_max_throughput_chk.3784579074 Sep 01 07:05:50 AM UTC 24 Sep 01 07:06:07 AM UTC 24 269983588 ps
T182 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_kmac_err_chk.1959889414 Sep 01 07:05:27 AM UTC 24 Sep 01 07:06:08 AM UTC 24 28035650373 ps
T183 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_alert_test.2168577627 Sep 01 07:05:54 AM UTC 24 Sep 01 07:06:08 AM UTC 24 255099214 ps
T184 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_kmac_err_chk.3860033475 Sep 01 07:05:41 AM UTC 24 Sep 01 07:06:11 AM UTC 24 3961173153 ps
T185 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_kmac_err_chk.4003038602 Sep 01 07:05:52 AM UTC 24 Sep 01 07:06:12 AM UTC 24 1180501835 ps
T186 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_alert_test.2147848971 Sep 01 07:06:02 AM UTC 24 Sep 01 07:06:15 AM UTC 24 570785611 ps
T187 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_max_throughput_chk.1455225964 Sep 01 07:06:04 AM UTC 24 Sep 01 07:06:19 AM UTC 24 523661191 ps
T188 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_kmac_err_chk.4095652748 Sep 01 07:06:00 AM UTC 24 Sep 01 07:06:20 AM UTC 24 337147122 ps
T189 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all.1188409306 Sep 01 07:05:43 AM UTC 24 Sep 01 07:06:22 AM UTC 24 817726739 ps
T190 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_alert_test.3816675736 Sep 01 07:06:08 AM UTC 24 Sep 01 07:06:23 AM UTC 24 517260198 ps
T191 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_max_throughput_chk.2663409742 Sep 01 07:05:58 AM UTC 24 Sep 01 07:06:23 AM UTC 24 1317651107 ps
T192 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_max_throughput_chk.1050650220 Sep 01 07:06:11 AM UTC 24 Sep 01 07:06:25 AM UTC 24 1700056813 ps
T193 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_alert_test.1412900151 Sep 01 07:06:16 AM UTC 24 Sep 01 07:06:33 AM UTC 24 3076595916 ps
T194 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_alert_test.4059147742 Sep 01 07:06:24 AM UTC 24 Sep 01 07:06:35 AM UTC 24 1032217574 ps
T195 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_max_throughput_chk.224656841 Sep 01 07:06:20 AM UTC 24 Sep 01 07:06:36 AM UTC 24 275778101 ps
T28 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_sec_cm.2018406823 Sep 01 07:04:16 AM UTC 24 Sep 01 07:06:43 AM UTC 24 4326317955 ps
T196 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all.2457403327 Sep 01 07:05:50 AM UTC 24 Sep 01 07:06:45 AM UTC 24 1060958102 ps
T69 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.4216257439 Sep 01 07:05:01 AM UTC 24 Sep 01 07:06:47 AM UTC 24 25964468753 ps
T70 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.3310678157 Sep 01 07:04:20 AM UTC 24 Sep 01 07:06:48 AM UTC 24 3366521438 ps
T197 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_max_throughput_chk.4126844530 Sep 01 07:06:34 AM UTC 24 Sep 01 07:06:51 AM UTC 24 260196412 ps
T198 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all.191248810 Sep 01 07:06:02 AM UTC 24 Sep 01 07:06:51 AM UTC 24 2143592158 ps
T199 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_kmac_err_chk.3677155345 Sep 01 07:06:13 AM UTC 24 Sep 01 07:06:55 AM UTC 24 4022107999 ps
T200 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all.4058194477 Sep 01 07:06:10 AM UTC 24 Sep 01 07:06:56 AM UTC 24 6550562346 ps
T201 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_kmac_err_chk.3754470678 Sep 01 07:06:08 AM UTC 24 Sep 01 07:06:57 AM UTC 24 7872262451 ps
T202 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all.3978360533 Sep 01 07:06:26 AM UTC 24 Sep 01 07:06:58 AM UTC 24 1579829384 ps
T203 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_kmac_err_chk.3547679378 Sep 01 07:06:23 AM UTC 24 Sep 01 07:06:58 AM UTC 24 1014605451 ps
T204 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_alert_test.2284730590 Sep 01 07:06:46 AM UTC 24 Sep 01 07:07:00 AM UTC 24 175089472 ps
T205 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all.3332838173 Sep 01 07:05:56 AM UTC 24 Sep 01 07:07:01 AM UTC 24 1354862164 ps
T206 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all.1186873618 Sep 01 07:06:19 AM UTC 24 Sep 01 07:07:01 AM UTC 24 1062120236 ps
T71 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.4164962615 Sep 01 07:05:19 AM UTC 24 Sep 01 07:07:03 AM UTC 24 1619799489 ps
T207 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_kmac_err_chk.1559484092 Sep 01 07:06:37 AM UTC 24 Sep 01 07:07:05 AM UTC 24 496179578 ps
T208 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_max_throughput_chk.3515089563 Sep 01 07:06:49 AM UTC 24 Sep 01 07:07:06 AM UTC 24 183194005 ps
T209 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_alert_test.3001254016 Sep 01 07:06:58 AM UTC 24 Sep 01 07:07:11 AM UTC 24 345787734 ps
T210 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_alert_test.1369645377 Sep 01 07:07:02 AM UTC 24 Sep 01 07:07:13 AM UTC 24 249553617 ps
T22 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.2688434630 Sep 01 07:05:41 AM UTC 24 Sep 01 07:07:14 AM UTC 24 1692663624 ps
T211 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_max_throughput_chk.2128022437 Sep 01 07:06:59 AM UTC 24 Sep 01 07:07:16 AM UTC 24 1036506939 ps
T212 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.2691742491 Sep 01 07:05:14 AM UTC 24 Sep 01 07:07:18 AM UTC 24 7727481694 ps
T213 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all.3582557356 Sep 01 07:06:48 AM UTC 24 Sep 01 07:07:21 AM UTC 24 2235813886 ps
T214 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_kmac_err_chk.3460740720 Sep 01 07:06:52 AM UTC 24 Sep 01 07:07:21 AM UTC 24 9901659303 ps
T215 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_max_throughput_chk.678245270 Sep 01 07:07:06 AM UTC 24 Sep 01 07:07:24 AM UTC 24 270253629 ps
T24 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.1678949850 Sep 01 07:04:14 AM UTC 24 Sep 01 07:07:25 AM UTC 24 8703203834 ps
T216 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_alert_test.910457693 Sep 01 07:07:14 AM UTC 24 Sep 01 07:07:25 AM UTC 24 172767036 ps
T217 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_kmac_err_chk.350895963 Sep 01 07:07:01 AM UTC 24 Sep 01 07:07:32 AM UTC 24 1012983639 ps
T218 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all.2112874843 Sep 01 07:07:04 AM UTC 24 Sep 01 07:07:34 AM UTC 24 304677617 ps
T219 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_stress_all.1275242448 Sep 01 07:07:17 AM UTC 24 Sep 01 07:07:49 AM UTC 24 550629886 ps
T220 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_max_throughput_chk.3867422648 Sep 01 07:07:19 AM UTC 24 Sep 01 07:07:35 AM UTC 24 523784030 ps
T25 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.2971763012 Sep 01 07:04:14 AM UTC 24 Sep 01 07:07:35 AM UTC 24 5361744866 ps
T26 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3864291860 Sep 01 07:04:33 AM UTC 24 Sep 01 07:07:36 AM UTC 24 2532147446 ps
T30 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2385982442 Sep 01 07:04:27 AM UTC 24 Sep 01 07:07:37 AM UTC 24 4879930111 ps
T221 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_alert_test.282618097 Sep 01 07:07:26 AM UTC 24 Sep 01 07:07:38 AM UTC 24 663351282 ps
T222 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_max_throughput_chk.3421884482 Sep 01 07:07:33 AM UTC 24 Sep 01 07:07:48 AM UTC 24 259311124 ps
T223 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_kmac_err_chk.3551065235 Sep 01 07:07:12 AM UTC 24 Sep 01 07:07:38 AM UTC 24 689326021 ps
T65 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.2323985939 Sep 01 07:04:15 AM UTC 24 Sep 01 07:07:38 AM UTC 24 11259098845 ps
T224 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all.3111625317 Sep 01 07:06:58 AM UTC 24 Sep 01 07:07:39 AM UTC 24 722816248 ps
T225 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.69272578 Sep 01 07:05:16 AM UTC 24 Sep 01 07:07:44 AM UTC 24 4013014225 ps
T226 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.329663086 Sep 01 07:04:52 AM UTC 24 Sep 01 07:07:45 AM UTC 24 15571597711 ps
T227 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.2637336763 Sep 01 07:06:15 AM UTC 24 Sep 01 07:07:48 AM UTC 24 29276659354 ps
T228 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.4123981196 Sep 01 07:06:02 AM UTC 24 Sep 01 07:07:49 AM UTC 24 20917303733 ps
T229 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_alert_test.220940941 Sep 01 07:07:40 AM UTC 24 Sep 01 07:07:50 AM UTC 24 175110744 ps
T230 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_alert_test.3930607063 Sep 01 07:07:36 AM UTC 24 Sep 01 07:07:52 AM UTC 24 498202048 ps
T231 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.4236112243 Sep 01 07:05:47 AM UTC 24 Sep 01 07:07:52 AM UTC 24 2378008678 ps
T232 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_kmac_err_chk.3330719982 Sep 01 07:07:22 AM UTC 24 Sep 01 07:07:55 AM UTC 24 506465569 ps
T233 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_kmac_err_chk.361551688 Sep 01 07:07:35 AM UTC 24 Sep 01 07:07:57 AM UTC 24 338996417 ps
T234 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.244988095 Sep 01 07:04:57 AM UTC 24 Sep 01 07:07:57 AM UTC 24 2624215035 ps
T235 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_max_throughput_chk.223975954 Sep 01 07:07:38 AM UTC 24 Sep 01 07:07:58 AM UTC 24 1083604954 ps
T236 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.3919156915 Sep 01 07:05:23 AM UTC 24 Sep 01 07:07:58 AM UTC 24 16943474070 ps
T155 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.1278158795 Sep 01 07:04:27 AM UTC 24 Sep 01 07:08:00 AM UTC 24 15507877606 ps
T237 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.3216607791 Sep 01 07:06:44 AM UTC 24 Sep 01 07:08:00 AM UTC 24 4289842478 ps
T238 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_kmac_err_chk.2215401556 Sep 01 07:07:39 AM UTC 24 Sep 01 07:08:03 AM UTC 24 2360777027 ps
T239 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_max_throughput_chk.2570583013 Sep 01 07:07:45 AM UTC 24 Sep 01 07:08:03 AM UTC 24 1113837356 ps
T240 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_alert_test.81922303 Sep 01 07:07:49 AM UTC 24 Sep 01 07:08:04 AM UTC 24 516673391 ps
T241 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_max_throughput_chk.3130095067 Sep 01 07:07:51 AM UTC 24 Sep 01 07:08:09 AM UTC 24 261611399 ps
T50 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2091704647 Sep 01 07:04:43 AM UTC 24 Sep 01 07:08:10 AM UTC 24 3255810533 ps
T242 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all.2486423234 Sep 01 07:07:26 AM UTC 24 Sep 01 07:08:10 AM UTC 24 3302524734 ps
T243 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_alert_test.763850372 Sep 01 07:07:58 AM UTC 24 Sep 01 07:08:11 AM UTC 24 266818850 ps
T244 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_kmac_err_chk.1367087677 Sep 01 07:07:49 AM UTC 24 Sep 01 07:08:13 AM UTC 24 2152510420 ps
T245 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_max_throughput_chk.1354360272 Sep 01 07:07:59 AM UTC 24 Sep 01 07:08:18 AM UTC 24 260176203 ps
T246 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_max_throughput_chk.3293479212 Sep 01 07:08:05 AM UTC 24 Sep 01 07:08:18 AM UTC 24 714972063 ps
T247 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_alert_test.2365569913 Sep 01 07:08:04 AM UTC 24 Sep 01 07:08:19 AM UTC 24 255120500 ps
T248 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.868154010 Sep 01 07:07:02 AM UTC 24 Sep 01 07:08:23 AM UTC 24 6615783510 ps
T249 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_kmac_err_chk.4271707575 Sep 01 07:07:53 AM UTC 24 Sep 01 07:08:23 AM UTC 24 992173341 ps
T250 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_alert_test.140512938 Sep 01 07:08:11 AM UTC 24 Sep 01 07:08:26 AM UTC 24 990616095 ps
T251 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all.1206951459 Sep 01 07:07:50 AM UTC 24 Sep 01 07:08:26 AM UTC 24 2101675383 ps
T252 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all.2900897346 Sep 01 07:08:04 AM UTC 24 Sep 01 07:08:29 AM UTC 24 1422591824 ps
T29 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_sec_cm.1090072823 Sep 01 07:04:21 AM UTC 24 Sep 01 07:08:31 AM UTC 24 1424685213 ps
T253 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.1039954382 Sep 01 07:06:08 AM UTC 24 Sep 01 07:08:32 AM UTC 24 4962935481 ps
T254 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.2623519753 Sep 01 07:07:13 AM UTC 24 Sep 01 07:08:32 AM UTC 24 1620651296 ps
T38 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_sec_cm.474149361 Sep 01 07:04:14 AM UTC 24 Sep 01 07:08:33 AM UTC 24 396967756 ps
T255 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_max_throughput_chk.746120464 Sep 01 07:08:19 AM UTC 24 Sep 01 07:08:34 AM UTC 24 261392760 ps
T256 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all.3827578810 Sep 01 07:07:38 AM UTC 24 Sep 01 07:08:35 AM UTC 24 1060409845 ps
T257 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_kmac_err_chk.1787483302 Sep 01 07:08:01 AM UTC 24 Sep 01 07:08:36 AM UTC 24 517870378 ps
T258 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.3942863376 Sep 01 07:04:14 AM UTC 24 Sep 01 07:08:40 AM UTC 24 4553975373 ps
T259 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_alert_test.3709955102 Sep 01 07:08:24 AM UTC 24 Sep 01 07:08:40 AM UTC 24 251983560 ps
T260 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_max_throughput_chk.2714323393 Sep 01 07:08:27 AM UTC 24 Sep 01 07:08:41 AM UTC 24 1421175966 ps
T261 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_kmac_err_chk.677485645 Sep 01 07:08:11 AM UTC 24 Sep 01 07:08:41 AM UTC 24 1380511893 ps
T262 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all.2294724162 Sep 01 07:07:45 AM UTC 24 Sep 01 07:08:42 AM UTC 24 3914505819 ps
T263 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all.4020930139 Sep 01 07:08:14 AM UTC 24 Sep 01 07:08:44 AM UTC 24 1535468935 ps
T264 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all.2296472750 Sep 01 07:07:59 AM UTC 24 Sep 01 07:08:46 AM UTC 24 2153324871 ps
T265 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.201753563 Sep 01 07:05:08 AM UTC 24 Sep 01 07:08:46 AM UTC 24 4798687523 ps
T266 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.69600357 Sep 01 07:06:55 AM UTC 24 Sep 01 07:08:48 AM UTC 24 1945193935 ps
T267 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_alert_test.860048353 Sep 01 07:08:33 AM UTC 24 Sep 01 07:08:48 AM UTC 24 260257669 ps
T268 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_max_throughput_chk.2803654831 Sep 01 07:08:34 AM UTC 24 Sep 01 07:08:49 AM UTC 24 860470510 ps
T269 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_alert_test.786310956 Sep 01 07:08:41 AM UTC 24 Sep 01 07:08:52 AM UTC 24 260839120 ps
T270 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_kmac_err_chk.1550190301 Sep 01 07:08:30 AM UTC 24 Sep 01 07:08:52 AM UTC 24 672827988 ps
T271 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_kmac_err_chk.2813848238 Sep 01 07:08:20 AM UTC 24 Sep 01 07:08:53 AM UTC 24 497565406 ps
T272 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.3694520226 Sep 01 07:05:27 AM UTC 24 Sep 01 07:08:54 AM UTC 24 41388081931 ps
T273 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.2236356959 Sep 01 07:08:11 AM UTC 24 Sep 01 07:08:54 AM UTC 24 1030082492 ps
T51 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.3289818975 Sep 01 07:04:52 AM UTC 24 Sep 01 07:08:55 AM UTC 24 3143265864 ps
T274 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_max_throughput_chk.1593589543 Sep 01 07:08:41 AM UTC 24 Sep 01 07:08:56 AM UTC 24 690714336 ps
T275 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_alert_test.2457252132 Sep 01 07:08:47 AM UTC 24 Sep 01 07:08:57 AM UTC 24 167410200 ps
T52 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.2101207440 Sep 01 07:04:47 AM UTC 24 Sep 01 07:08:58 AM UTC 24 8148498868 ps
T276 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.3067617594 Sep 01 07:04:14 AM UTC 24 Sep 01 07:08:58 AM UTC 24 4346381182 ps
T277 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_max_throughput_chk.909055250 Sep 01 07:08:49 AM UTC 24 Sep 01 07:09:01 AM UTC 24 739463011 ps
T53 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.4262837228 Sep 01 07:05:12 AM UTC 24 Sep 01 07:09:01 AM UTC 24 10003156731 ps
T278 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all.4047007572 Sep 01 07:08:27 AM UTC 24 Sep 01 07:09:02 AM UTC 24 2087662053 ps
T279 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_alert_test.1953094325 Sep 01 07:08:53 AM UTC 24 Sep 01 07:09:03 AM UTC 24 176730535 ps
T151 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.1332805347 Sep 01 07:06:21 AM UTC 24 Sep 01 07:09:04 AM UTC 24 2347377971 ps
T280 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.1236597085 Sep 01 07:08:01 AM UTC 24 Sep 01 07:09:05 AM UTC 24 4463559137 ps
T60 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_kmac_err_chk.2866567725 Sep 01 07:08:36 AM UTC 24 Sep 01 07:09:09 AM UTC 24 1590050979 ps
T281 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_max_throughput_chk.1941606475 Sep 01 07:08:59 AM UTC 24 Sep 01 07:09:10 AM UTC 24 724218367 ps
T282 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all.1261685247 Sep 01 07:08:47 AM UTC 24 Sep 01 07:09:12 AM UTC 24 1496499156 ps
T61 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_max_throughput_chk.3018704704 Sep 01 07:08:54 AM UTC 24 Sep 01 07:09:12 AM UTC 24 1217268889 ps
T283 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_alert_test.2305012662 Sep 01 07:08:57 AM UTC 24 Sep 01 07:09:13 AM UTC 24 255231722 ps
T284 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_alert_test.3723351741 Sep 01 07:09:03 AM UTC 24 Sep 01 07:09:15 AM UTC 24 2754729310 ps
T62 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_kmac_err_chk.3175508278 Sep 01 07:08:43 AM UTC 24 Sep 01 07:09:15 AM UTC 24 337105014 ps
T285 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all.174901730 Sep 01 07:08:33 AM UTC 24 Sep 01 07:09:16 AM UTC 24 747664541 ps
T286 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all.3213138249 Sep 01 07:08:41 AM UTC 24 Sep 01 07:09:17 AM UTC 24 272189655 ps
T287 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_kmac_err_chk.4013770795 Sep 01 07:08:55 AM UTC 24 Sep 01 07:09:18 AM UTC 24 2067465821 ps
T64 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.4102790117 Sep 01 07:06:36 AM UTC 24 Sep 01 07:09:19 AM UTC 24 55262066549 ps
T54 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.611143338 Sep 01 07:05:25 AM UTC 24 Sep 01 07:09:19 AM UTC 24 4822003348 ps
T288 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.2689611797 Sep 01 07:07:55 AM UTC 24 Sep 01 07:09:19 AM UTC 24 11422886686 ps
T289 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_kmac_err_chk.2923329690 Sep 01 07:08:50 AM UTC 24 Sep 01 07:09:21 AM UTC 24 1381015872 ps
T290 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_max_throughput_chk.584411816 Sep 01 07:09:04 AM UTC 24 Sep 01 07:09:21 AM UTC 24 515406578 ps
T291 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_kmac_err_chk.2564855454 Sep 01 07:09:02 AM UTC 24 Sep 01 07:09:22 AM UTC 24 347548737 ps
T292 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_alert_test.3538638470 Sep 01 07:09:12 AM UTC 24 Sep 01 07:09:24 AM UTC 24 168405501 ps
T293 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_max_throughput_chk.4122021020 Sep 01 07:09:13 AM UTC 24 Sep 01 07:09:27 AM UTC 24 176919715 ps
T294 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_alert_test.1850661334 Sep 01 07:09:16 AM UTC 24 Sep 01 07:09:29 AM UTC 24 689268453 ps
T295 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_kmac_err_chk.3952266529 Sep 01 07:09:10 AM UTC 24 Sep 01 07:09:30 AM UTC 24 2540261973 ps
T296 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all.2675447252 Sep 01 07:09:13 AM UTC 24 Sep 01 07:09:31 AM UTC 24 536913258 ps
T297 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.4005378418 Sep 01 07:06:59 AM UTC 24 Sep 01 07:09:31 AM UTC 24 2256784209 ps
T39 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_sec_cm.3393646022 Sep 01 07:04:14 AM UTC 24 Sep 01 07:09:31 AM UTC 24 490474776 ps
T298 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all.291103113 Sep 01 07:08:53 AM UTC 24 Sep 01 07:09:32 AM UTC 24 534770521 ps
T299 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.2677265827 Sep 01 07:04:24 AM UTC 24 Sep 01 07:09:34 AM UTC 24 3900392464 ps
T300 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_alert_test.3037931180 Sep 01 07:09:22 AM UTC 24 Sep 01 07:09:36 AM UTC 24 505965002 ps
T301 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_max_throughput_chk.1913661791 Sep 01 07:09:18 AM UTC 24 Sep 01 07:09:36 AM UTC 24 183382339 ps
T302 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_max_throughput_chk.4241858743 Sep 01 07:09:23 AM UTC 24 Sep 01 07:09:39 AM UTC 24 727531408 ps
T303 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all.4284404962 Sep 01 07:08:58 AM UTC 24 Sep 01 07:09:40 AM UTC 24 1058194233 ps
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