Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.42 96.89 91.99 97.68 100.00 98.28 98.05 99.06


Total tests in report: 458
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
65.25 65.25 92.58 92.58 70.65 70.65 49.78 49.78 40.00 40.00 90.00 90.00 93.85 93.85 19.91 19.91 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all.1600804656
81.55 16.30 95.93 3.35 80.90 10.25 78.01 28.24 40.00 0.00 92.76 2.76 95.65 1.80 87.59 67.68 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.932089587
85.78 4.23 95.93 0.00 83.15 2.25 78.01 0.00 66.67 26.67 93.10 0.34 95.80 0.15 87.82 0.23 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.167616530
88.98 3.20 96.17 0.24 87.78 4.63 85.43 7.42 73.33 6.67 95.52 2.41 96.10 0.30 88.52 0.70 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_kmac_err_chk.2451573423
91.62 2.64 96.53 0.36 88.20 0.42 88.28 2.85 86.67 13.33 96.55 1.03 96.10 0.00 88.99 0.47 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all.128371882
93.37 1.75 96.77 0.24 90.17 1.97 89.41 1.12 93.33 6.67 97.59 1.03 96.40 0.30 89.93 0.94 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_sec_cm.3079074461
94.48 1.11 96.89 0.12 90.59 0.42 89.41 0.00 100.00 6.67 97.93 0.34 96.40 0.00 90.16 0.23 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.4290342248
95.48 1.00 96.89 0.00 91.01 0.42 89.41 0.00 100.00 0.00 97.93 0.00 96.40 0.00 96.72 6.56 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1160633152
96.23 0.75 96.89 0.00 91.01 0.00 94.65 5.25 100.00 0.00 97.93 0.00 96.40 0.00 96.72 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all.217637598
96.47 0.24 96.89 0.00 91.15 0.14 96.23 1.57 100.00 0.00 97.93 0.00 96.40 0.00 96.72 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.1971064293
96.64 0.17 96.89 0.00 91.29 0.14 96.23 0.00 100.00 0.00 97.93 0.00 97.45 1.05 96.72 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2120256460
96.79 0.14 96.89 0.00 91.29 0.00 96.83 0.60 100.00 0.00 97.93 0.00 97.60 0.15 96.96 0.23 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all.446276243
96.92 0.13 96.89 0.00 91.29 0.00 96.83 0.00 100.00 0.00 97.93 0.00 97.60 0.00 97.89 0.94 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3313020529
97.02 0.11 96.89 0.00 91.85 0.56 97.00 0.17 100.00 0.00 97.93 0.00 97.60 0.00 97.89 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_alert_test.17999850
97.10 0.08 96.89 0.00 91.99 0.14 97.08 0.07 100.00 0.00 98.28 0.34 97.60 0.00 97.89 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_kmac_err_chk.3176837136
97.17 0.07 96.89 0.00 91.99 0.00 97.08 0.00 100.00 0.00 98.28 0.00 97.60 0.00 98.36 0.47 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.920064286
97.22 0.05 96.89 0.00 91.99 0.00 97.45 0.37 100.00 0.00 98.28 0.00 97.60 0.00 98.36 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all.610494520
97.27 0.04 96.89 0.00 91.99 0.00 97.45 0.00 100.00 0.00 98.28 0.00 97.90 0.30 98.36 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1116446035
97.31 0.04 96.89 0.00 91.99 0.00 97.50 0.05 100.00 0.00 98.28 0.00 97.90 0.00 98.59 0.23 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_max_throughput_chk.2120858290
97.34 0.03 96.89 0.00 91.99 0.00 97.50 0.00 100.00 0.00 98.28 0.00 97.90 0.00 98.83 0.23 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3566974168
97.38 0.03 96.89 0.00 91.99 0.00 97.50 0.00 100.00 0.00 98.28 0.00 97.90 0.00 99.06 0.23 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_sec_cm.2508054566
97.40 0.02 96.89 0.00 91.99 0.00 97.50 0.00 100.00 0.00 98.28 0.00 98.05 0.15 99.06 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_max_throughput_chk.2476083223
97.41 0.02 96.89 0.00 91.99 0.00 97.63 0.12 100.00 0.00 98.28 0.00 98.05 0.00 99.06 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_kmac_err_chk.540759756
97.42 0.01 96.89 0.00 91.99 0.00 97.68 0.05 100.00 0.00 98.28 0.00 98.05 0.00 99.06 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all.1033710435

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1655428023
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3580921221
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.178939508
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3079500989
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.116454095
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3214214267
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3040801840
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2253502497
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1034469891
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.4153214644
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3876461953
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.428155315
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1766432941
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.619956034
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_rw.793242235
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2586330316
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2988571019
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3226134614
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1643679273
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_errors.839664398
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.4242153121
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1501234475
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3457544440
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3281460521
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.602439059
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1551866976
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.4243827746
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3779576985
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_rw.578431553
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1107945526
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1733385130
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_errors.555561380
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3781939736
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1223536893
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_rw.83354270
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2970639476
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3331359402
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3316385255
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2948136102
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_rw.780312545
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.386746988
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1396852673
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3650300223
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1785145652
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1925939963
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3901245765
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.4273938218
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3980199428
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1665173474
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.4147815567
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1681586087
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_rw.174550099
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.474813942
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.666164096
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2200828663
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1858820989
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1049709953
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2256934663
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3338382082
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2102023085
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3461214832
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2415153509
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1148028592
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3988916811
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.4017993749
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.973345675
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3856731995
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3762008298
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3521988257
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_rw.4053042639
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.156541891
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1276076906
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1702767856
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.148383189
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.274480890
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3206224708
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3259440226
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2364236115
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1945536873
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2981078755
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2507679797
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.4208783050
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3886800644
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.484909459
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_rw.4189363725
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2579353074
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Total test records in report: 458
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_smoke.1330101401 Sep 04 02:03:51 AM UTC 24 Sep 04 02:04:03 AM UTC 24 333743151 ps
T2 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_sec_cm.3079074461 Sep 04 02:04:01 AM UTC 24 Sep 04 02:06:12 AM UTC 24 1200119343 ps
T3 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_max_throughput_chk.2120858290 Sep 04 02:03:51 AM UTC 24 Sep 04 02:04:03 AM UTC 24 514728195 ps
T4 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_alert_test.2828665959 Sep 04 02:04:01 AM UTC 24 Sep 04 02:04:11 AM UTC 24 506535526 ps
T5 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_max_throughput_chk.973590002 Sep 04 02:04:01 AM UTC 24 Sep 04 02:04:12 AM UTC 24 176970607 ps
T6 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_smoke.1386340363 Sep 04 02:04:01 AM UTC 24 Sep 04 02:04:12 AM UTC 24 351124323 ps
T7 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_alert_test.2208009196 Sep 04 02:04:01 AM UTC 24 Sep 04 02:04:12 AM UTC 24 1182665234 ps
T8 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_smoke.1133733436 Sep 04 02:04:01 AM UTC 24 Sep 04 02:04:13 AM UTC 24 680991355 ps
T9 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_max_throughput_chk.2358752118 Sep 04 02:04:01 AM UTC 24 Sep 04 02:04:14 AM UTC 24 268689875 ps
T10 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all.1600804656 Sep 04 02:03:51 AM UTC 24 Sep 04 02:04:15 AM UTC 24 1112060141 ps
T29 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_alert_test.1451158490 Sep 04 02:05:19 AM UTC 24 Sep 04 02:05:32 AM UTC 24 338484268 ps
T37 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_alert_test.4032700673 Sep 04 02:04:01 AM UTC 24 Sep 04 02:04:15 AM UTC 24 689141770 ps
T21 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_smoke.669395848 Sep 04 02:04:01 AM UTC 24 Sep 04 02:04:16 AM UTC 24 178034668 ps
T77 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_alert_test.18443667 Sep 04 02:04:02 AM UTC 24 Sep 04 02:04:19 AM UTC 24 3540055004 ps
T11 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_kmac_err_chk.540759756 Sep 04 02:04:02 AM UTC 24 Sep 04 02:04:23 AM UTC 24 1011512572 ps
T28 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_kmac_err_chk.2451573423 Sep 04 02:04:01 AM UTC 24 Sep 04 02:04:24 AM UTC 24 9875984114 ps
T17 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_smoke.1980636245 Sep 04 02:04:02 AM UTC 24 Sep 04 02:04:27 AM UTC 24 532862611 ps
T22 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_max_throughput_chk.2973029971 Sep 04 02:04:02 AM UTC 24 Sep 04 02:04:27 AM UTC 24 260216041 ps
T55 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_alert_test.2956838351 Sep 04 02:04:12 AM UTC 24 Sep 04 02:04:27 AM UTC 24 251014521 ps
T128 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_max_throughput_chk.3187403660 Sep 04 02:04:02 AM UTC 24 Sep 04 02:04:27 AM UTC 24 941210888 ps
T30 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all.1338108785 Sep 04 02:04:02 AM UTC 24 Sep 04 02:04:28 AM UTC 24 731969984 ps
T78 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_alert_test.17999850 Sep 04 02:04:16 AM UTC 24 Sep 04 02:04:28 AM UTC 24 273882630 ps
T129 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_max_throughput_chk.181369794 Sep 04 02:04:13 AM UTC 24 Sep 04 02:04:29 AM UTC 24 852670527 ps
T31 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_kmac_err_chk.1784625671 Sep 04 02:04:01 AM UTC 24 Sep 04 02:04:29 AM UTC 24 2249331584 ps
T73 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_smoke.2454978272 Sep 04 02:04:13 AM UTC 24 Sep 04 02:04:31 AM UTC 24 268741295 ps
T15 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all.2499060629 Sep 04 02:04:01 AM UTC 24 Sep 04 02:04:31 AM UTC 24 537478231 ps
T20 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_smoke.4097093288 Sep 04 02:04:17 AM UTC 24 Sep 04 02:04:32 AM UTC 24 1067420785 ps
T33 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_kmac_err_chk.3755131220 Sep 04 02:04:02 AM UTC 24 Sep 04 02:04:32 AM UTC 24 1338485817 ps
T32 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all.1664906195 Sep 04 02:04:01 AM UTC 24 Sep 04 02:04:32 AM UTC 24 2120074413 ps
T34 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_kmac_err_chk.1945023290 Sep 04 02:04:01 AM UTC 24 Sep 04 02:04:34 AM UTC 24 1325265512 ps
T130 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_max_throughput_chk.446524812 Sep 04 02:04:23 AM UTC 24 Sep 04 02:04:36 AM UTC 24 260731695 ps
T79 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_alert_test.1215833993 Sep 04 02:04:29 AM UTC 24 Sep 04 02:04:39 AM UTC 24 688530828 ps
T16 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_max_throughput_chk.3130104408 Sep 04 02:04:29 AM UTC 24 Sep 04 02:04:41 AM UTC 24 2547832453 ps
T43 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_kmac_err_chk.1625245 Sep 04 02:04:14 AM UTC 24 Sep 04 02:04:42 AM UTC 24 2251286790 ps
T80 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_alert_test.1210121679 Sep 04 02:04:30 AM UTC 24 Sep 04 02:04:45 AM UTC 24 918492368 ps
T12 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.932089587 Sep 04 02:04:01 AM UTC 24 Sep 04 02:04:45 AM UTC 24 4871662283 ps
T63 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all.302657883 Sep 04 02:04:02 AM UTC 24 Sep 04 02:04:46 AM UTC 24 1098049918 ps
T64 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_alert_test.4090004671 Sep 04 02:04:33 AM UTC 24 Sep 04 02:04:46 AM UTC 24 259946185 ps
T65 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_smoke.2006505129 Sep 04 02:04:29 AM UTC 24 Sep 04 02:04:47 AM UTC 24 521005876 ps
T66 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_max_throughput_chk.1295227201 Sep 04 02:04:33 AM UTC 24 Sep 04 02:04:47 AM UTC 24 184607182 ps
T44 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_kmac_err_chk.3949505355 Sep 04 02:04:25 AM UTC 24 Sep 04 02:04:49 AM UTC 24 8244868666 ps
T67 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_max_throughput_chk.4216681833 Sep 04 02:04:34 AM UTC 24 Sep 04 02:04:49 AM UTC 24 372526701 ps
T68 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all.128371882 Sep 04 02:04:20 AM UTC 24 Sep 04 02:04:50 AM UTC 24 2109551096 ps
T69 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_smoke.4024614099 Sep 04 02:04:33 AM UTC 24 Sep 04 02:04:50 AM UTC 24 720457064 ps
T45 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_kmac_err_chk.1079762400 Sep 04 02:04:33 AM UTC 24 Sep 04 02:04:53 AM UTC 24 1325241527 ps
T155 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_alert_test.143021254 Sep 04 02:04:44 AM UTC 24 Sep 04 02:04:54 AM UTC 24 869567456 ps
T89 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all.610494520 Sep 04 02:04:13 AM UTC 24 Sep 04 02:04:58 AM UTC 24 1105088311 ps
T46 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_kmac_err_chk.3397911449 Sep 04 02:04:29 AM UTC 24 Sep 04 02:04:58 AM UTC 24 3293579634 ps
T90 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_smoke.3025911077 Sep 04 02:04:33 AM UTC 24 Sep 04 02:04:59 AM UTC 24 1034357394 ps
T151 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all.1654597236 Sep 04 02:04:29 AM UTC 24 Sep 04 02:04:59 AM UTC 24 819145645 ps
T154 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_alert_test.2317497095 Sep 04 02:04:50 AM UTC 24 Sep 04 02:05:00 AM UTC 24 168192230 ps
T148 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_max_throughput_chk.3172181383 Sep 04 02:04:47 AM UTC 24 Sep 04 02:05:01 AM UTC 24 259378602 ps
T156 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_kmac_err_chk.1472319435 Sep 04 02:04:40 AM UTC 24 Sep 04 02:05:03 AM UTC 24 1180513939 ps
T152 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all.3276612768 Sep 04 02:04:33 AM UTC 24 Sep 04 02:05:04 AM UTC 24 2131108545 ps
T157 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_alert_test.1776643775 Sep 04 02:04:54 AM UTC 24 Sep 04 02:05:07 AM UTC 24 259089962 ps
T142 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_max_throughput_chk.446552061 Sep 04 02:04:50 AM UTC 24 Sep 04 02:05:11 AM UTC 24 1045011337 ps
T158 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_kmac_err_chk.3215946484 Sep 04 02:04:48 AM UTC 24 Sep 04 02:05:12 AM UTC 24 1983118771 ps
T159 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_max_throughput_chk.1171238284 Sep 04 02:05:00 AM UTC 24 Sep 04 02:05:13 AM UTC 24 260282606 ps
T149 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all.172220072 Sep 04 02:04:54 AM UTC 24 Sep 04 02:05:13 AM UTC 24 874672310 ps
T150 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_max_throughput_chk.4073754872 Sep 04 02:05:05 AM UTC 24 Sep 04 02:05:18 AM UTC 24 176968714 ps
T160 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_alert_test.3944051959 Sep 04 02:05:02 AM UTC 24 Sep 04 02:05:18 AM UTC 24 260604525 ps
T57 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all.217637598 Sep 04 02:04:33 AM UTC 24 Sep 04 02:05:20 AM UTC 24 1322674963 ps
T143 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_kmac_err_chk.1002702689 Sep 04 02:04:52 AM UTC 24 Sep 04 02:05:23 AM UTC 24 2349498634 ps
T13 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.2519561915 Sep 04 02:04:04 AM UTC 24 Sep 04 02:05:25 AM UTC 24 6534267898 ps
T14 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.3135986053 Sep 04 02:05:12 AM UTC 24 Sep 04 02:05:28 AM UTC 24 2257478998 ps
T153 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all.1033710435 Sep 04 02:04:47 AM UTC 24 Sep 04 02:05:29 AM UTC 24 3244221915 ps
T50 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_kmac_err_chk.3176837136 Sep 04 02:05:00 AM UTC 24 Sep 04 02:05:30 AM UTC 24 1271012229 ps
T161 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_max_throughput_chk.229392162 Sep 04 02:05:14 AM UTC 24 Sep 04 02:05:30 AM UTC 24 1074973070 ps
T18 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.1971064293 Sep 04 02:04:02 AM UTC 24 Sep 04 02:05:31 AM UTC 24 1942696551 ps
T162 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_alert_test.1579940307 Sep 04 02:05:14 AM UTC 24 Sep 04 02:05:33 AM UTC 24 1029976103 ps
T163 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_kmac_err_chk.2305628771 Sep 04 02:05:09 AM UTC 24 Sep 04 02:05:34 AM UTC 24 1829187931 ps
T58 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.947994209 Sep 04 02:04:42 AM UTC 24 Sep 04 02:05:35 AM UTC 24 1113355138 ps
T91 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all.3784828330 Sep 04 02:05:02 AM UTC 24 Sep 04 02:05:37 AM UTC 24 1218205931 ps
T164 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_max_throughput_chk.3076638542 Sep 04 02:05:24 AM UTC 24 Sep 04 02:05:37 AM UTC 24 1021112848 ps
T165 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_alert_test.4005201066 Sep 04 02:05:31 AM UTC 24 Sep 04 02:05:44 AM UTC 24 3061682171 ps
T51 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_kmac_err_chk.3022058198 Sep 04 02:05:15 AM UTC 24 Sep 04 02:05:45 AM UTC 24 1572088368 ps
T166 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_max_throughput_chk.3495716458 Sep 04 02:05:32 AM UTC 24 Sep 04 02:05:49 AM UTC 24 699754745 ps
T92 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all.1796917983 Sep 04 02:05:14 AM UTC 24 Sep 04 02:05:50 AM UTC 24 2085142140 ps
T167 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_alert_test.2437906751 Sep 04 02:05:36 AM UTC 24 Sep 04 02:05:52 AM UTC 24 956726172 ps
T168 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_max_throughput_chk.3070047601 Sep 04 02:05:38 AM UTC 24 Sep 04 02:05:55 AM UTC 24 867631935 ps
T19 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.684147158 Sep 04 02:04:29 AM UTC 24 Sep 04 02:05:56 AM UTC 24 9958196359 ps
T169 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_kmac_err_chk.1021774955 Sep 04 02:05:34 AM UTC 24 Sep 04 02:05:57 AM UTC 24 337178739 ps
T52 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_kmac_err_chk.3898288717 Sep 04 02:05:30 AM UTC 24 Sep 04 02:05:57 AM UTC 24 688927316 ps
T170 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_alert_test.1439801806 Sep 04 02:05:49 AM UTC 24 Sep 04 02:06:00 AM UTC 24 1078113677 ps
T171 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_max_throughput_chk.1028362748 Sep 04 02:05:53 AM UTC 24 Sep 04 02:06:07 AM UTC 24 1021383923 ps
T172 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_alert_test.795384826 Sep 04 02:05:58 AM UTC 24 Sep 04 02:06:12 AM UTC 24 169710081 ps
T173 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all.3486894917 Sep 04 02:05:51 AM UTC 24 Sep 04 02:06:13 AM UTC 24 433390313 ps
T93 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all.446276243 Sep 04 02:04:50 AM UTC 24 Sep 04 02:06:16 AM UTC 24 4251633340 ps
T174 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all.3738864621 Sep 04 02:05:20 AM UTC 24 Sep 04 02:06:16 AM UTC 24 7962713387 ps
T26 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_sec_cm.187664585 Sep 04 02:04:01 AM UTC 24 Sep 04 02:06:17 AM UTC 24 311802201 ps
T27 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_sec_cm.1182360086 Sep 04 02:04:04 AM UTC 24 Sep 04 02:06:18 AM UTC 24 290407365 ps
T175 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_kmac_err_chk.455423657 Sep 04 02:05:46 AM UTC 24 Sep 04 02:06:18 AM UTC 24 1413294575 ps
T35 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_sec_cm.4012352810 Sep 04 02:04:02 AM UTC 24 Sep 04 02:06:19 AM UTC 24 291329865 ps
T59 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.92967207 Sep 04 02:04:01 AM UTC 24 Sep 04 02:06:23 AM UTC 24 2857532618 ps
T94 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all.1758041955 Sep 04 02:05:38 AM UTC 24 Sep 04 02:06:24 AM UTC 24 2113572987 ps
T176 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_max_throughput_chk.1905825198 Sep 04 02:06:08 AM UTC 24 Sep 04 02:06:26 AM UTC 24 190380717 ps
T177 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_kmac_err_chk.3918193359 Sep 04 02:05:57 AM UTC 24 Sep 04 02:06:26 AM UTC 24 4707100358 ps
T60 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.3072018047 Sep 04 02:05:49 AM UTC 24 Sep 04 02:06:26 AM UTC 24 8769179835 ps
T178 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_alert_test.2477183734 Sep 04 02:06:16 AM UTC 24 Sep 04 02:06:29 AM UTC 24 181813058 ps
T61 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.4257606958 Sep 04 02:04:15 AM UTC 24 Sep 04 02:06:29 AM UTC 24 6247247240 ps
T179 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all.150138487 Sep 04 02:05:31 AM UTC 24 Sep 04 02:06:30 AM UTC 24 775839051 ps
T180 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_alert_test.2701067627 Sep 04 02:06:24 AM UTC 24 Sep 04 02:06:36 AM UTC 24 332311816 ps
T23 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.2685310688 Sep 04 02:04:13 AM UTC 24 Sep 04 02:06:36 AM UTC 24 2788786099 ps
T181 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_max_throughput_chk.2880718361 Sep 04 02:06:17 AM UTC 24 Sep 04 02:06:37 AM UTC 24 260358272 ps
T62 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.3092535561 Sep 04 02:04:33 AM UTC 24 Sep 04 02:06:38 AM UTC 24 4608604578 ps
T182 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_kmac_err_chk.3390909972 Sep 04 02:06:13 AM UTC 24 Sep 04 02:06:40 AM UTC 24 501890349 ps
T183 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all.672474617 Sep 04 02:06:25 AM UTC 24 Sep 04 02:06:41 AM UTC 24 903704221 ps
T184 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_alert_test.4142489576 Sep 04 02:06:30 AM UTC 24 Sep 04 02:06:43 AM UTC 24 662105282 ps
T185 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_max_throughput_chk.637656149 Sep 04 02:06:27 AM UTC 24 Sep 04 02:06:46 AM UTC 24 1810286283 ps
T186 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_kmac_err_chk.2741240146 Sep 04 02:06:19 AM UTC 24 Sep 04 02:06:47 AM UTC 24 4125606653 ps
T187 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all.1845427524 Sep 04 02:06:17 AM UTC 24 Sep 04 02:06:48 AM UTC 24 396301228 ps
T24 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3869951856 Sep 04 02:04:01 AM UTC 24 Sep 04 02:06:50 AM UTC 24 6475323611 ps
T188 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.1718435925 Sep 04 02:05:58 AM UTC 24 Sep 04 02:06:51 AM UTC 24 4106881228 ps
T189 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_max_throughput_chk.1186763874 Sep 04 02:06:37 AM UTC 24 Sep 04 02:06:52 AM UTC 24 584153996 ps
T190 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all.1016392365 Sep 04 02:06:00 AM UTC 24 Sep 04 02:06:53 AM UTC 24 560213238 ps
T191 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all.3129550213 Sep 04 02:06:42 AM UTC 24 Sep 04 02:06:53 AM UTC 24 611995062 ps
T192 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_alert_test.1767840912 Sep 04 02:06:41 AM UTC 24 Sep 04 02:06:54 AM UTC 24 251705046 ps
T193 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.4132385294 Sep 04 02:05:30 AM UTC 24 Sep 04 02:07:00 AM UTC 24 1737284812 ps
T194 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_max_throughput_chk.3465319229 Sep 04 02:06:44 AM UTC 24 Sep 04 02:07:01 AM UTC 24 318182690 ps
T195 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_kmac_err_chk.2830730120 Sep 04 02:06:27 AM UTC 24 Sep 04 02:07:01 AM UTC 24 4097591320 ps
T196 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_alert_test.805090731 Sep 04 02:06:49 AM UTC 24 Sep 04 02:07:02 AM UTC 24 639566193 ps
T197 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_kmac_err_chk.4207367418 Sep 04 02:06:37 AM UTC 24 Sep 04 02:07:06 AM UTC 24 339780225 ps
T198 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_alert_test.1355237803 Sep 04 02:06:55 AM UTC 24 Sep 04 02:07:09 AM UTC 24 1844664262 ps
T199 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_max_throughput_chk.782736078 Sep 04 02:06:52 AM UTC 24 Sep 04 02:07:09 AM UTC 24 2855785462 ps
T200 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all.3001453047 Sep 04 02:06:31 AM UTC 24 Sep 04 02:07:11 AM UTC 24 2004411002 ps
T201 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_max_throughput_chk.2126081505 Sep 04 02:07:02 AM UTC 24 Sep 04 02:07:19 AM UTC 24 356635329 ps
T202 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all.2123268078 Sep 04 02:06:50 AM UTC 24 Sep 04 02:07:21 AM UTC 24 388006864 ps
T203 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.631071837 Sep 04 02:05:19 AM UTC 24 Sep 04 02:07:25 AM UTC 24 3003026476 ps
T204 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_alert_test.659111021 Sep 04 02:07:10 AM UTC 24 Sep 04 02:07:25 AM UTC 24 990555099 ps
T25 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.3994841351 Sep 04 02:05:00 AM UTC 24 Sep 04 02:07:27 AM UTC 24 4889648369 ps
T205 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_max_throughput_chk.3578937966 Sep 04 02:07:12 AM UTC 24 Sep 04 02:07:28 AM UTC 24 187068654 ps
T206 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_kmac_err_chk.3907051241 Sep 04 02:06:53 AM UTC 24 Sep 04 02:07:29 AM UTC 24 6187863688 ps
T207 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_kmac_err_chk.507333291 Sep 04 02:07:03 AM UTC 24 Sep 04 02:07:30 AM UTC 24 1319917297 ps
T208 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_kmac_err_chk.3158573212 Sep 04 02:06:47 AM UTC 24 Sep 04 02:07:33 AM UTC 24 7857948348 ps
T209 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.1878770715 Sep 04 02:06:47 AM UTC 24 Sep 04 02:07:35 AM UTC 24 3473596964 ps
T210 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.2382613262 Sep 04 02:04:30 AM UTC 24 Sep 04 02:07:36 AM UTC 24 3120438646 ps
T211 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_alert_test.4066668222 Sep 04 02:07:26 AM UTC 24 Sep 04 02:07:39 AM UTC 24 990355079 ps
T212 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.1744647346 Sep 04 02:05:00 AM UTC 24 Sep 04 02:07:40 AM UTC 24 12769936216 ps
T146 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.176416439 Sep 04 02:04:48 AM UTC 24 Sep 04 02:07:41 AM UTC 24 2976701662 ps
T213 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all.447392958 Sep 04 02:07:00 AM UTC 24 Sep 04 02:07:44 AM UTC 24 836965095 ps
T53 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3766235318 Sep 04 02:04:29 AM UTC 24 Sep 04 02:07:46 AM UTC 24 3743150684 ps
T214 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_alert_test.2451182135 Sep 04 02:07:36 AM UTC 24 Sep 04 02:07:46 AM UTC 24 687608905 ps
T215 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_max_throughput_chk.3282657245 Sep 04 02:07:28 AM UTC 24 Sep 04 02:07:47 AM UTC 24 2848877560 ps
T216 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.3327250126 Sep 04 02:06:20 AM UTC 24 Sep 04 02:07:47 AM UTC 24 4269630878 ps
T217 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.524831934 Sep 04 02:06:13 AM UTC 24 Sep 04 02:07:49 AM UTC 24 5331371374 ps
T38 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.2704203504 Sep 04 02:04:02 AM UTC 24 Sep 04 02:07:54 AM UTC 24 7181942374 ps
T218 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_kmac_err_chk.1422486746 Sep 04 02:07:32 AM UTC 24 Sep 04 02:07:55 AM UTC 24 507083530 ps
T219 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all.1391330321 Sep 04 02:07:10 AM UTC 24 Sep 04 02:07:55 AM UTC 24 386850267 ps
T220 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_alert_test.296534982 Sep 04 02:07:46 AM UTC 24 Sep 04 02:07:55 AM UTC 24 1272087286 ps
T221 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_max_throughput_chk.2954447706 Sep 04 02:07:40 AM UTC 24 Sep 04 02:07:56 AM UTC 24 731188404 ps
T222 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_kmac_err_chk.229204152 Sep 04 02:07:22 AM UTC 24 Sep 04 02:07:57 AM UTC 24 518014877 ps
T223 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.491427742 Sep 04 02:06:30 AM UTC 24 Sep 04 02:07:57 AM UTC 24 9237971451 ps
T56 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.3023386126 Sep 04 02:05:26 AM UTC 24 Sep 04 02:07:59 AM UTC 24 2498791322 ps
T224 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all.2028129540 Sep 04 02:07:47 AM UTC 24 Sep 04 02:08:00 AM UTC 24 1033475565 ps
T225 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_max_throughput_chk.2235692422 Sep 04 02:07:48 AM UTC 24 Sep 04 02:08:01 AM UTC 24 510443278 ps
T226 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.2468393408 Sep 04 02:07:26 AM UTC 24 Sep 04 02:08:06 AM UTC 24 3180754419 ps
T227 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_kmac_err_chk.1740286451 Sep 04 02:07:42 AM UTC 24 Sep 04 02:08:06 AM UTC 24 1051216042 ps
T228 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_alert_test.325985348 Sep 04 02:07:56 AM UTC 24 Sep 04 02:08:07 AM UTC 24 969962973 ps
T229 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_max_throughput_chk.2796949568 Sep 04 02:07:57 AM UTC 24 Sep 04 02:08:08 AM UTC 24 188061462 ps
T230 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all.1873120209 Sep 04 02:07:37 AM UTC 24 Sep 04 02:08:09 AM UTC 24 1876178863 ps
T39 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2212751796 Sep 04 02:03:51 AM UTC 24 Sep 04 02:08:09 AM UTC 24 27479751601 ps
T231 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_kmac_err_chk.3254332371 Sep 04 02:07:49 AM UTC 24 Sep 04 02:08:10 AM UTC 24 333250433 ps
T232 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.3048283287 Sep 04 02:06:39 AM UTC 24 Sep 04 02:08:11 AM UTC 24 6352578958 ps
T233 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_alert_test.3530480378 Sep 04 02:07:59 AM UTC 24 Sep 04 02:08:12 AM UTC 24 977938373 ps
T234 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.3795345017 Sep 04 02:06:54 AM UTC 24 Sep 04 02:08:13 AM UTC 24 8988378499 ps
T235 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all.1666928504 Sep 04 02:07:27 AM UTC 24 Sep 04 02:08:15 AM UTC 24 5863571639 ps
T236 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.3297425261 Sep 04 02:04:52 AM UTC 24 Sep 04 02:08:15 AM UTC 24 8420592998 ps
T40 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.788204579 Sep 04 02:04:52 AM UTC 24 Sep 04 02:08:16 AM UTC 24 3139340044 ps
T237 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_kmac_err_chk.4011982910 Sep 04 02:07:58 AM UTC 24 Sep 04 02:08:19 AM UTC 24 346308856 ps
T238 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_max_throughput_chk.1462500519 Sep 04 02:08:01 AM UTC 24 Sep 04 02:08:19 AM UTC 24 712840559 ps
T239 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_stress_all.3745771130 Sep 04 02:08:00 AM UTC 24 Sep 04 02:08:20 AM UTC 24 788645353 ps
T240 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_alert_test.2849055652 Sep 04 02:08:08 AM UTC 24 Sep 04 02:08:20 AM UTC 24 514524982 ps
T241 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all.1435104248 Sep 04 02:07:56 AM UTC 24 Sep 04 02:08:21 AM UTC 24 987914872 ps
T242 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_max_throughput_chk.1772711119 Sep 04 02:08:10 AM UTC 24 Sep 04 02:08:27 AM UTC 24 265015249 ps
T243 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_alert_test.1073022693 Sep 04 02:08:13 AM UTC 24 Sep 04 02:08:28 AM UTC 24 518750826 ps
T244 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.161000133 Sep 04 02:05:34 AM UTC 24 Sep 04 02:08:28 AM UTC 24 12310925127 ps
T245 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_kmac_err_chk.3237918313 Sep 04 02:08:06 AM UTC 24 Sep 04 02:08:31 AM UTC 24 2248132661 ps
T246 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_alert_test.1665760347 Sep 04 02:08:19 AM UTC 24 Sep 04 02:08:33 AM UTC 24 718473143 ps
T247 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_max_throughput_chk.959054483 Sep 04 02:08:15 AM UTC 24 Sep 04 02:08:33 AM UTC 24 257457172 ps
T248 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all.4000726939 Sep 04 02:08:14 AM UTC 24 Sep 04 02:08:36 AM UTC 24 3122906306 ps
T249 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_kmac_err_chk.1303393328 Sep 04 02:08:11 AM UTC 24 Sep 04 02:08:38 AM UTC 24 333941164 ps
T250 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_max_throughput_chk.2370905737 Sep 04 02:08:20 AM UTC 24 Sep 04 02:08:39 AM UTC 24 543579593 ps
T41 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.167616530 Sep 04 02:04:24 AM UTC 24 Sep 04 02:08:40 AM UTC 24 20181153774 ps
T251 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_alert_test.3305174403 Sep 04 02:08:28 AM UTC 24 Sep 04 02:08:41 AM UTC 24 332980561 ps
T252 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_max_throughput_chk.1583437445 Sep 04 02:08:29 AM UTC 24 Sep 04 02:08:45 AM UTC 24 1024616338 ps
T253 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_kmac_err_chk.1685458643 Sep 04 02:08:16 AM UTC 24 Sep 04 02:08:47 AM UTC 24 343471176 ps
T254 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all.1272594654 Sep 04 02:08:10 AM UTC 24 Sep 04 02:08:49 AM UTC 24 769928386 ps
T255 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.1209054264 Sep 04 02:07:34 AM UTC 24 Sep 04 02:08:49 AM UTC 24 4759727171 ps
T256 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.3719550412 Sep 04 02:05:45 AM UTC 24 Sep 04 02:08:49 AM UTC 24 2704282075 ps
T257 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_kmac_err_chk.711783894 Sep 04 02:08:23 AM UTC 24 Sep 04 02:08:49 AM UTC 24 502261968 ps
T258 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_alert_test.2356406395 Sep 04 02:08:37 AM UTC 24 Sep 04 02:08:52 AM UTC 24 1032803777 ps
T259 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_max_throughput_chk.1251908813 Sep 04 02:08:40 AM UTC 24 Sep 04 02:08:56 AM UTC 24 179613068 ps
T42 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.3700690391 Sep 04 02:04:33 AM UTC 24 Sep 04 02:08:58 AM UTC 24 5490411301 ps
T260 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all.2972113002 Sep 04 02:08:29 AM UTC 24 Sep 04 02:09:00 AM UTC 24 1074925565 ps
T261 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_kmac_err_chk.1470510886 Sep 04 02:08:34 AM UTC 24 Sep 04 02:09:00 AM UTC 24 1380505236 ps
T262 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_alert_test.3922984201 Sep 04 02:08:48 AM UTC 24 Sep 04 02:09:01 AM UTC 24 175488234 ps
T36 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_sec_cm.2508054566 Sep 04 02:04:01 AM UTC 24 Sep 04 02:09:01 AM UTC 24 1166103106 ps
T47 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.4290342248 Sep 04 02:04:37 AM UTC 24 Sep 04 02:09:02 AM UTC 24 22040904850 ps
T263 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_max_throughput_chk.724858879 Sep 04 02:08:51 AM UTC 24 Sep 04 02:09:05 AM UTC 24 179979408 ps
T264 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.2177111577 Sep 04 02:04:48 AM UTC 24 Sep 04 02:09:06 AM UTC 24 78496010679 ps
T265 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.3722957014 Sep 04 02:07:07 AM UTC 24 Sep 04 02:09:07 AM UTC 24 2259874790 ps
T266 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_kmac_err_chk.605841957 Sep 04 02:08:42 AM UTC 24 Sep 04 02:09:10 AM UTC 24 2067184758 ps
T267 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_alert_test.4181340162 Sep 04 02:08:57 AM UTC 24 Sep 04 02:09:11 AM UTC 24 362556114 ps
T268 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_alert_test.779215272 Sep 04 02:09:03 AM UTC 24 Sep 04 02:09:16 AM UTC 24 197215175 ps
T269 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.1765658946 Sep 04 02:05:33 AM UTC 24 Sep 04 02:09:16 AM UTC 24 17061694012 ps
T270 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_kmac_err_chk.1024070243 Sep 04 02:08:51 AM UTC 24 Sep 04 02:09:16 AM UTC 24 347803867 ps
T271 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_max_throughput_chk.1513480704 Sep 04 02:09:00 AM UTC 24 Sep 04 02:09:19 AM UTC 24 1982752660 ps
T272 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all.967242108 Sep 04 02:08:59 AM UTC 24 Sep 04 02:09:21 AM UTC 24 374341258 ps
T273 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all.2236409312 Sep 04 02:08:38 AM UTC 24 Sep 04 02:09:21 AM UTC 24 9207395631 ps
T274 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.106445473 Sep 04 02:07:58 AM UTC 24 Sep 04 02:09:23 AM UTC 24 6721806791 ps
T275 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_max_throughput_chk.4207589534 Sep 04 02:09:07 AM UTC 24 Sep 04 02:09:23 AM UTC 24 179627355 ps
T276 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_kmac_err_chk.1189006813 Sep 04 02:09:02 AM UTC 24 Sep 04 02:09:25 AM UTC 24 2755350766 ps
T277 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_kmac_err_chk.1214398674 Sep 04 02:09:22 AM UTC 24 Sep 04 02:09:55 AM UTC 24 7890642311 ps
T278 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all.1804653338 Sep 04 02:08:19 AM UTC 24 Sep 04 02:09:25 AM UTC 24 1072953994 ps
T279 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.3749399187 Sep 04 02:06:45 AM UTC 24 Sep 04 02:09:25 AM UTC 24 10136528849 ps
T54 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.4005546053 Sep 04 02:04:01 AM UTC 24 Sep 04 02:09:26 AM UTC 24 18187487695 ps
T280 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_alert_test.2333171587 Sep 04 02:09:17 AM UTC 24 Sep 04 02:09:30 AM UTC 24 185787989 ps
T281 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all.3227011325 Sep 04 02:08:50 AM UTC 24 Sep 04 02:09:30 AM UTC 24 796037055 ps
T282 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_max_throughput_chk.2749140919 Sep 04 02:09:17 AM UTC 24 Sep 04 02:09:32 AM UTC 24 1365313521 ps
T283 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_kmac_err_chk.1352915179 Sep 04 02:09:11 AM UTC 24 Sep 04 02:09:33 AM UTC 24 6627462548 ps
T284 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.2490807397 Sep 04 02:05:56 AM UTC 24 Sep 04 02:09:33 AM UTC 24 9445567941 ps
T285 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_alert_test.1333715414 Sep 04 02:09:23 AM UTC 24 Sep 04 02:09:37 AM UTC 24 254676020 ps
T286 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_alert_test.3394164743 Sep 04 02:09:27 AM UTC 24 Sep 04 02:09:38 AM UTC 24 688924186 ps
T287 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2007332405 Sep 04 02:04:02 AM UTC 24 Sep 04 02:09:39 AM UTC 24 4204755211 ps
T288 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_max_throughput_chk.2239131056 Sep 04 02:09:25 AM UTC 24 Sep 04 02:09:44 AM UTC 24 553021449 ps
T289 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.4030131317 Sep 04 02:04:01 AM UTC 24 Sep 04 02:09:45 AM UTC 24 21529295910 ps
T290 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_max_throughput_chk.1252172159 Sep 04 02:09:31 AM UTC 24 Sep 04 02:09:48 AM UTC 24 715428303 ps
T291 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all.4126210468 Sep 04 02:09:17 AM UTC 24 Sep 04 02:09:49 AM UTC 24 1030173101 ps
T292 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.1694331294 Sep 04 02:07:48 AM UTC 24 Sep 04 02:09:50 AM UTC 24 1387393699 ps
T293 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all.3299190137 Sep 04 02:09:24 AM UTC 24 Sep 04 02:09:51 AM UTC 24 281091636 ps
T294 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2283344477 Sep 04 02:05:05 AM UTC 24 Sep 04 02:09:52 AM UTC 24 15060851773 ps
T295 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_alert_test.2250459218 Sep 04 02:09:38 AM UTC 24 Sep 04 02:09:53 AM UTC 24 881880292 ps
T108 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_max_throughput_chk.2476083223 Sep 04 02:09:39 AM UTC 24 Sep 04 02:09:57 AM UTC 24 260354729 ps
T109 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_kmac_err_chk.1777315678 Sep 04 02:09:26 AM UTC 24 Sep 04 02:10:00 AM UTC 24 2360460220 ps
T110 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all.3552555499 Sep 04 02:09:05 AM UTC 24 Sep 04 02:10:02 AM UTC 24 2105182285 ps
T111 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_kmac_err_chk.2067546233 Sep 04 02:09:34 AM UTC 24 Sep 04 02:10:02 AM UTC 24 502481806 ps
T112 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.1633201335 Sep 04 02:09:12 AM UTC 24 Sep 04 02:10:03 AM UTC 24 966044549 ps
T113 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_max_throughput_chk.3147478589 Sep 04 02:09:53 AM UTC 24 Sep 04 02:10:04 AM UTC 24 190120807 ps
T114 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_alert_test.1817242742 Sep 04 02:09:50 AM UTC 24 Sep 04 02:10:05 AM UTC 24 249411106 ps
T115 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.2947194446 Sep 04 02:08:25 AM UTC 24 Sep 04 02:10:06 AM UTC 24 7501447950 ps
T116 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_alert_test.3779917347 Sep 04 02:09:56 AM UTC 24 Sep 04 02:10:08 AM UTC 24 1027288510 ps
T48 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.1107380284 Sep 04 02:06:37 AM UTC 24 Sep 04 02:10:13 AM UTC 24 3051944737 ps
T296 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all.3692443717 Sep 04 02:09:38 AM UTC 24 Sep 04 02:10:13 AM UTC 24 1298153087 ps
T297 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_max_throughput_chk.2409193526 Sep 04 02:10:01 AM UTC 24 Sep 04 02:10:15 AM UTC 24 998459321 ps
T298 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2947171558 Sep 04 02:06:53 AM UTC 24 Sep 04 02:10:15 AM UTC 24 25515649179 ps
T299 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_kmac_err_chk.2122868530 Sep 04 02:09:46 AM UTC 24 Sep 04 02:10:16 AM UTC 24 993228702 ps
T300 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_kmac_err_chk.1190143858 Sep 04 02:09:53 AM UTC 24 Sep 04 02:10:19 AM UTC 24 2753256220 ps
T49 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_alert_test.1000611009 Sep 04 02:10:04 AM UTC 24 Sep 04 02:10:20 AM UTC 24 4954723531 ps
T301 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_kmac_err_chk.826649300 Sep 04 02:10:03 AM UTC 24 Sep 04 02:10:22 AM UTC 24 1374129711 ps
T302 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.1067134884 Sep 04 02:09:22 AM UTC 24 Sep 04 02:10:23 AM UTC 24 7243550445 ps
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