Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

424721

1

T1

59

T3

28

T4

48

full_word

263996

1

T1

5

T3

6

T4

2

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	688417	1			T1	64		T3	34		T4	50
auto[TlIntgErrCmd]	102	1			T58	2		T59	1		T60	2
auto[TlIntgErrData]	96	1			T58	5		T59	2		T60	5
auto[TlIntgErrBoth]	102	1			T58	3		T59	7		T60	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

125726

1

T1

64

T3

34

T4

50

auto[1]

562991

1

T11

1897

T12

754

T13

8924

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	61698	1			T1	59		T3	28		T4	48
auto[TlIntgErrNone]	partial	auto[1]	362744	1			T11	1191		T12	422		T13	5596
auto[TlIntgErrNone]	full_word	auto[0]	63897	1			T1	5		T3	6		T4	2
auto[TlIntgErrNone]	full_word	auto[1]	200078	1			T11	706		T12	332		T13	3328
auto[TlIntgErrCmd]	partial	auto[0]	42	1			T58	1		T59	1		T60	1
auto[TlIntgErrCmd]	partial	auto[1]	52	1			T58	1		T102	2		T103	4
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T60	1		T109	1		T113	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T114	1		T112	2		T107	1
auto[TlIntgErrData]	partial	auto[0]	44	1			T58	3		T59	1		T60	3
auto[TlIntgErrData]	partial	auto[1]	47	1			T58	2		T59	1		T60	2
auto[TlIntgErrData]	full_word	auto[0]	4	1			T109	1		T110	1		T113	1
auto[TlIntgErrData]	full_word	auto[1]	1	1			T115	1		-	-		-	-
auto[TlIntgErrBoth]	partial	auto[0]	34	1			T58	2		T59	2		T60	1
auto[TlIntgErrBoth]	partial	auto[1]	60	1			T58	1		T59	5		T60	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T106	1		T116	1		T117	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T60	1		T102	1		T114	1