Line Coverage for Module :
prim_subst_perm
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 35 | 1 | 1 | 100.00 |
ALWAYS | 64 | 10 | 10 | 100.00 |
ALWAYS | 64 | 10 | 10 | 100.00 |
CONT_ASSIGN | 90 | 1 | 1 | 100.00 |
34 // initialize
35 1/1 assign data_state[0] = data_i;
Tests: T1 T2 T3
36
37 for (genvar r = 0; r < NumRounds; r++) begin : gen_round
38 logic [DataWidth-1:0] data_state_sbox, data_state_flipped;
39 ////////////////////////////////
40 // decryption pass, performs inverse permutation and sbox
41 if (Decrypt) begin : gen_dec
42 always_comb begin : p_dec
43 data_state_sbox = data_state[r] ^ key_i;
44 // Reverse odd/even grouping
45 data_state_flipped = data_state_sbox;
46 for (int k = 0; k < DataWidth/2; k++) begin
47 data_state_flipped[k * 2] = data_state_sbox[k];
48 data_state_flipped[k * 2 + 1] = data_state_sbox[k + DataWidth/2];
49 end
50 // Flip vector
51 for (int k = 0; k < DataWidth; k++) begin
52 data_state_sbox[DataWidth - 1 - k] = data_state_flipped[k];
53 end
54 // Inverse SBox layer
55 for (int k = 0; k < DataWidth/4; k++) begin
56 data_state_sbox[k*4 +: 4] = prim_cipher_pkg::PRESENT_SBOX4_INV[data_state_sbox[k*4 +: 4]];
57 end
58 data_state[r + 1] = data_state_sbox;
59 end
60 ////////////////////////////////
61 // encryption pass
62 end else begin : gen_enc
63 always_comb begin : p_enc
64 1/1 data_state_sbox = data_state[r] ^ key_i;
Tests: T1 T2 T3
65 // This SBox layer is aligned to nibbles, so the uppermost bits may not be affected by this.
66 // However, the permutation below ensures that these bits get shuffled to a different
67 // position when performing multiple rounds.
68 1/1 for (int k = 0; k < DataWidth/4; k++) begin
Tests: T1 T2 T3
69 1/1 data_state_sbox[k*4 +: 4] = prim_cipher_pkg::PRESENT_SBOX4[data_state_sbox[k*4 +: 4]];
Tests: T1 T2 T3
70 end
71 // Flip the vector to move the MSB positions into the LSB positions
72 1/1 for (int k = 0; k < DataWidth; k++) begin
Tests: T1 T2 T3
73 1/1 data_state_flipped[DataWidth - 1 - k] = data_state_sbox[k];
Tests: T1 T2 T3
74 end
75 // Regroup bits such that all even indices are stacked up first, followed by all odd
76 // indices. Note that if the Width is odd, this is still ok, since
77 // the uppermost bit just stays in place in that case.
78 1/1 data_state_sbox = data_state_flipped;
Tests: T1 T2 T3
79 1/1 for (int k = 0; k < DataWidth/2; k++) begin
Tests: T1 T2 T3
80 1/1 data_state_sbox[k] = data_state_flipped[k * 2];
Tests: T1 T2 T3
81 1/1 data_state_sbox[k + DataWidth/2] = data_state_flipped[k * 2 + 1];
Tests: T1 T2 T3
82 end
83 1/1 data_state[r + 1] = data_state_sbox;
Tests: T1 T2 T3
***repeat 1
64 1/1 data_state_sbox = data_state[r] ^ key_i;
Tests: T1 T2 T3
65 // This SBox layer is aligned to nibbles, so the uppermost bits may not be affected by this.
66 // However, the permutation below ensures that these bits get shuffled to a different
67 // position when performing multiple rounds.
68 1/1 for (int k = 0; k < DataWidth/4; k++) begin
Tests: T1 T2 T3
69 1/1 data_state_sbox[k*4 +: 4] = prim_cipher_pkg::PRESENT_SBOX4[data_state_sbox[k*4 +: 4]];
Tests: T1 T2 T3
70 end
71 // Flip the vector to move the MSB positions into the LSB positions
72 1/1 for (int k = 0; k < DataWidth; k++) begin
Tests: T1 T2 T3
73 1/1 data_state_flipped[DataWidth - 1 - k] = data_state_sbox[k];
Tests: T1 T2 T3
74 end
75 // Regroup bits such that all even indices are stacked up first, followed by all odd
76 // indices. Note that if the Width is odd, this is still ok, since
77 // the uppermost bit just stays in place in that case.
78 1/1 data_state_sbox = data_state_flipped;
Tests: T1 T2 T3
79 1/1 for (int k = 0; k < DataWidth/2; k++) begin
Tests: T1 T2 T3
80 1/1 data_state_sbox[k] = data_state_flipped[k * 2];
Tests: T1 T2 T3
81 1/1 data_state_sbox[k + DataWidth/2] = data_state_flipped[k * 2 + 1];
Tests: T1 T2 T3
82 end
83 1/1 data_state[r + 1] = data_state_sbox;
Tests: T1 T2 T3
84 end
85 end // gen_enc
86 ////////////////////////////////
87 end // gen_round
88
89 // finalize
90 1/1 assign data_o = data_state[NumRounds] ^ key_i;
Tests: T1 T2 T3