Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_64kB-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

511234

1

T1

187

T3

19

T4

23

full_word

312513

1

T1

28

T3

1

T6

3

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	823477	1			T1	215		T3	20		T4	23
auto[TlIntgErrCmd]	82	1			T75	2		T76	5		T77	3
auto[TlIntgErrData]	103	1			T75	4		T76	2		T77	2
auto[TlIntgErrBoth]	85	1			T75	4		T76	3		T77	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

152139

1

T1

215

T3

20

T4

23

auto[1]

671608

1

T14

7031

T15

5172

T16

5991

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrCmd]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	75961	1			T1	187		T3	19		T4	23
auto[TlIntgErrNone]	partial	auto[1]	435021	1			T14	4354		T15	3822		T16	3831
auto[TlIntgErrNone]	full_word	auto[0]	76050	1			T1	28		T3	1		T6	3
auto[TlIntgErrNone]	full_word	auto[1]	236445	1			T14	2677		T15	1350		T16	2160
auto[TlIntgErrCmd]	partial	auto[0]	31	1			T76	3		T77	1		T131	1
auto[TlIntgErrCmd]	partial	auto[1]	46	1			T75	2		T76	2		T77	2
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T132	1		T133	2		T134	1
auto[TlIntgErrData]	partial	auto[0]	54	1			T75	2		T131	4		T135	3
auto[TlIntgErrData]	partial	auto[1]	41	1			T75	2		T76	2		T77	2
auto[TlIntgErrData]	full_word	auto[0]	4	1			T135	2		T136	1		T137	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T138	1		T134	1		T136	1
auto[TlIntgErrBoth]	partial	auto[0]	38	1			T75	1		T77	1		T131	2
auto[TlIntgErrBoth]	partial	auto[1]	42	1			T75	1		T76	3		T77	4
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T136	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T75	2		T136	1		T139	1