Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.gen_fsm_scramble_enabled.u_checker_fsm.u_counter

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.67 100.00 96.36 100.00 96.97 100.00 gen_fsm_scramble_enabled.u_checker_fsm


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : rom_ctrl_counter
Line No.TotalCoveredPercent
TOTAL2323100.00
CONT_ASSIGN7411100.00
ALWAYS7633100.00
ALWAYS8466100.00
ALWAYS9455100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN11111100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11411100.00
CONT_ASSIGN11511100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN11711100.00

73 74 1/1 assign done_d = addr_q == TopAddr; Tests: T1 T2 T3  75 always_ff @(posedge clk_i or negedge rst_ni) begin 76 1/1 if (!rst_ni) begin Tests: T1 T2 T3  77 1/1 done_q <= 1'b0; Tests: T1 T2 T3  78 end else begin 79 1/1 done_q <= done_d; Tests: T1 T2 T3  80 end 81 end 82 83 always_ff @(posedge clk_i or negedge rst_ni) begin 84 1/1 if (!rst_ni) begin Tests: T1 T2 T3  85 1/1 addr_q <= '0; Tests: T1 T2 T3  86 1/1 last_nontop_q <= 1'b0; Tests: T1 T2 T3  87 1/1 end else if (go) begin Tests: T1 T2 T3  88 1/1 addr_q <= addr_d; Tests: T1 T2 T3  89 1/1 last_nontop_q <= last_nontop_d; Tests: T1 T2 T3  90 end MISSING_ELSE 91 end 92 93 always_ff @(posedge clk_i or negedge rst_ni) begin 94 1/1 if (!rst_ni) begin Tests: T1 T2 T3  95 1/1 req_q <= 1'b0; Tests: T1 T2 T3  96 1/1 vld_q <= 1'b0; Tests: T1 T2 T3  97 end else begin 98 // The first ROM request goes out immediately after reset (once we reach the top of ROM, we 99 // signal done_o, after which the request signal is unused). We could clear it again when we 100 // are done, but there's no need: the mux will switch away from us anyway. 101 1/1 req_q <= 1'b1; Tests: T1 T2 T3  102 103 // ROM data is valid from one cycle after the request goes out. 104 1/1 vld_q <= req_q; Tests: T1 T2 T3  105 end 106 end 107 108 1/1 assign go = data_rdy_i & vld_q & ~done_d; Tests: T1 T2 T3  109 110 1/1 assign addr_d = addr_q + {{AW-1{1'b0}}, 1'b1}; Tests: T1 T2 T3  111 1/1 assign last_nontop_d = addr_q == TNTAddr; Tests: T1 T2 T3  112 113 1/1 assign done_o = done_q; Tests: T1 T2 T3  114 1/1 assign read_addr_o = go ? addr_d : addr_q; Tests: T1 T2 T3  115 1/1 assign read_req_o = req_q; Tests: T1 T2 T3  116 1/1 assign data_addr_o = addr_q; Tests: T1 T2 T3  117 1/1 assign data_last_nontop_o = last_nontop_q; Tests: T1 T2 T3 

Cond Coverage for Module : rom_ctrl_counter
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (addr_q == TopAddr)
            ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       108
 EXPRESSION (data_rdy_i & vld_q & ((~done_d)))
             -----1----   --2--   -----3-----
-1--2--3-StatusTests
011CoveredT2,T3,T4
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       111
 EXPRESSION (addr_q == TNTAddr)
            ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       114
 EXPRESSION (go ? addr_d : addr_q)
             -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Module : rom_ctrl_counter
Line No.TotalCoveredPercent
Branches 9 9 100.00
TERNARY 114 2 2 100.00
IF 76 2 2 100.00
IF 84 3 3 100.00
IF 94 2 2 100.00


114 assign read_addr_o = go ? addr_d : addr_q; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


76 if (!rst_ni) begin -1- 77 done_q <= 1'b0; ==> 78 end else begin 79 done_q <= done_d; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


84 if (!rst_ni) begin -1- 85 addr_q <= '0; ==> 86 last_nontop_q <= 1'b0; 87 end else if (go) begin -2- 88 addr_q <= addr_d; ==> 89 last_nontop_q <= last_nontop_d; 90 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


94 if (!rst_ni) begin -1- 95 req_q <= 1'b0; ==> 96 vld_q <= 1'b0; 97 end else begin 98 // The first ROM request goes out immediately after reset (once we reach the top of ROM, we 99 // signal done_o, after which the request signal is unused). We could clear it again when we 100 // are done, but there's no need: the mux will switch away from us anyway. 101 req_q <= 1'b1; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : rom_ctrl_counter
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NonTopCountValid_A 313 313 0 0
TopCountValid_A 313 313 0 0


NonTopCountValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 313 313 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

TopCountValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 313 313 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%