Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_64kB-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

499041

1

T5

28

T6

144

T7

86

full_word

313034

1

T5

4

T6

17

T7

8

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	811765	1			T5	32		T6	161		T7	94
auto[TlIntgErrCmd]	99	1			T91	2		T92	2		T93	1
auto[TlIntgErrData]	110	1			T91	6		T92	4		T93	5
auto[TlIntgErrBoth]	101	1			T91	2		T92	4		T93	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

147514

1

T5

32

T6

161

T7

94

auto[1]

664561

1

T14

905

T15

4708

T16

3697

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	71292	1			T5	28		T6	144		T7	86
auto[TlIntgErrNone]	partial	auto[1]	427464	1			T14	612		T15	2768		T16	2136
auto[TlIntgErrNone]	full_word	auto[0]	76078	1			T5	4		T6	17		T7	8
auto[TlIntgErrNone]	full_word	auto[1]	236931	1			T14	293		T15	1940		T16	1561
auto[TlIntgErrCmd]	partial	auto[0]	42	1			T91	1		T92	1		T136	2
auto[TlIntgErrCmd]	partial	auto[1]	48	1			T91	1		T92	1		T93	1
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T138	1		T145	1		T146	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T138	1		T142	1		T139	1
auto[TlIntgErrData]	partial	auto[0]	55	1			T91	3		T92	2		T93	1
auto[TlIntgErrData]	partial	auto[1]	47	1			T91	3		T92	1		T93	4
auto[TlIntgErrData]	full_word	auto[0]	3	1			T147	1		T141	1		T142	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T92	1		T137	1		T141	1
auto[TlIntgErrBoth]	partial	auto[0]	35	1			T93	1		T136	3		T137	1
auto[TlIntgErrBoth]	partial	auto[1]	58	1			T91	2		T92	3		T93	2
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T93	1		T136	1		T137	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T92	1		T148	1		T149	1