Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_64kB-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

463230

1

T4

76

T5

24

T7

20

full_word

288647

1

T4

7

T5

1

T7

4

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	751567	1			T4	83		T5	25		T7	24
auto[TlIntgErrCmd]	100	1			T87	4		T88	3		T89	4
auto[TlIntgErrData]	107	1			T87	1		T88	3		T89	4
auto[TlIntgErrBoth]	103	1			T87	5		T88	4		T89	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

138508

1

T4

83

T5

25

T7

24

auto[1]

613369

1

T13

2449

T14

870

T15

5295

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	68337	1			T4	76		T5	24		T7	20
auto[TlIntgErrNone]	partial	auto[1]	394619	1			T13	1816		T14	597		T15	3309
auto[TlIntgErrNone]	full_word	auto[0]	70034	1			T4	7		T5	1		T7	4
auto[TlIntgErrNone]	full_word	auto[1]	218577	1			T13	633		T14	273		T15	1986
auto[TlIntgErrCmd]	partial	auto[0]	36	1			T87	2		T88	1		T89	2
auto[TlIntgErrCmd]	partial	auto[1]	54	1			T87	2		T88	2		T89	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T139	2		T140	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T135	1		T133	1		T141	1
auto[TlIntgErrData]	partial	auto[0]	47	1			T88	1		T89	2		T130	1
auto[TlIntgErrData]	partial	auto[1]	45	1			T87	1		T88	2		T89	2
auto[TlIntgErrData]	full_word	auto[0]	8	1			T130	1		T142	1		T136	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T131	1		T133	2		T141	1
auto[TlIntgErrBoth]	partial	auto[0]	40	1			T87	2		T88	1		T89	1
auto[TlIntgErrBoth]	partial	auto[1]	52	1			T87	3		T88	1		T89	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T142	1		T131	1		T134	1
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T88	2		T135	1		T132	1