Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

496659

1

T3

36

T4

27

T5

297

full_word

306948

1

T4

3

T5

38

T7

21

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	803307	1			T3	36		T4	30		T5	335
auto[TlIntgErrCmd]	112	1			T83	3		T84	3		T85	3
auto[TlIntgErrData]	95	1			T83	3		T84	4		T85	3
auto[TlIntgErrBoth]	93	1			T83	4		T84	3		T85	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

146558

1

T3

36

T4

30

T5

335

auto[1]

657049

1

T14

650

T15

4942

T16

5620

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	72013	1			T3	36		T4	27		T5	297
auto[TlIntgErrNone]	partial	auto[1]	424370	1			T14	357		T15	3042		T16	3709
auto[TlIntgErrNone]	full_word	auto[0]	74414	1			T4	3		T5	38		T7	21
auto[TlIntgErrNone]	full_word	auto[1]	232510	1			T14	293		T15	1900		T16	1911
auto[TlIntgErrCmd]	partial	auto[0]	33	1			T85	2		T134	1		T131	2
auto[TlIntgErrCmd]	partial	auto[1]	72	1			T83	3		T84	3		T85	1
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T129	1		T130	1		T138	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T139	1		T140	1		-	-
auto[TlIntgErrData]	partial	auto[0]	44	1			T83	3		T85	2		T134	3
auto[TlIntgErrData]	partial	auto[1]	41	1			T84	2		T85	1		T134	1
auto[TlIntgErrData]	full_word	auto[0]	7	1			T84	1		T134	1		T132	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T84	1		T137	1		T141	1
auto[TlIntgErrBoth]	partial	auto[0]	38	1			T83	1		T84	1		T85	2
auto[TlIntgErrBoth]	partial	auto[1]	48	1			T83	3		T84	2		T85	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T136	1		T132	1		T142	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T135	2		T141	1		-	-