Unified Coverage Report :: Module :: rom_ctrl_scrambled_rom

Module : rom_ctrl_scrambled_rom

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50	75.00					100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_64kB-sim-vcs/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_scrambled_rom.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_rom_scramble_enabled.u_rom	100.00	100.00					100.00

---

Module Instance : tb.dut.gen_rom_scramble_enabled.u_rom

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	90.91		100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.99	100.00	98.28	97.26		100.00	79.41	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prince	100.00			100.00
u_rom	94.44	83.33				100.00	100.00
u_seed_anchor	0.00	0.00
u_sp_addr	100.00	100.00

Line Coverage for Module : rom_ctrl_scrambled_rom

	Line No.	Total	Covered	Percent
TOTAL		4	3	75.00
CONT_ASSIGN	81	1	0	0.00
CONT_ASSIGN	82	0	0
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
CONT_ASSIGN	153	1	1	100.00

80                        logic [Aw-1:0] addr_scr_nonce;
81         0/1     ==>    assign data_scr_nonce = scr_nonce[63-Aw:0];
82         unreachable    assign addr_scr_nonce = scr_nonce[63-:Aw];
83                      
84                        // Parameter Checks ==========================================================
85                      
86                        // The depth needs to be a power of 2 to use address scrambling
87                        `ASSERT_INIT(DepthPow2Check_A, (Depth & (Depth - 1)) == 0)
88                        // We only support a width up to 64
89                        `ASSERT_INIT(MaxWidthCheck_A, Width <= 64)
90                      
91                        // Address scrambling ========================================================
92                      
93                        logic [Aw-1:0] addr_scr;
94                        prim_subst_perm #(
95                          .DataWidth (Aw),
96                          .NumRounds (2),
97                          .Decrypt   (0)
98                        ) u_sp_addr (
99                          .data_i (rom_addr_i),
100                         .key_i  (addr_scr_nonce),
101                         .data_o (addr_scr)
102                       );
103                     
104                       // Keystream generation ======================================================
105                     
106                       logic [63:0] keystream;
107                     
108                       prim_prince #(
109                         .DataWidth      (64),
110                         .KeyWidth       (128),
111                         .NumRoundsHalf  (3),
112                         .HalfwayDataReg (1'b1),
113                         .HalfwayKeyReg  (1'b1)
114                       ) u_prince (
115                         .clk_i   (clk_i),
116                         .rst_ni  (rst_ni),
117                         .valid_i (req_i),
118                         .data_i  ({data_scr_nonce, prince_addr_i}),
119                         .key_i   (scr_key),
120                         .dec_i   (1'b0),
121                         .data_o  (keystream),
122                         .valid_o ()
123                       );
124                     
125                       if (Width < 64) begin : gen_unread_keystream
126                         // Ignore top bits of keystream: we just use the bottom Width bits.
127                         logic unused_top_keystream;
128        1/1              assign unused_top_keystream = ^keystream[63:Width];
           Tests:       T1 T2 T3 
129                       end
130                     
131                       // The physical ROM ==========================================================
132                     
133                       logic [Width-1:0] rdata_scr;
134                     
135                       prim_rom_adv #(
136                         .Width       (Width),
137                         .Depth       (Depth),
138                         .MemInitFile (MemInitFile)
139                       ) u_rom (
140                         .clk_i    (clk_i),
141                         .rst_ni   (rst_ni),
142                         .req_i    (req_i),
143                         .addr_i   (addr_scr),
144                         .rvalid_o (rvalid_o),
145                         .rdata_o  (rdata_scr),
146                         .cfg_i    (cfg_i)
147                       );
148                     
149        1/1            assign scr_rdata_o = rdata_scr;
           Tests:       T1 T2 T3 
150                     
151                       // XOR rdata with keystream ==================================================
152                     
153        1/1            assign clr_rdata_o = rdata_scr ^ keystream[Width-1:0];
           Tests:       T1 T2 T3 

---

Assert Coverage for Module : rom_ctrl_scrambled_rom

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DepthPow2Check_A	313	313	0	0
MaxWidthCheck_A	313	313	0	0

DepthPow2Check_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313	313	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

MaxWidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313	313	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.gen_rom_scramble_enabled.u_rom

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	81	0	0
CONT_ASSIGN	82	0	0
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
CONT_ASSIGN	153	1	1	100.00

80                        logic [Aw-1:0] addr_scr_nonce;
81         excluded       assign data_scr_nonce = scr_nonce[63-Aw:0];
Exclude Annotation: Waived the continuous assignment block as RHS is a fixed wire
82         unreachable    assign addr_scr_nonce = scr_nonce[63-:Aw];
83                      
84                        // Parameter Checks ==========================================================
85                      
86                        // The depth needs to be a power of 2 to use address scrambling
87                        `ASSERT_INIT(DepthPow2Check_A, (Depth & (Depth - 1)) == 0)
88                        // We only support a width up to 64
89                        `ASSERT_INIT(MaxWidthCheck_A, Width <= 64)
90                      
91                        // Address scrambling ========================================================
92                      
93                        logic [Aw-1:0] addr_scr;
94                        prim_subst_perm #(
95                          .DataWidth (Aw),
96                          .NumRounds (2),
97                          .Decrypt   (0)
98                        ) u_sp_addr (
99                          .data_i (rom_addr_i),
100                         .key_i  (addr_scr_nonce),
101                         .data_o (addr_scr)
102                       );
103                     
104                       // Keystream generation ======================================================
105                     
106                       logic [63:0] keystream;
107                     
108                       prim_prince #(
109                         .DataWidth      (64),
110                         .KeyWidth       (128),
111                         .NumRoundsHalf  (3),
112                         .HalfwayDataReg (1'b1),
113                         .HalfwayKeyReg  (1'b1)
114                       ) u_prince (
115                         .clk_i   (clk_i),
116                         .rst_ni  (rst_ni),
117                         .valid_i (req_i),
118                         .data_i  ({data_scr_nonce, prince_addr_i}),
119                         .key_i   (scr_key),
120                         .dec_i   (1'b0),
121                         .data_o  (keystream),
122                         .valid_o ()
123                       );
124                     
125                       if (Width < 64) begin : gen_unread_keystream
126                         // Ignore top bits of keystream: we just use the bottom Width bits.
127                         logic unused_top_keystream;
128        1/1              assign unused_top_keystream = ^keystream[63:Width];
           Tests:       T1 T2 T3 
129                       end
130                     
131                       // The physical ROM ==========================================================
132                     
133                       logic [Width-1:0] rdata_scr;
134                     
135                       prim_rom_adv #(
136                         .Width       (Width),
137                         .Depth       (Depth),
138                         .MemInitFile (MemInitFile)
139                       ) u_rom (
140                         .clk_i    (clk_i),
141                         .rst_ni   (rst_ni),
142                         .req_i    (req_i),
143                         .addr_i   (addr_scr),
144                         .rvalid_o (rvalid_o),
145                         .rdata_o  (rdata_scr),
146                         .cfg_i    (cfg_i)
147                       );
148                     
149        1/1            assign scr_rdata_o = rdata_scr;
           Tests:       T1 T2 T3 
150                     
151                       // XOR rdata with keystream ==================================================
152                     
153        1/1            assign clr_rdata_o = rdata_scr ^ keystream[Width-1:0];
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.gen_rom_scramble_enabled.u_rom

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DepthPow2Check_A	313	313	0	0
MaxWidthCheck_A	313	313	0	0

DepthPow2Check_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313	313	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

MaxWidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313	313	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0