Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

529818

1

T2

182

T3

19

T5

27

full_word

325510

1

T2

14

T3

3

T5

4

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	854998	1			T2	196		T3	22		T5	31
auto[TlIntgErrCmd]	116	1			T67	3		T68	3		T69	4
auto[TlIntgErrData]	116	1			T67	3		T68	4		T69	1
auto[TlIntgErrBoth]	98	1			T67	4		T68	3		T69	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

155668

1

T2

196

T3

22

T5

31

auto[1]

699660

1

T12

5976

T13

8718

T14

10961

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	76874	1			T2	182		T3	19		T5	27
auto[TlIntgErrNone]	partial	auto[1]	452642	1			T12	3543		T13	5358		T14	7028
auto[TlIntgErrNone]	full_word	auto[0]	78653	1			T2	14		T3	3		T5	4
auto[TlIntgErrNone]	full_word	auto[1]	246829	1			T12	2433		T13	3360		T14	3933
auto[TlIntgErrCmd]	partial	auto[0]	38	1			T67	2		T68	3		T69	3
auto[TlIntgErrCmd]	partial	auto[1]	66	1			T67	1		T117	4		T119	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T124	1		T125	1		T126	1
auto[TlIntgErrCmd]	full_word	auto[1]	9	1			T69	1		T117	1		T127	1
auto[TlIntgErrData]	partial	auto[0]	57	1			T67	2		T117	2		T119	2
auto[TlIntgErrData]	partial	auto[1]	49	1			T67	1		T68	4		T117	1
auto[TlIntgErrData]	full_word	auto[0]	4	1			T118	2		T120	1		T123	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T69	1		T128	1		T129	2
auto[TlIntgErrBoth]	partial	auto[0]	37	1			T67	1		T68	1		T69	2
auto[TlIntgErrBoth]	partial	auto[1]	55	1			T67	3		T68	2		T69	3
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T130	1		T123	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T121	1		T120	1		T128	1