Unified Coverage Report :: Module :: prim_buf

Module : prim_buf

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/sim-vcs/../src/lowrisc_prim_abstract_buf_0/prim_buf.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_tl_rom_h2d_buf
tb.dut.u_reg_regs.u_prim_reg_we_check.u_prim_buf
tb.dut.gen_rom_scramble_enabled.u_rom.u_seed_anchor.u_secure_anchor_buf

---

Module Instance : tb.dut.u_tl_rom_h2d_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.99	100.00	98.28	97.26		100.00	79.41	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00

---

Module Instance : tb.dut.u_reg_regs.u_prim_reg_we_check.u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_reg_we_check

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00

---

Module Instance : tb.dut.gen_rom_scramble_enabled.u_rom.u_seed_anchor.u_secure_anchor_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_seed_anchor

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	0.00	0.00