| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 97.28 | 96.89 | 92.13 | 97.68 | 100.00 | 98.62 | 97.30 | 98.37 |
| T310 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_max_throughput_chk.1942443161 | Feb 08 01:56:18 PM UTC 25 | Feb 08 01:56:36 PM UTC 25 | 261600848 ps | ||
| T311 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all.3170907912 | Feb 08 01:56:17 PM UTC 25 | Feb 08 01:56:40 PM UTC 25 | 349864033 ps | ||
| T312 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_alert_test.1735035159 | Feb 08 01:56:36 PM UTC 25 | Feb 08 01:56:52 PM UTC 25 | 507556670 ps | ||
| T313 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_kmac_err_chk.2414563451 | Feb 08 01:56:32 PM UTC 25 | Feb 08 01:56:52 PM UTC 25 | 396627433 ps | ||
| T314 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_max_throughput_chk.4203938037 | Feb 08 01:56:52 PM UTC 25 | Feb 08 01:57:08 PM UTC 25 | 1747701443 ps | ||
| T315 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all.783631276 | Feb 08 01:56:41 PM UTC 25 | Feb 08 01:57:09 PM UTC 25 | 5776956394 ps | ||
| T316 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_alert_test.1813026155 | Feb 08 01:57:11 PM UTC 25 | Feb 08 01:57:23 PM UTC 25 | 169976736 ps | ||
| T317 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_kmac_err_chk.361994392 | Feb 08 01:57:04 PM UTC 25 | Feb 08 01:57:27 PM UTC 25 | 1706096307 ps | ||
| T318 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.1530482774 | Feb 08 01:53:24 PM UTC 25 | Feb 08 01:58:15 PM UTC 25 | 3563693540 ps | ||
| T319 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.307183373 | Feb 08 01:54:03 PM UTC 25 | Feb 08 01:59:05 PM UTC 25 | 43741235175 ps | ||
| T320 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1491637394 | Feb 08 01:55:41 PM UTC 25 | Feb 08 02:00:16 PM UTC 25 | 4773166619 ps | ||
| T14 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.2155249730 | Feb 08 01:45:24 PM UTC 25 | Feb 08 02:00:58 PM UTC 25 | 53019181753 ps | ||
| T17 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.3114159917 | Feb 08 01:40:37 PM UTC 25 | Feb 08 02:01:08 PM UTC 25 | 125016178812 ps | ||
| T54 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.2226973857 | Feb 08 01:40:53 PM UTC 25 | Feb 08 02:01:31 PM UTC 25 | 31733402561 ps | ||
| T321 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1754231932 | Feb 08 01:56:53 PM UTC 25 | Feb 08 02:01:46 PM UTC 25 | 15815892489 ps | ||
| T322 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.4282061927 | Feb 08 01:54:30 PM UTC 25 | Feb 08 02:01:48 PM UTC 25 | 25845454659 ps | ||
| T323 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.1268790046 | Feb 08 01:55:16 PM UTC 25 | Feb 08 02:01:55 PM UTC 25 | 18401894676 ps | ||
| T324 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.72135248 | Feb 08 01:56:25 PM UTC 25 | Feb 08 02:03:05 PM UTC 25 | 4875987291 ps | ||
| T325 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.575306902 | Feb 08 01:56:04 PM UTC 25 | Feb 08 02:06:27 PM UTC 25 | 32840197646 ps | ||
| T55 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.1855411632 | Feb 08 01:55:43 PM UTC 25 | Feb 08 02:08:52 PM UTC 25 | 19707482577 ps | ||
| T56 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.3652916444 | Feb 08 01:39:26 PM UTC 25 | Feb 08 02:13:25 PM UTC 25 | 43870483097 ps | ||
| T57 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.709098215 | Feb 08 01:52:00 PM UTC 25 | Feb 08 02:14:36 PM UTC 25 | 89843961872 ps | ||
| T58 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.1025267774 | Feb 08 01:44:46 PM UTC 25 | Feb 08 02:26:57 PM UTC 25 | 51380032009 ps | ||
| T59 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.2077265494 | Feb 08 01:42:22 PM UTC 25 | Feb 08 02:31:26 PM UTC 25 | 981678825591 ps | ||
| T326 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.747874692 | Feb 08 01:48:55 PM UTC 25 | Feb 08 02:33:19 PM UTC 25 | 208740816106 ps | ||
| T327 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.1742215966 | Feb 08 01:56:10 PM UTC 25 | Feb 08 02:35:12 PM UTC 25 | 224368428724 ps | ||
| T328 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.220689185 | Feb 08 01:43:29 PM UTC 25 | Feb 08 02:57:22 PM UTC 25 | 25650558764 ps | ||
| T329 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.3608323189 | Feb 08 01:43:18 PM UTC 25 | Feb 08 03:00:36 PM UTC 25 | 103644496888 ps | ||
| T330 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.3494501867 | Feb 08 01:54:13 PM UTC 25 | Feb 08 04:29:55 PM UTC 25 | 20892582983 ps | ||
| T331 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3903277707 | Feb 08 01:57:28 PM UTC 25 | Feb 08 01:57:42 PM UTC 25 | 168600575 ps | ||
| T332 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2607659275 | Feb 08 01:57:43 PM UTC 25 | Feb 08 01:57:59 PM UTC 25 | 989703989 ps | ||
| T333 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1129241651 | Feb 08 01:58:00 PM UTC 25 | Feb 08 01:58:17 PM UTC 25 | 990543564 ps | ||
| T72 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3095836652 | Feb 08 01:57:24 PM UTC 25 | Feb 08 01:58:31 PM UTC 25 | 1596032192 ps | ||
| T73 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_rw.4087578677 | Feb 08 01:58:17 PM UTC 25 | Feb 08 01:58:32 PM UTC 25 | 253181549 ps | ||
| T74 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1776206640 | Feb 08 01:58:15 PM UTC 25 | Feb 08 01:58:32 PM UTC 25 | 2081632455 ps | ||
| T117 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1044057363 | Feb 08 01:58:25 PM UTC 25 | Feb 08 01:58:40 PM UTC 25 | 1766632670 ps | ||
| T334 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.4100586736 | Feb 08 01:58:32 PM UTC 25 | Feb 08 01:58:44 PM UTC 25 | 1975784267 ps | ||
| T82 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.134478133 | Feb 08 01:58:32 PM UTC 25 | Feb 08 01:58:50 PM UTC 25 | 1069942861 ps | ||
| T83 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.306784487 | Feb 08 01:58:32 PM UTC 25 | Feb 08 01:58:51 PM UTC 25 | 705580249 ps | ||
| T335 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_errors.818911234 | Feb 08 01:58:45 PM UTC 25 | Feb 08 01:59:04 PM UTC 25 | 4945179297 ps | ||
| T336 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1697000965 | Feb 08 01:58:52 PM UTC 25 | Feb 08 01:59:04 PM UTC 25 | 174452894 ps | ||
| T337 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2098645042 | Feb 08 01:59:05 PM UTC 25 | Feb 08 01:59:19 PM UTC 25 | 175200731 ps | ||
| T84 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.99946567 | Feb 08 01:59:05 PM UTC 25 | Feb 08 01:59:19 PM UTC 25 | 671228705 ps | ||
| T85 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3718600596 | Feb 08 01:59:06 PM UTC 25 | Feb 08 01:59:21 PM UTC 25 | 338828231 ps | ||
| T338 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1161112683 | Feb 08 01:59:12 PM UTC 25 | Feb 08 01:59:26 PM UTC 25 | 719326383 ps | ||
| T86 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.716631299 | Feb 08 01:59:20 PM UTC 25 | Feb 08 01:59:33 PM UTC 25 | 167509384 ps | ||
| T109 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2238762930 | Feb 08 01:59:20 PM UTC 25 | Feb 08 01:59:35 PM UTC 25 | 1158543462 ps | ||
| T339 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1267304879 | Feb 08 01:59:21 PM UTC 25 | Feb 08 01:59:39 PM UTC 25 | 821010078 ps | ||
| T340 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1426960618 | Feb 08 01:59:34 PM UTC 25 | Feb 08 01:59:45 PM UTC 25 | 167743501 ps | ||
| T341 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1699722111 | Feb 08 01:59:36 PM UTC 25 | Feb 08 01:59:48 PM UTC 25 | 175258469 ps | ||
| T342 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2646144810 | Feb 08 01:59:26 PM UTC 25 | Feb 08 01:59:49 PM UTC 25 | 407224259 ps | ||
| T68 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1083715278 | Feb 08 01:57:41 PM UTC 25 | Feb 08 01:59:50 PM UTC 25 | 2175749225 ps | ||
| T87 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.73776179 | Feb 08 01:59:40 PM UTC 25 | Feb 08 01:59:56 PM UTC 25 | 173868601 ps | ||
| T88 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3738622108 | Feb 08 01:58:41 PM UTC 25 | Feb 08 01:59:58 PM UTC 25 | 3108300456 ps | ||
| T89 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_rw.184351954 | Feb 08 01:59:46 PM UTC 25 | Feb 08 02:00:01 PM UTC 25 | 260536558 ps | ||
| T343 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3582368960 | Feb 08 01:59:49 PM UTC 25 | Feb 08 02:00:05 PM UTC 25 | 345826317 ps | ||
| T344 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.390838522 | Feb 08 01:59:50 PM UTC 25 | Feb 08 02:00:07 PM UTC 25 | 259119955 ps | ||
| T345 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3260047878 | Feb 08 01:59:56 PM UTC 25 | Feb 08 02:00:09 PM UTC 25 | 1056398031 ps | ||
| T110 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.4191259761 | Feb 08 01:59:51 PM UTC 25 | Feb 08 02:00:19 PM UTC 25 | 2019425600 ps | ||
| T94 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3984622134 | Feb 08 01:59:22 PM UTC 25 | Feb 08 02:00:27 PM UTC 25 | 2962013892 ps | ||
| T346 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1483423006 | Feb 08 02:00:22 PM UTC 25 | Feb 08 02:00:32 PM UTC 25 | 167717288 ps | ||
| T347 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.339271932 | Feb 08 02:00:22 PM UTC 25 | Feb 08 02:00:36 PM UTC 25 | 1230983742 ps | ||
| T348 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2492352563 | Feb 08 02:00:22 PM UTC 25 | Feb 08 02:00:36 PM UTC 25 | 660177435 ps | ||
| T349 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3442092796 | Feb 08 02:00:22 PM UTC 25 | Feb 08 02:00:38 PM UTC 25 | 1030753744 ps | ||
| T350 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3529673844 | Feb 08 02:00:28 PM UTC 25 | Feb 08 02:00:40 PM UTC 25 | 1031983575 ps | ||
| T351 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.194480933 | Feb 08 02:00:22 PM UTC 25 | Feb 08 02:00:40 PM UTC 25 | 517288727 ps | ||
| T352 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_tl_errors.599681013 | Feb 08 02:00:01 PM UTC 25 | Feb 08 02:00:42 PM UTC 25 | 688535965 ps | ||
| T111 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2240131724 | Feb 08 02:00:33 PM UTC 25 | Feb 08 02:00:48 PM UTC 25 | 255815646 ps | ||
| T353 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.139620279 | Feb 08 02:00:36 PM UTC 25 | Feb 08 02:00:51 PM UTC 25 | 178167492 ps | ||
| T354 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1581177702 | Feb 08 02:00:41 PM UTC 25 | Feb 08 02:00:55 PM UTC 25 | 1375824934 ps | ||
| T355 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.447657143 | Feb 08 02:00:42 PM UTC 25 | Feb 08 02:00:57 PM UTC 25 | 1768719943 ps | ||
| T95 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2754772871 | Feb 08 01:59:59 PM UTC 25 | Feb 08 02:00:59 PM UTC 25 | 714894952 ps | ||
| T356 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_tl_errors.4163246522 | Feb 08 02:00:39 PM UTC 25 | Feb 08 02:01:00 PM UTC 25 | 718263778 ps | ||
| T69 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1588508560 | Feb 08 01:58:51 PM UTC 25 | Feb 08 02:01:03 PM UTC 25 | 940359286 ps | ||
| T96 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2037173168 | Feb 08 02:00:53 PM UTC 25 | Feb 08 02:01:06 PM UTC 25 | 788601631 ps | ||
| T97 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2270623236 | Feb 08 02:00:48 PM UTC 25 | Feb 08 02:01:13 PM UTC 25 | 1044322086 ps | ||
| T357 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2916760354 | Feb 08 02:00:58 PM UTC 25 | Feb 08 02:01:13 PM UTC 25 | 2468105110 ps | ||
| T358 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.540609017 | Feb 08 02:00:56 PM UTC 25 | Feb 08 02:01:13 PM UTC 25 | 688974283 ps | ||
| T112 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1980030060 | Feb 08 02:00:59 PM UTC 25 | Feb 08 02:01:14 PM UTC 25 | 692677160 ps | ||
| T359 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.4027009745 | Feb 08 02:01:00 PM UTC 25 | Feb 08 02:01:15 PM UTC 25 | 610297960 ps | ||
| T360 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2172375649 | Feb 08 02:01:04 PM UTC 25 | Feb 08 02:01:22 PM UTC 25 | 171864365 ps | ||
| T113 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3861700438 | Feb 08 02:01:08 PM UTC 25 | Feb 08 02:01:23 PM UTC 25 | 506769034 ps | ||
| T361 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2033534210 | Feb 08 02:01:14 PM UTC 25 | Feb 08 02:01:28 PM UTC 25 | 688906440 ps | ||
| T114 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.836817549 | Feb 08 02:01:14 PM UTC 25 | Feb 08 02:01:31 PM UTC 25 | 1031351790 ps | ||
| T362 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3146857789 | Feb 08 02:01:14 PM UTC 25 | Feb 08 02:01:33 PM UTC 25 | 280432695 ps | ||
| T363 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_csr_rw.186041137 | Feb 08 02:01:23 PM UTC 25 | Feb 08 02:01:36 PM UTC 25 | 173131711 ps | ||
| T364 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2557192161 | Feb 08 02:01:25 PM UTC 25 | Feb 08 02:01:38 PM UTC 25 | 1006958619 ps | ||
| T115 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2872832654 | Feb 08 02:01:24 PM UTC 25 | Feb 08 02:01:39 PM UTC 25 | 991590318 ps | ||
| T99 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2155821220 | Feb 08 02:01:33 PM UTC 25 | Feb 08 02:01:50 PM UTC 25 | 991184800 ps | ||
| T365 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1691832361 | Feb 08 02:01:40 PM UTC 25 | Feb 08 02:01:52 PM UTC 25 | 332930185 ps | ||
| T116 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2046673600 | Feb 08 02:01:38 PM UTC 25 | Feb 08 02:01:53 PM UTC 25 | 517375357 ps | ||
| T366 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.803443705 | Feb 08 02:01:38 PM UTC 25 | Feb 08 02:01:53 PM UTC 25 | 354265623 ps | ||
| T367 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3806860608 | Feb 08 02:01:31 PM UTC 25 | Feb 08 02:01:55 PM UTC 25 | 2101407949 ps | ||
| T368 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2698792031 | Feb 08 02:01:50 PM UTC 25 | Feb 08 02:02:03 PM UTC 25 | 688726944 ps | ||
| T98 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_csr_rw.249788938 | Feb 08 02:01:49 PM UTC 25 | Feb 08 02:02:03 PM UTC 25 | 660756476 ps | ||
| T369 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.530408173 | Feb 08 02:01:53 PM UTC 25 | Feb 08 02:02:08 PM UTC 25 | 988700629 ps | ||
| T105 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3441192923 | Feb 08 02:00:37 PM UTC 25 | Feb 08 02:02:11 PM UTC 25 | 1529789962 ps | ||
| T370 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1312864223 | Feb 08 02:01:53 PM UTC 25 | Feb 08 02:02:12 PM UTC 25 | 661011814 ps | ||
| T371 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3084427727 | Feb 08 02:01:56 PM UTC 25 | Feb 08 02:02:12 PM UTC 25 | 259791812 ps | ||
| T372 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2199203605 | Feb 08 02:02:05 PM UTC 25 | Feb 08 02:02:17 PM UTC 25 | 1114135768 ps | ||
| T373 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3471324023 | Feb 08 02:02:04 PM UTC 25 | Feb 08 02:02:22 PM UTC 25 | 1080018554 ps | ||
| T374 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.794823468 | Feb 08 02:01:39 PM UTC 25 | Feb 08 02:02:27 PM UTC 25 | 1074910875 ps | ||
| T375 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1998888354 | Feb 08 02:02:13 PM UTC 25 | Feb 08 02:02:28 PM UTC 25 | 168024462 ps | ||
| T376 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3130941362 | Feb 08 02:02:12 PM UTC 25 | Feb 08 02:02:32 PM UTC 25 | 1032912664 ps | ||
| T377 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3739661919 | Feb 08 02:02:22 PM UTC 25 | Feb 08 02:02:37 PM UTC 25 | 396440680 ps | ||
| T378 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_rw.668262002 | Feb 08 02:03:07 PM UTC 25 | Feb 08 02:03:22 PM UTC 25 | 250019319 ps | ||
| T70 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1194204099 | Feb 08 01:59:32 PM UTC 25 | Feb 08 02:02:38 PM UTC 25 | 405743595 ps | ||
| T100 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2043615271 | Feb 08 02:01:01 PM UTC 25 | Feb 08 02:02:38 PM UTC 25 | 6096902974 ps | ||
| T379 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.617729435 | Feb 08 02:02:18 PM UTC 25 | Feb 08 02:02:40 PM UTC 25 | 253456396 ps | ||
| T380 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3031950203 | Feb 08 02:02:28 PM UTC 25 | Feb 08 02:02:48 PM UTC 25 | 286984880 ps | ||
| T101 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1329264130 | Feb 08 02:02:37 PM UTC 25 | Feb 08 02:02:50 PM UTC 25 | 174699857 ps | ||
| T381 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3211835716 | Feb 08 02:02:39 PM UTC 25 | Feb 08 02:02:53 PM UTC 25 | 1957647134 ps | ||
| T382 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1992455302 | Feb 08 02:01:28 PM UTC 25 | Feb 08 02:02:55 PM UTC 25 | 1591089019 ps | ||
| T383 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3308886898 | Feb 08 02:02:45 PM UTC 25 | Feb 08 02:03:03 PM UTC 25 | 719206519 ps | ||
| T102 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1328869110 | Feb 08 02:02:51 PM UTC 25 | Feb 08 02:03:05 PM UTC 25 | 265675884 ps | ||
| T384 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2393531120 | Feb 08 02:02:38 PM UTC 25 | Feb 08 02:03:07 PM UTC 25 | 3608511097 ps | ||
| T385 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.4095509429 | Feb 08 02:02:54 PM UTC 25 | Feb 08 02:03:08 PM UTC 25 | 661747932 ps | ||
| T386 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2499767582 | Feb 08 02:01:14 PM UTC 25 | Feb 08 02:03:10 PM UTC 25 | 6337966275 ps | ||
| T387 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1846844783 | Feb 08 02:02:56 PM UTC 25 | Feb 08 02:03:19 PM UTC 25 | 1027007010 ps | ||
| T388 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2693443717 | Feb 08 02:01:53 PM UTC 25 | Feb 08 02:03:20 PM UTC 25 | 1561578551 ps | ||
| T122 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2609081867 | Feb 08 02:01:47 PM UTC 25 | Feb 08 02:03:24 PM UTC 25 | 3813742255 ps | ||
| T103 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1197944377 | Feb 08 02:02:09 PM UTC 25 | Feb 08 02:03:25 PM UTC 25 | 1547675306 ps | ||
| T389 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_errors.479985649 | Feb 08 02:03:06 PM UTC 25 | Feb 08 02:03:26 PM UTC 25 | 450715704 ps | ||
| T390 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2848134922 | Feb 08 02:02:28 PM UTC 25 | Feb 08 02:03:26 PM UTC 25 | 1064156078 ps | ||
| T123 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2758782822 | Feb 08 02:01:55 PM UTC 25 | Feb 08 02:03:30 PM UTC 25 | 1334668722 ps | ||
| T391 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2559341115 | Feb 08 02:03:10 PM UTC 25 | Feb 08 02:03:30 PM UTC 25 | 1066538841 ps | ||
| T392 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2146179529 | Feb 08 02:03:09 PM UTC 25 | Feb 08 02:03:32 PM UTC 25 | 513209891 ps | ||
| T393 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2156561211 | Feb 08 02:02:41 PM UTC 25 | Feb 08 02:03:38 PM UTC 25 | 1016224079 ps | ||
| T394 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_rw.4242518745 | Feb 08 02:03:26 PM UTC 25 | Feb 08 02:03:39 PM UTC 25 | 719546052 ps | ||
| T395 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_errors.987977941 | Feb 08 02:03:20 PM UTC 25 | Feb 08 02:03:39 PM UTC 25 | 508128894 ps | ||
| T396 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.427905725 | Feb 08 02:03:26 PM UTC 25 | Feb 08 02:03:40 PM UTC 25 | 663474324 ps | ||
| T397 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3806025187 | Feb 08 02:03:26 PM UTC 25 | Feb 08 02:03:41 PM UTC 25 | 514488506 ps | ||
| T398 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3968700793 | Feb 08 02:03:27 PM UTC 25 | Feb 08 02:03:44 PM UTC 25 | 358966331 ps | ||
| T104 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3845674301 | Feb 08 02:03:31 PM UTC 25 | Feb 08 02:03:45 PM UTC 25 | 692454890 ps | ||
| T130 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2842659533 | Feb 08 02:00:41 PM UTC 25 | Feb 08 02:03:46 PM UTC 25 | 446639420 ps | ||
| T399 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3032378305 | Feb 08 02:03:32 PM UTC 25 | Feb 08 02:03:51 PM UTC 25 | 182964039 ps | ||
| T400 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3013748660 | Feb 08 02:03:42 PM UTC 25 | Feb 08 02:03:56 PM UTC 25 | 167980645 ps | ||
| T401 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2771297561 | Feb 08 02:03:39 PM UTC 25 | Feb 08 02:03:57 PM UTC 25 | 517687591 ps | ||
| T402 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3590068825 | Feb 08 02:03:44 PM UTC 25 | Feb 08 02:03:59 PM UTC 25 | 190228737 ps | ||
| T403 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3095767888 | Feb 08 02:03:40 PM UTC 25 | Feb 08 02:04:00 PM UTC 25 | 259997517 ps | ||
| T404 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3775901523 | Feb 08 02:03:04 PM UTC 25 | Feb 08 02:04:03 PM UTC 25 | 2104863469 ps | ||
| T405 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.4168452022 | Feb 08 02:03:46 PM UTC 25 | Feb 08 02:04:03 PM UTC 25 | 512083196 ps | ||
| T406 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3147803714 | Feb 08 02:03:51 PM UTC 25 | Feb 08 02:04:08 PM UTC 25 | 1028685162 ps | ||
| T407 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2321420186 | Feb 08 02:03:57 PM UTC 25 | Feb 08 02:04:11 PM UTC 25 | 1033835357 ps | ||
| T408 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3328657004 | Feb 08 02:03:20 PM UTC 25 | Feb 08 02:04:11 PM UTC 25 | 1060794656 ps | ||
| T409 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2368012064 | Feb 08 02:03:59 PM UTC 25 | Feb 08 02:04:13 PM UTC 25 | 1499763657 ps | ||
| T410 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1365501736 | Feb 08 02:04:00 PM UTC 25 | Feb 08 02:04:14 PM UTC 25 | 750476451 ps | ||
| T411 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3909908156 | Feb 08 02:01:15 PM UTC 25 | Feb 08 02:04:19 PM UTC 25 | 1343401280 ps | ||
| T412 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2379997349 | Feb 08 02:04:04 PM UTC 25 | Feb 08 02:04:19 PM UTC 25 | 173312701 ps | ||
| T413 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1788831957 | Feb 08 02:04:12 PM UTC 25 | Feb 08 02:04:22 PM UTC 25 | 1035406337 ps | ||
| T107 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1972458723 | Feb 08 02:03:40 PM UTC 25 | Feb 08 02:04:24 PM UTC 25 | 690871452 ps | ||
| T414 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.4152649118 | Feb 08 02:04:13 PM UTC 25 | Feb 08 02:04:26 PM UTC 25 | 262983487 ps | ||
| T415 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3625530179 | Feb 08 02:04:14 PM UTC 25 | Feb 08 02:04:27 PM UTC 25 | 5177114192 ps | ||
| T106 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1802545631 | Feb 08 02:03:27 PM UTC 25 | Feb 08 02:04:28 PM UTC 25 | 16869987645 ps | ||
| T108 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.832770466 | Feb 08 02:03:46 PM UTC 25 | Feb 08 02:04:35 PM UTC 25 | 5342100335 ps | ||
| T131 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.4001070888 | Feb 08 02:02:49 PM UTC 25 | Feb 08 02:04:36 PM UTC 25 | 619648245 ps | ||
| T416 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2469547371 | Feb 08 02:04:23 PM UTC 25 | Feb 08 02:04:38 PM UTC 25 | 1031308163 ps | ||
| T417 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1007699841 | Feb 08 02:04:25 PM UTC 25 | Feb 08 02:04:42 PM UTC 25 | 257430178 ps | ||
| T418 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1020185216 | Feb 08 02:04:20 PM UTC 25 | Feb 08 02:04:45 PM UTC 25 | 1176927431 ps | ||
| T419 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3390003747 | Feb 08 02:04:26 PM UTC 25 | Feb 08 02:04:49 PM UTC 25 | 4172655098 ps | ||
| T133 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2667766318 | Feb 08 02:01:32 PM UTC 25 | Feb 08 02:04:49 PM UTC 25 | 1936851409 ps | ||
| T420 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.813852916 | Feb 08 02:04:04 PM UTC 25 | Feb 08 02:04:56 PM UTC 25 | 1051452800 ps | ||
| T421 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1973886234 | Feb 08 02:04:15 PM UTC 25 | Feb 08 02:04:57 PM UTC 25 | 692944077 ps | ||
| T125 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1007835668 | Feb 08 02:03:06 PM UTC 25 | Feb 08 02:04:59 PM UTC 25 | 1722747567 ps | ||
| T127 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2676173896 | Feb 08 02:00:22 PM UTC 25 | Feb 08 02:05:02 PM UTC 25 | 492316331 ps | ||
| T134 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1142018722 | Feb 08 02:01:07 PM UTC 25 | Feb 08 02:05:04 PM UTC 25 | 5011411044 ps | ||
| T129 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3762797928 | Feb 08 02:02:33 PM UTC 25 | Feb 08 02:05:22 PM UTC 25 | 2411177833 ps | ||
| T126 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1343312899 | Feb 08 02:03:56 PM UTC 25 | Feb 08 02:05:25 PM UTC 25 | 448133571 ps | ||
| T422 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.167666207 | Feb 08 02:04:10 PM UTC 25 | Feb 08 02:05:50 PM UTC 25 | 353676555 ps | ||
| T124 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.414581385 | Feb 08 02:02:13 PM UTC 25 | Feb 08 02:05:58 PM UTC 25 | 290254126 ps | ||
| T132 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1297303990 | Feb 08 02:03:41 PM UTC 25 | Feb 08 02:06:33 PM UTC 25 | 3929936267 ps | ||
| T423 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.4090442648 | Feb 08 02:03:24 PM UTC 25 | Feb 08 02:06:33 PM UTC 25 | 384043612 ps | ||
| T424 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.638077040 | Feb 08 02:04:20 PM UTC 25 | Feb 08 02:06:38 PM UTC 25 | 1361436278 ps | ||
| T128 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.924194980 | Feb 08 02:03:31 PM UTC 25 | Feb 08 02:07:33 PM UTC 25 | 1588066315 ps |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all.4065703355 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 1978270295 ps |
| CPU time | 32.88 seconds |
| Started | Feb 08 01:38:55 PM UTC 25 |
| Finished | Feb 08 01:39:29 PM UTC 25 |
| Peak memory | 227372 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4065703355 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all.4065703355 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3808242218 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 7250075969 ps |
| CPU time | 254.9 seconds |
| Started | Feb 08 01:38:56 PM UTC 25 |
| Finished | Feb 08 01:43:15 PM UTC 25 |
| Peak memory | 259520 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3808242218 -assert nopostproc +UVM_TESTNAME=rom_c trl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_corrupt_sig_fatal_chk.3808242218 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.2352074337 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 13225342172 ps |
| CPU time | 610.02 seconds |
| Started | Feb 08 01:38:59 PM UTC 25 |
| Finished | Feb 08 01:49:17 PM UTC 25 |
| Peak memory | 240932 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom _ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=2352074337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl _stress_all_with_rand_reset.2352074337 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_max_throughput_chk.3198844352 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 727386726 ps |
| CPU time | 13.91 seconds |
| Started | Feb 08 01:38:58 PM UTC 25 |
| Finished | Feb 08 01:39:13 PM UTC 25 |
| Peak memory | 228372 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3198844352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.3198844352 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_kmac_err_chk.2357016574 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 1952010041 ps |
| CPU time | 29.39 seconds |
| Started | Feb 08 01:39:30 PM UTC 25 |
| Finished | Feb 08 01:40:01 PM UTC 25 |
| Peak memory | 228456 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2357016574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.2357016574 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.555897626 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 15081120802 ps |
| CPU time | 213.32 seconds |
| Started | Feb 08 01:39:47 PM UTC 25 |
| Finished | Feb 08 01:43:24 PM UTC 25 |
| Peak memory | 228784 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=555897626 -assert nopostproc +UVM_TESTNAME=rom_ct rl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_corrupt_sig_fatal_chk.555897626 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_alert_test.1465045646 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 1455988507 ps |
| CPU time | 12.92 seconds |
| Started | Feb 08 01:38:58 PM UTC 25 |
| Finished | Feb 08 01:39:12 PM UTC 25 |
| Peak memory | 227632 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1465045646 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ct rl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.1465045646 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_max_throughput_chk.1959265924 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 2144979520 ps |
| CPU time | 11.97 seconds |
| Started | Feb 08 01:42:20 PM UTC 25 |
| Finished | Feb 08 01:42:33 PM UTC 25 |
| Peak memory | 228452 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1959265924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.1959265924 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2758782822 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 1334668722 ps |
| CPU time | 92.71 seconds |
| Started | Feb 08 02:01:55 PM UTC 25 |
| Finished | Feb 08 02:03:30 PM UTC 25 |
| Peak memory | 228432 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758782822 -assert nopostproc +UVM_TESTNAME= rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_intg_err.2758782822 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all.2180343225 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 574822205 ps |
| CPU time | 38 seconds |
| Started | Feb 08 01:39:57 PM UTC 25 |
| Finished | Feb 08 01:40:37 PM UTC 25 |
| Peak memory | 228524 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2180343225 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all.2180343225 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all.3786960895 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 1033908416 ps |
| CPU time | 24.67 seconds |
| Started | Feb 08 01:39:15 PM UTC 25 |
| Finished | Feb 08 01:39:42 PM UTC 25 |
| Peak memory | 228524 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3786960895 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all.3786960895 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_sec_cm.3792947949 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 500633174 ps |
| CPU time | 271 seconds |
| Started | Feb 08 01:39:28 PM UTC 25 |
| Finished | Feb 08 01:44:03 PM UTC 25 |
| Peak memory | 257228 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792947949 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctr l_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.3792947949 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all.1429709718 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 1098577012 ps |
| CPU time | 32.3 seconds |
| Started | Feb 08 01:38:58 PM UTC 25 |
| Finished | Feb 08 01:39:32 PM UTC 25 |
| Peak memory | 228456 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429709718 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all.1429709718 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.716631299 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 167509384 ps |
| CPU time | 11.56 seconds |
| Started | Feb 08 01:59:20 PM UTC 25 |
| Finished | Feb 08 01:59:33 PM UTC 25 |
| Peak memory | 220928 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=716631299 -assert nopostproc +UVM_TESTNAME=rom_ ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom _ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_aliasing.716631299 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_kmac_err_chk.895843983 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 2059434785 ps |
| CPU time | 30.09 seconds |
| Started | Feb 08 01:40:07 PM UTC 25 |
| Finished | Feb 08 01:40:38 PM UTC 25 |
| Peak memory | 228028 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=895843983 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.895843983 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.414581385 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 290254126 ps |
| CPU time | 221.22 seconds |
| Started | Feb 08 02:02:13 PM UTC 25 |
| Finished | Feb 08 02:05:58 PM UTC 25 |
| Peak memory | 225024 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=414581385 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_intg_err.414581385 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_kmac_err_chk.2734854427 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 342793165 ps |
| CPU time | 19.14 seconds |
| Started | Feb 08 01:38:58 PM UTC 25 |
| Finished | Feb 08 01:39:19 PM UTC 25 |
| Peak memory | 228460 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2734854427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.2734854427 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1007835668 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 1722747567 ps |
| CPU time | 110.8 seconds |
| Started | Feb 08 02:03:06 PM UTC 25 |
| Finished | Feb 08 02:04:59 PM UTC 25 |
| Peak memory | 223172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1007835668 -assert nopostproc +UVM_TESTNAME= rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_intg_err.1007835668 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3095836652 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 1596032192 ps |
| CPU time | 65.77 seconds |
| Started | Feb 08 01:57:24 PM UTC 25 |
| Finished | Feb 08 01:58:31 PM UTC 25 |
| Peak memory | 224972 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3095836652 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_passthru_mem_tl_intg_err.3095836652 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.2193846442 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 14969081785 ps |
| CPU time | 330.89 seconds |
| Started | Feb 08 01:38:58 PM UTC 25 |
| Finished | Feb 08 01:44:33 PM UTC 25 |
| Peak memory | 227784 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2193846442 -assert nopostproc +UVM_TESTNAME=rom_c trl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_corrupt_sig_fatal_chk.2193846442 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_max_throughput_chk.3641009100 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 3963552699 ps |
| CPU time | 23.99 seconds |
| Started | Feb 08 01:39:45 PM UTC 25 |
| Finished | Feb 08 01:40:10 PM UTC 25 |
| Peak memory | 228200 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3641009100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.3641009100 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all.2893317696 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 5530079907 ps |
| CPU time | 60.72 seconds |
| Started | Feb 08 01:41:47 PM UTC 25 |
| Finished | Feb 08 01:42:49 PM UTC 25 |
| Peak memory | 228524 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2893317696 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all.2893317696 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1083715278 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 2175749225 ps |
| CPU time | 126.09 seconds |
| Started | Feb 08 01:57:41 PM UTC 25 |
| Finished | Feb 08 01:59:50 PM UTC 25 |
| Peak memory | 225276 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1083715278 -assert nopostproc +UVM_TESTNAME= rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_intg_err.1083715278 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.4001070888 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 619648245 ps |
| CPU time | 105.16 seconds |
| Started | Feb 08 02:02:49 PM UTC 25 |
| Finished | Feb 08 02:04:36 PM UTC 25 |
| Peak memory | 222980 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4001070888 -assert nopostproc +UVM_TESTNAME= rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_intg_err.4001070888 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.306784487 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 705580249 ps |
| CPU time | 17.34 seconds |
| Started | Feb 08 01:58:32 PM UTC 25 |
| Finished | Feb 08 01:58:51 PM UTC 25 |
| Peak memory | 222912 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306784487 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_same_csr_outstanding.306784487 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.3114159917 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 125016178812 ps |
| CPU time | 1216.9 seconds |
| Started | Feb 08 01:40:37 PM UTC 25 |
| Finished | Feb 08 02:01:08 PM UTC 25 |
| Peak memory | 246124 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom _ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3114159917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl _stress_all_with_rand_reset.3114159917 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_kmac_err_chk.380144298 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 7890789455 ps |
| CPU time | 36.21 seconds |
| Started | Feb 08 01:38:56 PM UTC 25 |
| Finished | Feb 08 01:39:34 PM UTC 25 |
| Peak memory | 228520 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=380144298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.380144298 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.134478133 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 1069942861 ps |
| CPU time | 16.28 seconds |
| Started | Feb 08 01:58:32 PM UTC 25 |
| Finished | Feb 08 01:58:50 PM UTC 25 |
| Peak memory | 220992 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=134478133 -assert nopostproc +UVM_TESTNAME=rom_ ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom _ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_aliasing.134478133 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1044057363 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 1766632670 ps |
| CPU time | 13.18 seconds |
| Started | Feb 08 01:58:25 PM UTC 25 |
| Finished | Feb 08 01:58:40 PM UTC 25 |
| Peak memory | 221124 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1044057363 -assert nopostproc +UVM_TESTNAME=rom _ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ro m_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_bash.1044057363 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1776206640 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 2081632455 ps |
| CPU time | 15.41 seconds |
| Started | Feb 08 01:58:15 PM UTC 25 |
| Finished | Feb 08 01:58:32 PM UTC 25 |
| Peak memory | 222916 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776206640 -assert nopostproc +UVM_TESTNAME=rom _ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ro m_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_reset.1776206640 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.4100586736 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 1975784267 ps |
| CPU time | 10.1 seconds |
| Started | Feb 08 01:58:32 PM UTC 25 |
| Finished | Feb 08 01:58:44 PM UTC 25 |
| Peak memory | 228312 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 4100586736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_wit h_rand_reset.4100586736 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_rw.4087578677 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 253181549 ps |
| CPU time | 13.24 seconds |
| Started | Feb 08 01:58:17 PM UTC 25 |
| Finished | Feb 08 01:58:32 PM UTC 25 |
| Peak memory | 220860 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4087578677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_ base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl _64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.4087578677 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1129241651 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 990543564 ps |
| CPU time | 15.32 seconds |
| Started | Feb 08 01:58:00 PM UTC 25 |
| Finished | Feb 08 01:58:17 PM UTC 25 |
| Peak memory | 220804 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1129241651 -assert nopostproc +UVM_TE STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_partial_access.1129241651 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2607659275 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 989703989 ps |
| CPU time | 14.92 seconds |
| Started | Feb 08 01:57:43 PM UTC 25 |
| Finished | Feb 08 01:57:59 PM UTC 25 |
| Peak memory | 221124 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2607659275 -assert nopostproc +UVM_TESTNAME=rom _ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ro m_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.2607659275 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3903277707 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 168600575 ps |
| CPU time | 12.55 seconds |
| Started | Feb 08 01:57:28 PM UTC 25 |
| Finished | Feb 08 01:57:42 PM UTC 25 |
| Peak memory | 227156 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3903277707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_bas e_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64 kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.3903277707 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1161112683 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 719326383 ps |
| CPU time | 12.51 seconds |
| Started | Feb 08 01:59:12 PM UTC 25 |
| Finished | Feb 08 01:59:26 PM UTC 25 |
| Peak memory | 220796 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161112683 -assert nopostproc +UVM_TESTNAME=rom _ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ro m_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_bash.1161112683 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.99946567 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 671228705 ps |
| CPU time | 13.4 seconds |
| Started | Feb 08 01:59:05 PM UTC 25 |
| Finished | Feb 08 01:59:19 PM UTC 25 |
| Peak memory | 222908 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=99946567 -assert nopostproc +UVM_TESTNAME=rom_c trl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_reset.99946567 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1267304879 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 821010078 ps |
| CPU time | 16.48 seconds |
| Started | Feb 08 01:59:21 PM UTC 25 |
| Finished | Feb 08 01:59:39 PM UTC 25 |
| Peak memory | 228312 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1267304879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_wit h_rand_reset.1267304879 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3718600596 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 338828231 ps |
| CPU time | 13.92 seconds |
| Started | Feb 08 01:59:06 PM UTC 25 |
| Finished | Feb 08 01:59:21 PM UTC 25 |
| Peak memory | 220984 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3718600596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_ base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl _64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.3718600596 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2098645042 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 175200731 ps |
| CPU time | 13.38 seconds |
| Started | Feb 08 01:59:05 PM UTC 25 |
| Finished | Feb 08 01:59:19 PM UTC 25 |
| Peak memory | 220868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098645042 -assert nopostproc +UVM_TE STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_partial_access.2098645042 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1697000965 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 174452894 ps |
| CPU time | 11.3 seconds |
| Started | Feb 08 01:58:52 PM UTC 25 |
| Finished | Feb 08 01:59:04 PM UTC 25 |
| Peak memory | 220868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1697000965 -assert nopostproc +UVM_TESTNAME=rom _ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ro m_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk.1697000965 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3738622108 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 3108300456 ps |
| CPU time | 75.44 seconds |
| Started | Feb 08 01:58:41 PM UTC 25 |
| Finished | Feb 08 01:59:58 PM UTC 25 |
| Peak memory | 225292 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738622108 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_passthru_mem_tl_intg_err.3738622108 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2238762930 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 1158543462 ps |
| CPU time | 13.32 seconds |
| Started | Feb 08 01:59:20 PM UTC 25 |
| Finished | Feb 08 01:59:35 PM UTC 25 |
| Peak memory | 223104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2238762930 -assert nopostproc +UVM_ TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_same_csr_outstanding.2238762930 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_errors.818911234 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 4945179297 ps |
| CPU time | 17.68 seconds |
| Started | Feb 08 01:58:45 PM UTC 25 |
| Finished | Feb 08 01:59:04 PM UTC 25 |
| Peak memory | 228452 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=818911234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base _test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64k B-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.818911234 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1588508560 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 940359286 ps |
| CPU time | 129.67 seconds |
| Started | Feb 08 01:58:51 PM UTC 25 |
| Finished | Feb 08 02:01:03 PM UTC 25 |
| Peak memory | 225148 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1588508560 -assert nopostproc +UVM_TESTNAME= rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_intg_err.1588508560 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3739661919 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 396440680 ps |
| CPU time | 13.68 seconds |
| Started | Feb 08 02:02:22 PM UTC 25 |
| Finished | Feb 08 02:02:37 PM UTC 25 |
| Peak memory | 227084 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3739661919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_wi th_rand_reset.3739661919 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1998888354 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 168024462 ps |
| CPU time | 13.68 seconds |
| Started | Feb 08 02:02:13 PM UTC 25 |
| Finished | Feb 08 02:02:28 PM UTC 25 |
| Peak memory | 221048 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1998888354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_ base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl _64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.1998888354 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1197944377 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 1547675306 ps |
| CPU time | 74.49 seconds |
| Started | Feb 08 02:02:09 PM UTC 25 |
| Finished | Feb 08 02:03:25 PM UTC 25 |
| Peak memory | 224920 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1197944377 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_passthru_mem_tl_intg_err.1197944377 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.617729435 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 253456396 ps |
| CPU time | 20.49 seconds |
| Started | Feb 08 02:02:18 PM UTC 25 |
| Finished | Feb 08 02:02:40 PM UTC 25 |
| Peak memory | 222924 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=617729435 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_same_csr_outstanding.617729435 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3130941362 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 1032912664 ps |
| CPU time | 18.99 seconds |
| Started | Feb 08 02:02:12 PM UTC 25 |
| Finished | Feb 08 02:02:32 PM UTC 25 |
| Peak memory | 228040 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3130941362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_bas e_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64 kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.3130941362 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3211835716 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 1957647134 ps |
| CPU time | 12.5 seconds |
| Started | Feb 08 02:02:39 PM UTC 25 |
| Finished | Feb 08 02:02:53 PM UTC 25 |
| Peak memory | 228580 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3211835716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_wi th_rand_reset.3211835716 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1329264130 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 174699857 ps |
| CPU time | 11.43 seconds |
| Started | Feb 08 02:02:37 PM UTC 25 |
| Finished | Feb 08 02:02:50 PM UTC 25 |
| Peak memory | 221048 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1329264130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_ base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl _64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.1329264130 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2848134922 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 1064156078 ps |
| CPU time | 55.65 seconds |
| Started | Feb 08 02:02:28 PM UTC 25 |
| Finished | Feb 08 02:03:26 PM UTC 25 |
| Peak memory | 224984 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2848134922 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_passthru_mem_tl_intg_err.2848134922 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2393531120 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 3608511097 ps |
| CPU time | 26.69 seconds |
| Started | Feb 08 02:02:38 PM UTC 25 |
| Finished | Feb 08 02:03:07 PM UTC 25 |
| Peak memory | 223236 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2393531120 -assert nopostproc +UVM_ TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_same_csr_outstanding.2393531120 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3031950203 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 286984880 ps |
| CPU time | 18.51 seconds |
| Started | Feb 08 02:02:28 PM UTC 25 |
| Finished | Feb 08 02:02:48 PM UTC 25 |
| Peak memory | 227284 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3031950203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_bas e_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64 kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.3031950203 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3762797928 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 2411177833 ps |
| CPU time | 166.09 seconds |
| Started | Feb 08 02:02:33 PM UTC 25 |
| Finished | Feb 08 02:05:22 PM UTC 25 |
| Peak memory | 225092 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3762797928 -assert nopostproc +UVM_TESTNAME= rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_intg_err.3762797928 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1846844783 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 1027007010 ps |
| CPU time | 22.1 seconds |
| Started | Feb 08 02:02:56 PM UTC 25 |
| Finished | Feb 08 02:03:19 PM UTC 25 |
| Peak memory | 227152 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1846844783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_wi th_rand_reset.1846844783 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1328869110 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 265675884 ps |
| CPU time | 13.06 seconds |
| Started | Feb 08 02:02:51 PM UTC 25 |
| Finished | Feb 08 02:03:05 PM UTC 25 |
| Peak memory | 220984 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1328869110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_ base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl _64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.1328869110 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2156561211 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 1016224079 ps |
| CPU time | 55.65 seconds |
| Started | Feb 08 02:02:41 PM UTC 25 |
| Finished | Feb 08 02:03:38 PM UTC 25 |
| Peak memory | 224984 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2156561211 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_passthru_mem_tl_intg_err.2156561211 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.4095509429 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 661747932 ps |
| CPU time | 12.91 seconds |
| Started | Feb 08 02:02:54 PM UTC 25 |
| Finished | Feb 08 02:03:08 PM UTC 25 |
| Peak memory | 220800 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095509429 -assert nopostproc +UVM_ TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_same_csr_outstanding.4095509429 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3308886898 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 719206519 ps |
| CPU time | 17.02 seconds |
| Started | Feb 08 02:02:45 PM UTC 25 |
| Finished | Feb 08 02:03:03 PM UTC 25 |
| Peak memory | 228328 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3308886898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_bas e_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64 kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.3308886898 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2559341115 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 1066538841 ps |
| CPU time | 18.73 seconds |
| Started | Feb 08 02:03:10 PM UTC 25 |
| Finished | Feb 08 02:03:30 PM UTC 25 |
| Peak memory | 227408 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2559341115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_wi th_rand_reset.2559341115 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_rw.668262002 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 250019319 ps |
| CPU time | 13.75 seconds |
| Started | Feb 08 02:03:07 PM UTC 25 |
| Finished | Feb 08 02:03:22 PM UTC 25 |
| Peak memory | 220856 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=668262002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_b ase_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_ 64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.668262002 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3775901523 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 2104863469 ps |
| CPU time | 57.03 seconds |
| Started | Feb 08 02:03:04 PM UTC 25 |
| Finished | Feb 08 02:04:03 PM UTC 25 |
| Peak memory | 224984 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3775901523 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_passthru_mem_tl_intg_err.3775901523 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2146179529 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 513209891 ps |
| CPU time | 21.36 seconds |
| Started | Feb 08 02:03:09 PM UTC 25 |
| Finished | Feb 08 02:03:32 PM UTC 25 |
| Peak memory | 223108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2146179529 -assert nopostproc +UVM_ TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_same_csr_outstanding.2146179529 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_errors.479985649 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 450715704 ps |
| CPU time | 18.28 seconds |
| Started | Feb 08 02:03:06 PM UTC 25 |
| Finished | Feb 08 02:03:26 PM UTC 25 |
| Peak memory | 227124 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=479985649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base _test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64k B-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.479985649 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3806025187 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 514488506 ps |
| CPU time | 13.27 seconds |
| Started | Feb 08 02:03:26 PM UTC 25 |
| Finished | Feb 08 02:03:41 PM UTC 25 |
| Peak memory | 225040 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3806025187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_wi th_rand_reset.3806025187 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_rw.4242518745 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 719546052 ps |
| CPU time | 11.61 seconds |
| Started | Feb 08 02:03:26 PM UTC 25 |
| Finished | Feb 08 02:03:39 PM UTC 25 |
| Peak memory | 220856 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4242518745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_ base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl _64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.4242518745 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3328657004 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 1060794656 ps |
| CPU time | 49.38 seconds |
| Started | Feb 08 02:03:20 PM UTC 25 |
| Finished | Feb 08 02:04:11 PM UTC 25 |
| Peak memory | 223000 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3328657004 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_passthru_mem_tl_intg_err.3328657004 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.427905725 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 663474324 ps |
| CPU time | 12.66 seconds |
| Started | Feb 08 02:03:26 PM UTC 25 |
| Finished | Feb 08 02:03:40 PM UTC 25 |
| Peak memory | 221060 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=427905725 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_same_csr_outstanding.427905725 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_errors.987977941 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 508128894 ps |
| CPU time | 17.42 seconds |
| Started | Feb 08 02:03:20 PM UTC 25 |
| Finished | Feb 08 02:03:39 PM UTC 25 |
| Peak memory | 228020 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987977941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base _test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64k B-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.987977941 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.4090442648 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 384043612 ps |
| CPU time | 186.64 seconds |
| Started | Feb 08 02:03:24 PM UTC 25 |
| Finished | Feb 08 02:06:33 PM UTC 25 |
| Peak memory | 228248 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4090442648 -assert nopostproc +UVM_TESTNAME= rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_intg_err.4090442648 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2771297561 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 517687591 ps |
| CPU time | 16.9 seconds |
| Started | Feb 08 02:03:39 PM UTC 25 |
| Finished | Feb 08 02:03:57 PM UTC 25 |
| Peak memory | 227084 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2771297561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_wi th_rand_reset.2771297561 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3845674301 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 692454890 ps |
| CPU time | 12.48 seconds |
| Started | Feb 08 02:03:31 PM UTC 25 |
| Finished | Feb 08 02:03:45 PM UTC 25 |
| Peak memory | 220856 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3845674301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_ base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl _64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.3845674301 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1802545631 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 16869987645 ps |
| CPU time | 59.5 seconds |
| Started | Feb 08 02:03:27 PM UTC 25 |
| Finished | Feb 08 02:04:28 PM UTC 25 |
| Peak memory | 225112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1802545631 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_passthru_mem_tl_intg_err.1802545631 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3032378305 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 182964039 ps |
| CPU time | 16.94 seconds |
| Started | Feb 08 02:03:32 PM UTC 25 |
| Finished | Feb 08 02:03:51 PM UTC 25 |
| Peak memory | 222916 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3032378305 -assert nopostproc +UVM_ TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_same_csr_outstanding.3032378305 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3968700793 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 358966331 ps |
| CPU time | 15.07 seconds |
| Started | Feb 08 02:03:27 PM UTC 25 |
| Finished | Feb 08 02:03:44 PM UTC 25 |
| Peak memory | 228360 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3968700793 -assert nopostproc +UVM_TESTNAME=rom_ctrl_bas e_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64 kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.3968700793 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.924194980 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 1588066315 ps |
| CPU time | 237.81 seconds |
| Started | Feb 08 02:03:31 PM UTC 25 |
| Finished | Feb 08 02:07:33 PM UTC 25 |
| Peak memory | 224960 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=924194980 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_intg_err.924194980 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.4168452022 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 512083196 ps |
| CPU time | 15.49 seconds |
| Started | Feb 08 02:03:46 PM UTC 25 |
| Finished | Feb 08 02:04:03 PM UTC 25 |
| Peak memory | 227280 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 4168452022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_wi th_rand_reset.4168452022 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3013748660 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 167980645 ps |
| CPU time | 12.44 seconds |
| Started | Feb 08 02:03:42 PM UTC 25 |
| Finished | Feb 08 02:03:56 PM UTC 25 |
| Peak memory | 220856 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3013748660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_ base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl _64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.3013748660 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1972458723 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 690871452 ps |
| CPU time | 43.04 seconds |
| Started | Feb 08 02:03:40 PM UTC 25 |
| Finished | Feb 08 02:04:24 PM UTC 25 |
| Peak memory | 224984 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1972458723 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_passthru_mem_tl_intg_err.1972458723 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3590068825 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 190228737 ps |
| CPU time | 13.38 seconds |
| Started | Feb 08 02:03:44 PM UTC 25 |
| Finished | Feb 08 02:03:59 PM UTC 25 |
| Peak memory | 222916 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3590068825 -assert nopostproc +UVM_ TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_same_csr_outstanding.3590068825 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3095767888 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 259997517 ps |
| CPU time | 18.87 seconds |
| Started | Feb 08 02:03:40 PM UTC 25 |
| Finished | Feb 08 02:04:00 PM UTC 25 |
| Peak memory | 227092 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3095767888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_bas e_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64 kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.3095767888 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1297303990 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 3929936267 ps |
| CPU time | 169.41 seconds |
| Started | Feb 08 02:03:41 PM UTC 25 |
| Finished | Feb 08 02:06:33 PM UTC 25 |
| Peak memory | 228376 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1297303990 -assert nopostproc +UVM_TESTNAME= rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_intg_err.1297303990 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1365501736 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 750476451 ps |
| CPU time | 12.1 seconds |
| Started | Feb 08 02:04:00 PM UTC 25 |
| Finished | Feb 08 02:04:14 PM UTC 25 |
| Peak memory | 228324 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1365501736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_wi th_rand_reset.1365501736 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2321420186 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 1033835357 ps |
| CPU time | 12.22 seconds |
| Started | Feb 08 02:03:57 PM UTC 25 |
| Finished | Feb 08 02:04:11 PM UTC 25 |
| Peak memory | 220984 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2321420186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_ base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl _64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.2321420186 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.832770466 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 5342100335 ps |
| CPU time | 47.55 seconds |
| Started | Feb 08 02:03:46 PM UTC 25 |
| Finished | Feb 08 02:04:35 PM UTC 25 |
| Peak memory | 225108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=832770466 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_passthru_mem_tl_intg_err.832770466 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2368012064 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 1499763657 ps |
| CPU time | 12.38 seconds |
| Started | Feb 08 02:03:59 PM UTC 25 |
| Finished | Feb 08 02:04:13 PM UTC 25 |
| Peak memory | 221060 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2368012064 -assert nopostproc +UVM_ TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_same_csr_outstanding.2368012064 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3147803714 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 1028685162 ps |
| CPU time | 15.9 seconds |
| Started | Feb 08 02:03:51 PM UTC 25 |
| Finished | Feb 08 02:04:08 PM UTC 25 |
| Peak memory | 227156 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3147803714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_bas e_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64 kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.3147803714 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1343312899 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 448133571 ps |
| CPU time | 86.65 seconds |
| Started | Feb 08 02:03:56 PM UTC 25 |
| Finished | Feb 08 02:05:25 PM UTC 25 |
| Peak memory | 225156 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1343312899 -assert nopostproc +UVM_TESTNAME= rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_intg_err.1343312899 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3625530179 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 5177114192 ps |
| CPU time | 11.55 seconds |
| Started | Feb 08 02:04:14 PM UTC 25 |
| Finished | Feb 08 02:04:27 PM UTC 25 |
| Peak memory | 228452 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3625530179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_wi th_rand_reset.3625530179 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1788831957 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 1035406337 ps |
| CPU time | 9.41 seconds |
| Started | Feb 08 02:04:12 PM UTC 25 |
| Finished | Feb 08 02:04:22 PM UTC 25 |
| Peak memory | 221112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1788831957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_ base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl _64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.1788831957 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.813852916 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 1051452800 ps |
| CPU time | 51.19 seconds |
| Started | Feb 08 02:04:04 PM UTC 25 |
| Finished | Feb 08 02:04:56 PM UTC 25 |
| Peak memory | 225024 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=813852916 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_passthru_mem_tl_intg_err.813852916 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.4152649118 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 262983487 ps |
| CPU time | 11.88 seconds |
| Started | Feb 08 02:04:13 PM UTC 25 |
| Finished | Feb 08 02:04:26 PM UTC 25 |
| Peak memory | 220868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4152649118 -assert nopostproc +UVM_ TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_same_csr_outstanding.4152649118 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2379997349 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 173312701 ps |
| CPU time | 14.23 seconds |
| Started | Feb 08 02:04:04 PM UTC 25 |
| Finished | Feb 08 02:04:19 PM UTC 25 |
| Peak memory | 227336 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2379997349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_bas e_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64 kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.2379997349 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.167666207 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 353676555 ps |
| CPU time | 98.01 seconds |
| Started | Feb 08 02:04:10 PM UTC 25 |
| Finished | Feb 08 02:05:50 PM UTC 25 |
| Peak memory | 222912 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=167666207 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_intg_err.167666207 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3390003747 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 4172655098 ps |
| CPU time | 21.03 seconds |
| Started | Feb 08 02:04:26 PM UTC 25 |
| Finished | Feb 08 02:04:49 PM UTC 25 |
| Peak memory | 228644 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3390003747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_wi th_rand_reset.3390003747 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2469547371 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 1031308163 ps |
| CPU time | 13.12 seconds |
| Started | Feb 08 02:04:23 PM UTC 25 |
| Finished | Feb 08 02:04:38 PM UTC 25 |
| Peak memory | 221048 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2469547371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_ base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl _64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.2469547371 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1973886234 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 692944077 ps |
| CPU time | 40.36 seconds |
| Started | Feb 08 02:04:15 PM UTC 25 |
| Finished | Feb 08 02:04:57 PM UTC 25 |
| Peak memory | 224984 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1973886234 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_passthru_mem_tl_intg_err.1973886234 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1007699841 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 257430178 ps |
| CPU time | 15.32 seconds |
| Started | Feb 08 02:04:25 PM UTC 25 |
| Finished | Feb 08 02:04:42 PM UTC 25 |
| Peak memory | 223172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1007699841 -assert nopostproc +UVM_ TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_same_csr_outstanding.1007699841 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1020185216 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 1176927431 ps |
| CPU time | 23.8 seconds |
| Started | Feb 08 02:04:20 PM UTC 25 |
| Finished | Feb 08 02:04:45 PM UTC 25 |
| Peak memory | 228192 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1020185216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_bas e_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64 kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.1020185216 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.638077040 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 1361436278 ps |
| CPU time | 135.38 seconds |
| Started | Feb 08 02:04:20 PM UTC 25 |
| Finished | Feb 08 02:06:38 PM UTC 25 |
| Peak memory | 228436 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638077040 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_intg_err.638077040 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.390838522 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 259119955 ps |
| CPU time | 15.83 seconds |
| Started | Feb 08 01:59:50 PM UTC 25 |
| Finished | Feb 08 02:00:07 PM UTC 25 |
| Peak memory | 221056 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390838522 -assert nopostproc +UVM_TESTNAME=rom_ ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom _ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_aliasing.390838522 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3582368960 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 345826317 ps |
| CPU time | 14.38 seconds |
| Started | Feb 08 01:59:49 PM UTC 25 |
| Finished | Feb 08 02:00:05 PM UTC 25 |
| Peak memory | 220868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3582368960 -assert nopostproc +UVM_TESTNAME=rom _ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ro m_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_bash.3582368960 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.73776179 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 173868601 ps |
| CPU time | 14.65 seconds |
| Started | Feb 08 01:59:40 PM UTC 25 |
| Finished | Feb 08 01:59:56 PM UTC 25 |
| Peak memory | 222908 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=73776179 -assert nopostproc +UVM_TESTNAME=rom_c trl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_reset.73776179 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3260047878 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 1056398031 ps |
| CPU time | 11.19 seconds |
| Started | Feb 08 01:59:56 PM UTC 25 |
| Finished | Feb 08 02:00:09 PM UTC 25 |
| Peak memory | 227076 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3260047878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_wit h_rand_reset.3260047878 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_rw.184351954 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 260536558 ps |
| CPU time | 13.75 seconds |
| Started | Feb 08 01:59:46 PM UTC 25 |
| Finished | Feb 08 02:00:01 PM UTC 25 |
| Peak memory | 221056 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184351954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_b ase_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_ 64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.184351954 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1699722111 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 175258469 ps |
| CPU time | 11.45 seconds |
| Started | Feb 08 01:59:36 PM UTC 25 |
| Finished | Feb 08 01:59:48 PM UTC 25 |
| Peak memory | 220868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1699722111 -assert nopostproc +UVM_TE STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_partial_access.1699722111 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1426960618 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 167743501 ps |
| CPU time | 9.85 seconds |
| Started | Feb 08 01:59:34 PM UTC 25 |
| Finished | Feb 08 01:59:45 PM UTC 25 |
| Peak memory | 220868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1426960618 -assert nopostproc +UVM_TESTNAME=rom _ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ro m_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk.1426960618 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3984622134 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 2962013892 ps |
| CPU time | 63.16 seconds |
| Started | Feb 08 01:59:22 PM UTC 25 |
| Finished | Feb 08 02:00:27 PM UTC 25 |
| Peak memory | 225028 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3984622134 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_passthru_mem_tl_intg_err.3984622134 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.4191259761 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 2019425600 ps |
| CPU time | 26.28 seconds |
| Started | Feb 08 01:59:51 PM UTC 25 |
| Finished | Feb 08 02:00:19 PM UTC 25 |
| Peak memory | 221064 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191259761 -assert nopostproc +UVM_ TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_same_csr_outstanding.4191259761 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2646144810 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 407224259 ps |
| CPU time | 21.36 seconds |
| Started | Feb 08 01:59:26 PM UTC 25 |
| Finished | Feb 08 01:59:49 PM UTC 25 |
| Peak memory | 227160 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2646144810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_bas e_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64 kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.2646144810 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1194204099 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 405743595 ps |
| CPU time | 183.4 seconds |
| Started | Feb 08 01:59:32 PM UTC 25 |
| Finished | Feb 08 02:02:38 PM UTC 25 |
| Peak memory | 225148 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1194204099 -assert nopostproc +UVM_TESTNAME= rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_intg_err.1194204099 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3529673844 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 1031983575 ps |
| CPU time | 10.76 seconds |
| Started | Feb 08 02:00:28 PM UTC 25 |
| Finished | Feb 08 02:00:40 PM UTC 25 |
| Peak memory | 220868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3529673844 -assert nopostproc +UVM_TESTNAME=rom _ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ro m_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_aliasing.3529673844 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2492352563 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 660177435 ps |
| CPU time | 12.45 seconds |
| Started | Feb 08 02:00:22 PM UTC 25 |
| Finished | Feb 08 02:00:36 PM UTC 25 |
| Peak memory | 220796 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2492352563 -assert nopostproc +UVM_TESTNAME=rom _ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ro m_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_bash.2492352563 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.194480933 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 517288727 ps |
| CPU time | 17.12 seconds |
| Started | Feb 08 02:00:22 PM UTC 25 |
| Finished | Feb 08 02:00:40 PM UTC 25 |
| Peak memory | 223076 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=194480933 -assert nopostproc +UVM_TESTNAME=rom_ ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom _ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_reset.194480933 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.139620279 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 178167492 ps |
| CPU time | 13.68 seconds |
| Started | Feb 08 02:00:36 PM UTC 25 |
| Finished | Feb 08 02:00:51 PM UTC 25 |
| Peak memory | 225172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 139620279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with _rand_reset.139620279 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3442092796 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 1030753744 ps |
| CPU time | 14.93 seconds |
| Started | Feb 08 02:00:22 PM UTC 25 |
| Finished | Feb 08 02:00:38 PM UTC 25 |
| Peak memory | 221048 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442092796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_ base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl _64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.3442092796 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.339271932 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 1230983742 ps |
| CPU time | 12.53 seconds |
| Started | Feb 08 02:00:22 PM UTC 25 |
| Finished | Feb 08 02:00:36 PM UTC 25 |
| Peak memory | 220860 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339271932 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_partial_access.339271932 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1483423006 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 167717288 ps |
| CPU time | 8.62 seconds |
| Started | Feb 08 02:00:22 PM UTC 25 |
| Finished | Feb 08 02:00:32 PM UTC 25 |
| Peak memory | 220868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1483423006 -assert nopostproc +UVM_TESTNAME=rom _ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ro m_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.1483423006 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2754772871 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 714894952 ps |
| CPU time | 58.04 seconds |
| Started | Feb 08 01:59:59 PM UTC 25 |
| Finished | Feb 08 02:00:59 PM UTC 25 |
| Peak memory | 222924 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2754772871 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_passthru_mem_tl_intg_err.2754772871 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2240131724 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 255815646 ps |
| CPU time | 13.36 seconds |
| Started | Feb 08 02:00:33 PM UTC 25 |
| Finished | Feb 08 02:00:48 PM UTC 25 |
| Peak memory | 220872 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2240131724 -assert nopostproc +UVM_ TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_same_csr_outstanding.2240131724 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_tl_errors.599681013 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 688535965 ps |
| CPU time | 19.43 seconds |
| Started | Feb 08 02:00:01 PM UTC 25 |
| Finished | Feb 08 02:00:42 PM UTC 25 |
| Peak memory | 228452 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=599681013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base _test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64k B-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.599681013 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2676173896 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 492316331 ps |
| CPU time | 276.31 seconds |
| Started | Feb 08 02:00:22 PM UTC 25 |
| Finished | Feb 08 02:05:02 PM UTC 25 |
| Peak memory | 224956 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2676173896 -assert nopostproc +UVM_TESTNAME= rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_intg_err.2676173896 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2916760354 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 2468105110 ps |
| CPU time | 14.36 seconds |
| Started | Feb 08 02:00:58 PM UTC 25 |
| Finished | Feb 08 02:01:13 PM UTC 25 |
| Peak memory | 221188 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2916760354 -assert nopostproc +UVM_TESTNAME=rom _ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ro m_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_aliasing.2916760354 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.540609017 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 688974283 ps |
| CPU time | 16.45 seconds |
| Started | Feb 08 02:00:56 PM UTC 25 |
| Finished | Feb 08 02:01:13 PM UTC 25 |
| Peak memory | 220864 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=540609017 -assert nopostproc +UVM_TESTNAME=rom_ ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom _ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_bash.540609017 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2270623236 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 1044322086 ps |
| CPU time | 23.08 seconds |
| Started | Feb 08 02:00:48 PM UTC 25 |
| Finished | Feb 08 02:01:13 PM UTC 25 |
| Peak memory | 222916 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270623236 -assert nopostproc +UVM_TESTNAME=rom _ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ro m_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_reset.2270623236 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.4027009745 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 610297960 ps |
| CPU time | 13.56 seconds |
| Started | Feb 08 02:01:00 PM UTC 25 |
| Finished | Feb 08 02:01:15 PM UTC 25 |
| Peak memory | 225092 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 4027009745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_wit h_rand_reset.4027009745 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2037173168 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 788601631 ps |
| CPU time | 12.09 seconds |
| Started | Feb 08 02:00:53 PM UTC 25 |
| Finished | Feb 08 02:01:06 PM UTC 25 |
| Peak memory | 220924 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2037173168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_ base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl _64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.2037173168 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.447657143 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 1768719943 ps |
| CPU time | 13.23 seconds |
| Started | Feb 08 02:00:42 PM UTC 25 |
| Finished | Feb 08 02:00:57 PM UTC 25 |
| Peak memory | 220860 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=447657143 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_partial_access.447657143 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1581177702 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 1375824934 ps |
| CPU time | 12.49 seconds |
| Started | Feb 08 02:00:41 PM UTC 25 |
| Finished | Feb 08 02:00:55 PM UTC 25 |
| Peak memory | 220868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1581177702 -assert nopostproc +UVM_TESTNAME=rom _ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ro m_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk.1581177702 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3441192923 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 1529789962 ps |
| CPU time | 91.44 seconds |
| Started | Feb 08 02:00:37 PM UTC 25 |
| Finished | Feb 08 02:02:11 PM UTC 25 |
| Peak memory | 224972 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3441192923 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_passthru_mem_tl_intg_err.3441192923 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1980030060 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 692677160 ps |
| CPU time | 13.67 seconds |
| Started | Feb 08 02:00:59 PM UTC 25 |
| Finished | Feb 08 02:01:14 PM UTC 25 |
| Peak memory | 222916 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980030060 -assert nopostproc +UVM_ TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_same_csr_outstanding.1980030060 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_tl_errors.4163246522 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 718263778 ps |
| CPU time | 19.64 seconds |
| Started | Feb 08 02:00:39 PM UTC 25 |
| Finished | Feb 08 02:01:00 PM UTC 25 |
| Peak memory | 227368 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4163246522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_bas e_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64 kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.4163246522 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2842659533 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 446639420 ps |
| CPU time | 181.38 seconds |
| Started | Feb 08 02:00:41 PM UTC 25 |
| Finished | Feb 08 02:03:46 PM UTC 25 |
| Peak memory | 228168 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2842659533 -assert nopostproc +UVM_TESTNAME= rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_intg_err.2842659533 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3146857789 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 280432695 ps |
| CPU time | 17.18 seconds |
| Started | Feb 08 02:01:14 PM UTC 25 |
| Finished | Feb 08 02:01:33 PM UTC 25 |
| Peak memory | 228312 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3146857789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_wit h_rand_reset.3146857789 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3861700438 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 506769034 ps |
| CPU time | 13.16 seconds |
| Started | Feb 08 02:01:08 PM UTC 25 |
| Finished | Feb 08 02:01:23 PM UTC 25 |
| Peak memory | 220920 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3861700438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_ base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl _64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.3861700438 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2043615271 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 6096902974 ps |
| CPU time | 95.12 seconds |
| Started | Feb 08 02:01:01 PM UTC 25 |
| Finished | Feb 08 02:02:38 PM UTC 25 |
| Peak memory | 225292 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043615271 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_passthru_mem_tl_intg_err.2043615271 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.836817549 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 1031351790 ps |
| CPU time | 15.8 seconds |
| Started | Feb 08 02:01:14 PM UTC 25 |
| Finished | Feb 08 02:01:31 PM UTC 25 |
| Peak memory | 220868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836817549 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_same_csr_outstanding.836817549 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2172375649 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 171864365 ps |
| CPU time | 16.26 seconds |
| Started | Feb 08 02:01:04 PM UTC 25 |
| Finished | Feb 08 02:01:22 PM UTC 25 |
| Peak memory | 227284 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2172375649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_bas e_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64 kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.2172375649 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1142018722 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 5011411044 ps |
| CPU time | 233.04 seconds |
| Started | Feb 08 02:01:07 PM UTC 25 |
| Finished | Feb 08 02:05:04 PM UTC 25 |
| Peak memory | 228432 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1142018722 -assert nopostproc +UVM_TESTNAME= rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_intg_err.1142018722 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2557192161 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 1006958619 ps |
| CPU time | 11.44 seconds |
| Started | Feb 08 02:01:25 PM UTC 25 |
| Finished | Feb 08 02:01:38 PM UTC 25 |
| Peak memory | 228312 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2557192161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_wit h_rand_reset.2557192161 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_csr_rw.186041137 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 173131711 ps |
| CPU time | 12.44 seconds |
| Started | Feb 08 02:01:23 PM UTC 25 |
| Finished | Feb 08 02:01:36 PM UTC 25 |
| Peak memory | 221120 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=186041137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_b ase_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_ 64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.186041137 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2499767582 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 6337966275 ps |
| CPU time | 113.23 seconds |
| Started | Feb 08 02:01:14 PM UTC 25 |
| Finished | Feb 08 02:03:10 PM UTC 25 |
| Peak memory | 225292 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2499767582 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_passthru_mem_tl_intg_err.2499767582 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2872832654 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 991590318 ps |
| CPU time | 14.47 seconds |
| Started | Feb 08 02:01:24 PM UTC 25 |
| Finished | Feb 08 02:01:39 PM UTC 25 |
| Peak memory | 221064 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2872832654 -assert nopostproc +UVM_ TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_same_csr_outstanding.2872832654 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2033534210 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 688906440 ps |
| CPU time | 12.06 seconds |
| Started | Feb 08 02:01:14 PM UTC 25 |
| Finished | Feb 08 02:01:28 PM UTC 25 |
| Peak memory | 228256 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2033534210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_bas e_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64 kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.2033534210 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3909908156 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 1343401280 ps |
| CPU time | 180.45 seconds |
| Started | Feb 08 02:01:15 PM UTC 25 |
| Finished | Feb 08 02:04:19 PM UTC 25 |
| Peak memory | 228304 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3909908156 -assert nopostproc +UVM_TESTNAME= rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_intg_err.3909908156 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.803443705 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 354265623 ps |
| CPU time | 13.86 seconds |
| Started | Feb 08 02:01:38 PM UTC 25 |
| Finished | Feb 08 02:01:53 PM UTC 25 |
| Peak memory | 227032 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 803443705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with _rand_reset.803443705 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2155821220 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 991184800 ps |
| CPU time | 14.97 seconds |
| Started | Feb 08 02:01:33 PM UTC 25 |
| Finished | Feb 08 02:01:50 PM UTC 25 |
| Peak memory | 220860 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2155821220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_ base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl _64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.2155821220 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1992455302 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 1591089019 ps |
| CPU time | 84.29 seconds |
| Started | Feb 08 02:01:28 PM UTC 25 |
| Finished | Feb 08 02:02:55 PM UTC 25 |
| Peak memory | 224972 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1992455302 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_passthru_mem_tl_intg_err.1992455302 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2046673600 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 517375357 ps |
| CPU time | 13.78 seconds |
| Started | Feb 08 02:01:38 PM UTC 25 |
| Finished | Feb 08 02:01:53 PM UTC 25 |
| Peak memory | 222876 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2046673600 -assert nopostproc +UVM_ TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_same_csr_outstanding.2046673600 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3806860608 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 2101407949 ps |
| CPU time | 22.84 seconds |
| Started | Feb 08 02:01:31 PM UTC 25 |
| Finished | Feb 08 02:01:55 PM UTC 25 |
| Peak memory | 227112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3806860608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_bas e_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64 kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.3806860608 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2667766318 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 1936851409 ps |
| CPU time | 193.72 seconds |
| Started | Feb 08 02:01:32 PM UTC 25 |
| Finished | Feb 08 02:04:49 PM UTC 25 |
| Peak memory | 228496 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2667766318 -assert nopostproc +UVM_TESTNAME= rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_intg_err.2667766318 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.530408173 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 988700629 ps |
| CPU time | 13.85 seconds |
| Started | Feb 08 02:01:53 PM UTC 25 |
| Finished | Feb 08 02:02:08 PM UTC 25 |
| Peak memory | 227156 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 530408173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with _rand_reset.530408173 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_csr_rw.249788938 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 660756476 ps |
| CPU time | 13.26 seconds |
| Started | Feb 08 02:01:49 PM UTC 25 |
| Finished | Feb 08 02:02:03 PM UTC 25 |
| Peak memory | 220928 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=249788938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_b ase_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_ 64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.249788938 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.794823468 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 1074910875 ps |
| CPU time | 47.11 seconds |
| Started | Feb 08 02:01:39 PM UTC 25 |
| Finished | Feb 08 02:02:27 PM UTC 25 |
| Peak memory | 224904 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=794823468 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_passthru_mem_tl_intg_err.794823468 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2698792031 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 688726944 ps |
| CPU time | 12.19 seconds |
| Started | Feb 08 02:01:50 PM UTC 25 |
| Finished | Feb 08 02:02:03 PM UTC 25 |
| Peak memory | 222920 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2698792031 -assert nopostproc +UVM_ TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_same_csr_outstanding.2698792031 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1691832361 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 332930185 ps |
| CPU time | 11.1 seconds |
| Started | Feb 08 02:01:40 PM UTC 25 |
| Finished | Feb 08 02:01:52 PM UTC 25 |
| Peak memory | 228328 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1691832361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_bas e_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64 kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.1691832361 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2609081867 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 3813742255 ps |
| CPU time | 95.42 seconds |
| Started | Feb 08 02:01:47 PM UTC 25 |
| Finished | Feb 08 02:03:24 PM UTC 25 |
| Peak memory | 223228 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609081867 -assert nopostproc +UVM_TESTNAME= rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_intg_err.2609081867 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2199203605 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 1114135768 ps |
| CPU time | 11.7 seconds |
| Started | Feb 08 02:02:05 PM UTC 25 |
| Finished | Feb 08 02:02:17 PM UTC 25 |
| Peak memory | 225028 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2199203605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_wit h_rand_reset.2199203605 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3084427727 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 259791812 ps |
| CPU time | 14.34 seconds |
| Started | Feb 08 02:01:56 PM UTC 25 |
| Finished | Feb 08 02:02:12 PM UTC 25 |
| Peak memory | 220856 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3084427727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_ base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl _64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.3084427727 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2693443717 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 1561578551 ps |
| CPU time | 84.71 seconds |
| Started | Feb 08 02:01:53 PM UTC 25 |
| Finished | Feb 08 02:03:20 PM UTC 25 |
| Peak memory | 225164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2693443717 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_passthru_mem_tl_intg_err.2693443717 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3471324023 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 1080018554 ps |
| CPU time | 15.81 seconds |
| Started | Feb 08 02:02:04 PM UTC 25 |
| Finished | Feb 08 02:02:22 PM UTC 25 |
| Peak memory | 222920 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3471324023 -assert nopostproc +UVM_ TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_same_csr_outstanding.3471324023 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1312864223 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 661011814 ps |
| CPU time | 17.4 seconds |
| Started | Feb 08 02:01:53 PM UTC 25 |
| Finished | Feb 08 02:02:12 PM UTC 25 |
| Peak memory | 227968 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1312864223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_bas e_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64 kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.1312864223 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_max_throughput_chk.1992092928 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 189621699 ps |
| CPU time | 16.27 seconds |
| Started | Feb 08 01:38:56 PM UTC 25 |
| Finished | Feb 08 01:39:14 PM UTC 25 |
| Peak memory | 228528 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1992092928 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.1992092928 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_sec_cm.207661229 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 607384508 ps |
| CPU time | 238.77 seconds |
| Started | Feb 08 01:38:56 PM UTC 25 |
| Finished | Feb 08 01:42:59 PM UTC 25 |
| Peak memory | 257256 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207661229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_ base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl _64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.207661229 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_smoke.142700926 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 325301989 ps |
| CPU time | 15.51 seconds |
| Started | Feb 08 01:38:55 PM UTC 25 |
| Finished | Feb 08 01:39:12 PM UTC 25 |
| Peak memory | 228312 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=142700926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.142700926 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_alert_test.4124862449 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 477609336 ps |
| CPU time | 12.53 seconds |
| Started | Feb 08 01:39:13 PM UTC 25 |
| Finished | Feb 08 01:39:27 PM UTC 25 |
| Peak memory | 227560 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4124862449 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ct rl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.4124862449 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_sec_cm.1032058095 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 2283037410 ps |
| CPU time | 246.94 seconds |
| Started | Feb 08 01:39:13 PM UTC 25 |
| Finished | Feb 08 01:43:24 PM UTC 25 |
| Peak memory | 259476 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032058095 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctr l_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.1032058095 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_smoke.3635136370 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 1064838314 ps |
| CPU time | 15.54 seconds |
| Started | Feb 08 01:38:58 PM UTC 25 |
| Finished | Feb 08 01:39:15 PM UTC 25 |
| Peak memory | 228464 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3635136370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.3635136370 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_alert_test.276583891 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 174960771 ps |
| CPU time | 10.67 seconds |
| Started | Feb 08 01:42:07 PM UTC 25 |
| Finished | Feb 08 01:42:19 PM UTC 25 |
| Peak memory | 227584 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276583891 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctr l_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.276583891 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.3034047209 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 19490961284 ps |
| CPU time | 280.51 seconds |
| Started | Feb 08 01:41:56 PM UTC 25 |
| Finished | Feb 08 01:46:40 PM UTC 25 |
| Peak memory | 257324 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3034047209 -assert nopostproc +UVM_TESTNAME=rom_c trl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_corrupt_sig_fatal_chk.3034047209 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_kmac_err_chk.1700617680 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 652587770 ps |
| CPU time | 29.74 seconds |
| Started | Feb 08 01:41:57 PM UTC 25 |
| Finished | Feb 08 01:42:28 PM UTC 25 |
| Peak memory | 228416 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1700617680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.1700617680 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_max_throughput_chk.2378880627 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 1073649566 ps |
| CPU time | 17.08 seconds |
| Started | Feb 08 01:41:52 PM UTC 25 |
| Finished | Feb 08 01:42:10 PM UTC 25 |
| Peak memory | 228452 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2378880627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.2378880627 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_alert_test.453248430 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 2753304837 ps |
| CPU time | 12.86 seconds |
| Started | Feb 08 01:42:24 PM UTC 25 |
| Finished | Feb 08 01:42:38 PM UTC 25 |
| Peak memory | 227696 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=453248430 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctr l_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.453248430 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.1362281714 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 7037525473 ps |
| CPU time | 448.22 seconds |
| Started | Feb 08 01:42:21 PM UTC 25 |
| Finished | Feb 08 01:49:55 PM UTC 25 |
| Peak memory | 256392 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1362281714 -assert nopostproc +UVM_TESTNAME=rom_c trl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_corrupt_sig_fatal_chk.1362281714 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_kmac_err_chk.2456360184 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 2545617708 ps |
| CPU time | 26.31 seconds |
| Started | Feb 08 01:42:21 PM UTC 25 |
| Finished | Feb 08 01:42:48 PM UTC 25 |
| Peak memory | 228532 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456360184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.2456360184 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all.897914116 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 1587316148 ps |
| CPU time | 50.65 seconds |
| Started | Feb 08 01:42:11 PM UTC 25 |
| Finished | Feb 08 01:43:04 PM UTC 25 |
| Peak memory | 228456 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=897914116 -assert no postproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all.897914116 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.2077265494 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 981678825591 ps |
| CPU time | 2913.01 seconds |
| Started | Feb 08 01:42:22 PM UTC 25 |
| Finished | Feb 08 02:31:26 PM UTC 25 |
| Peak memory | 256364 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom _ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=2077265494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctr l_stress_all_with_rand_reset.2077265494 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_alert_test.449851500 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 505725013 ps |
| CPU time | 13.21 seconds |
| Started | Feb 08 01:42:50 PM UTC 25 |
| Finished | Feb 08 01:43:05 PM UTC 25 |
| Peak memory | 227372 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=449851500 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctr l_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.449851500 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1167892298 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 10442320795 ps |
| CPU time | 252.64 seconds |
| Started | Feb 08 01:42:35 PM UTC 25 |
| Finished | Feb 08 01:46:51 PM UTC 25 |
| Peak memory | 246152 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1167892298 -assert nopostproc +UVM_TESTNAME=rom_c trl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_corrupt_sig_fatal_chk.1167892298 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_kmac_err_chk.395736044 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 506838598 ps |
| CPU time | 35.4 seconds |
| Started | Feb 08 01:42:39 PM UTC 25 |
| Finished | Feb 08 01:43:16 PM UTC 25 |
| Peak memory | 228456 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395736044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.395736044 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_max_throughput_chk.1755891087 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 726520130 ps |
| CPU time | 13.93 seconds |
| Started | Feb 08 01:42:34 PM UTC 25 |
| Finished | Feb 08 01:42:49 PM UTC 25 |
| Peak memory | 228452 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1755891087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.1755891087 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all.2518581006 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 1446571449 ps |
| CPU time | 32.53 seconds |
| Started | Feb 08 01:42:29 PM UTC 25 |
| Finished | Feb 08 01:43:03 PM UTC 25 |
| Peak memory | 228524 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2518581006 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_stress_all.2518581006 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_alert_test.376225233 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 327033728 ps |
| CPU time | 15.21 seconds |
| Started | Feb 08 01:43:05 PM UTC 25 |
| Finished | Feb 08 01:43:22 PM UTC 25 |
| Peak memory | 227656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=376225233 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctr l_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.376225233 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3781905125 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 4655690782 ps |
| CPU time | 280.23 seconds |
| Started | Feb 08 01:42:59 PM UTC 25 |
| Finished | Feb 08 01:47:44 PM UTC 25 |
| Peak memory | 246120 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781905125 -assert nopostproc +UVM_TESTNAME=rom_c trl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_corrupt_sig_fatal_chk.3781905125 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_kmac_err_chk.860038489 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 519512071 ps |
| CPU time | 32.85 seconds |
| Started | Feb 08 01:43:04 PM UTC 25 |
| Finished | Feb 08 01:43:38 PM UTC 25 |
| Peak memory | 228520 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=860038489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.860038489 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_max_throughput_chk.1066576148 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 511125115 ps |
| CPU time | 15.3 seconds |
| Started | Feb 08 01:42:52 PM UTC 25 |
| Finished | Feb 08 01:43:09 PM UTC 25 |
| Peak memory | 228452 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1066576148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.1066576148 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all.13807975 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 841294655 ps |
| CPU time | 36.74 seconds |
| Started | Feb 08 01:42:50 PM UTC 25 |
| Finished | Feb 08 01:43:29 PM UTC 25 |
| Peak memory | 228456 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13807975 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all.13807975 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_alert_test.1230182986 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 348025436 ps |
| CPU time | 12.79 seconds |
| Started | Feb 08 01:43:22 PM UTC 25 |
| Finished | Feb 08 01:43:36 PM UTC 25 |
| Peak memory | 227536 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1230182986 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ct rl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.1230182986 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.397903820 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 2908438961 ps |
| CPU time | 272.89 seconds |
| Started | Feb 08 01:43:09 PM UTC 25 |
| Finished | Feb 08 01:47:46 PM UTC 25 |
| Peak memory | 256800 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=397903820 -assert nopostproc +UVM_TESTNAME=rom_ct rl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_corrupt_sig_fatal_chk.397903820 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_kmac_err_chk.689881074 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 639426677 ps |
| CPU time | 22.39 seconds |
| Started | Feb 08 01:43:15 PM UTC 25 |
| Finished | Feb 08 01:43:39 PM UTC 25 |
| Peak memory | 228456 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=689881074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.689881074 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_max_throughput_chk.1827727028 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 1597413108 ps |
| CPU time | 11.99 seconds |
| Started | Feb 08 01:43:07 PM UTC 25 |
| Finished | Feb 08 01:43:21 PM UTC 25 |
| Peak memory | 228452 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1827727028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.1827727028 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all.1318918964 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 205392891 ps |
| CPU time | 26.19 seconds |
| Started | Feb 08 01:43:05 PM UTC 25 |
| Finished | Feb 08 01:43:33 PM UTC 25 |
| Peak memory | 228020 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1318918964 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all.1318918964 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.3608323189 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 103644496888 ps |
| CPU time | 4590.44 seconds |
| Started | Feb 08 01:43:18 PM UTC 25 |
| Finished | Feb 08 03:00:36 PM UTC 25 |
| Peak memory | 280916 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom _ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3608323189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctr l_stress_all_with_rand_reset.3608323189 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_alert_test.1138858054 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 383567808 ps |
| CPU time | 15.81 seconds |
| Started | Feb 08 01:43:33 PM UTC 25 |
| Finished | Feb 08 01:43:50 PM UTC 25 |
| Peak memory | 227632 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1138858054 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ct rl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.1138858054 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1975110029 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 17715707947 ps |
| CPU time | 361.36 seconds |
| Started | Feb 08 01:43:25 PM UTC 25 |
| Finished | Feb 08 01:49:31 PM UTC 25 |
| Peak memory | 257456 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1975110029 -assert nopostproc +UVM_TESTNAME=rom_c trl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_corrupt_sig_fatal_chk.1975110029 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_kmac_err_chk.3877272377 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 1034192079 ps |
| CPU time | 33.23 seconds |
| Started | Feb 08 01:43:25 PM UTC 25 |
| Finished | Feb 08 01:44:00 PM UTC 25 |
| Peak memory | 228468 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3877272377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.3877272377 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_max_throughput_chk.1092612627 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 357744950 ps |
| CPU time | 11.39 seconds |
| Started | Feb 08 01:43:23 PM UTC 25 |
| Finished | Feb 08 01:43:35 PM UTC 25 |
| Peak memory | 228516 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1092612627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.1092612627 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all.3662487770 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 754651932 ps |
| CPU time | 39.64 seconds |
| Started | Feb 08 01:43:23 PM UTC 25 |
| Finished | Feb 08 01:44:04 PM UTC 25 |
| Peak memory | 228436 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3662487770 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all.3662487770 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.220689185 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 25650558764 ps |
| CPU time | 4397.6 seconds |
| Started | Feb 08 01:43:29 PM UTC 25 |
| Finished | Feb 08 02:57:22 PM UTC 25 |
| Peak memory | 244124 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom _ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=220689185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl _stress_all_with_rand_reset.220689185 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_alert_test.2962720311 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 4086105897 ps |
| CPU time | 22.1 seconds |
| Started | Feb 08 01:43:40 PM UTC 25 |
| Finished | Feb 08 01:44:04 PM UTC 25 |
| Peak memory | 227744 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2962720311 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ct rl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.2962720311 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.311172821 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 7141423716 ps |
| CPU time | 313.37 seconds |
| Started | Feb 08 01:43:36 PM UTC 25 |
| Finished | Feb 08 01:48:54 PM UTC 25 |
| Peak memory | 256372 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=311172821 -assert nopostproc +UVM_TESTNAME=rom_ct rl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_corrupt_sig_fatal_chk.311172821 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_kmac_err_chk.1150289040 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 1015355718 ps |
| CPU time | 33.84 seconds |
| Started | Feb 08 01:43:36 PM UTC 25 |
| Finished | Feb 08 01:44:12 PM UTC 25 |
| Peak memory | 228468 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1150289040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.1150289040 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_max_throughput_chk.1589915266 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 187264536 ps |
| CPU time | 14.88 seconds |
| Started | Feb 08 01:43:34 PM UTC 25 |
| Finished | Feb 08 01:43:50 PM UTC 25 |
| Peak memory | 228516 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1589915266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.1589915266 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all.611562869 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 1128330059 ps |
| CPU time | 19.15 seconds |
| Started | Feb 08 01:43:34 PM UTC 25 |
| Finished | Feb 08 01:43:55 PM UTC 25 |
| Peak memory | 228456 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=611562869 -assert no postproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all.611562869 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_alert_test.3704538648 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 518792515 ps |
| CPU time | 12.45 seconds |
| Started | Feb 08 01:44:01 PM UTC 25 |
| Finished | Feb 08 01:44:15 PM UTC 25 |
| Peak memory | 227608 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704538648 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ct rl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.3704538648 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.4159886440 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 6563355205 ps |
| CPU time | 406.35 seconds |
| Started | Feb 08 01:43:56 PM UTC 25 |
| Finished | Feb 08 01:50:47 PM UTC 25 |
| Peak memory | 258504 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4159886440 -assert nopostproc +UVM_TESTNAME=rom_c trl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_corrupt_sig_fatal_chk.4159886440 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_kmac_err_chk.905555035 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 337453302 ps |
| CPU time | 20.58 seconds |
| Started | Feb 08 01:43:57 PM UTC 25 |
| Finished | Feb 08 01:44:19 PM UTC 25 |
| Peak memory | 228460 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=905555035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.905555035 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_max_throughput_chk.3163609316 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 2498023939 ps |
| CPU time | 11.6 seconds |
| Started | Feb 08 01:43:52 PM UTC 25 |
| Finished | Feb 08 01:44:05 PM UTC 25 |
| Peak memory | 228516 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3163609316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.3163609316 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all.1442226139 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 394253908 ps |
| CPU time | 51.74 seconds |
| Started | Feb 08 01:43:52 PM UTC 25 |
| Finished | Feb 08 01:44:45 PM UTC 25 |
| Peak memory | 227372 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1442226139 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all.1442226139 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_alert_test.2208102208 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 692777836 ps |
| CPU time | 12.95 seconds |
| Started | Feb 08 01:44:10 PM UTC 25 |
| Finished | Feb 08 01:44:24 PM UTC 25 |
| Peak memory | 227608 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2208102208 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ct rl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.2208102208 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.1856247677 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 42703171994 ps |
| CPU time | 248.28 seconds |
| Started | Feb 08 01:44:05 PM UTC 25 |
| Finished | Feb 08 01:48:17 PM UTC 25 |
| Peak memory | 257360 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1856247677 -assert nopostproc +UVM_TESTNAME=rom_c trl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_corrupt_sig_fatal_chk.1856247677 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_kmac_err_chk.533842177 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 348419519 ps |
| CPU time | 20.09 seconds |
| Started | Feb 08 01:44:05 PM UTC 25 |
| Finished | Feb 08 01:44:27 PM UTC 25 |
| Peak memory | 228460 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=533842177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.533842177 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_max_throughput_chk.1785641693 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 534675860 ps |
| CPU time | 14.99 seconds |
| Started | Feb 08 01:44:04 PM UTC 25 |
| Finished | Feb 08 01:44:20 PM UTC 25 |
| Peak memory | 228452 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1785641693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.1785641693 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all.897337899 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 562408423 ps |
| CPU time | 44.52 seconds |
| Started | Feb 08 01:44:04 PM UTC 25 |
| Finished | Feb 08 01:44:50 PM UTC 25 |
| Peak memory | 228520 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=897337899 -assert no postproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all.897337899 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_alert_test.3749669505 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 1234901256 ps |
| CPU time | 14.76 seconds |
| Started | Feb 08 01:44:28 PM UTC 25 |
| Finished | Feb 08 01:44:44 PM UTC 25 |
| Peak memory | 227680 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749669505 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ct rl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.3749669505 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.1070497779 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 48389086469 ps |
| CPU time | 268.46 seconds |
| Started | Feb 08 01:44:20 PM UTC 25 |
| Finished | Feb 08 01:48:52 PM UTC 25 |
| Peak memory | 257456 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1070497779 -assert nopostproc +UVM_TESTNAME=rom_c trl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_corrupt_sig_fatal_chk.1070497779 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_kmac_err_chk.238157804 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 347642359 ps |
| CPU time | 20.61 seconds |
| Started | Feb 08 01:44:22 PM UTC 25 |
| Finished | Feb 08 01:44:44 PM UTC 25 |
| Peak memory | 228460 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=238157804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.238157804 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_max_throughput_chk.3408798077 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 525502151 ps |
| CPU time | 12.7 seconds |
| Started | Feb 08 01:44:15 PM UTC 25 |
| Finished | Feb 08 01:44:29 PM UTC 25 |
| Peak memory | 228452 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3408798077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.3408798077 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all.1015591135 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 2277527736 ps |
| CPU time | 40.68 seconds |
| Started | Feb 08 01:44:12 PM UTC 25 |
| Finished | Feb 08 01:44:55 PM UTC 25 |
| Peak memory | 228524 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1015591135 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all.1015591135 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_alert_test.1959654177 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 1377003825 ps |
| CPU time | 8.73 seconds |
| Started | Feb 08 01:39:28 PM UTC 25 |
| Finished | Feb 08 01:39:38 PM UTC 25 |
| Peak memory | 227600 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1959654177 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ct rl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.1959654177 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.829583274 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 4413796074 ps |
| CPU time | 276.9 seconds |
| Started | Feb 08 01:39:20 PM UTC 25 |
| Finished | Feb 08 01:44:00 PM UTC 25 |
| Peak memory | 246156 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=829583274 -assert nopostproc +UVM_TESTNAME=rom_ct rl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_corrupt_sig_fatal_chk.829583274 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_kmac_err_chk.2418931100 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 5500496261 ps |
| CPU time | 24.43 seconds |
| Started | Feb 08 01:39:21 PM UTC 25 |
| Finished | Feb 08 01:39:46 PM UTC 25 |
| Peak memory | 228520 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2418931100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.2418931100 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_max_throughput_chk.2536285096 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 185345600 ps |
| CPU time | 11.41 seconds |
| Started | Feb 08 01:39:15 PM UTC 25 |
| Finished | Feb 08 01:39:28 PM UTC 25 |
| Peak memory | 228508 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2536285096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.2536285096 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_smoke.1490032480 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 186734610 ps |
| CPU time | 13.65 seconds |
| Started | Feb 08 01:39:14 PM UTC 25 |
| Finished | Feb 08 01:39:29 PM UTC 25 |
| Peak memory | 228532 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1490032480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.1490032480 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.3652916444 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 43870483097 ps |
| CPU time | 2017.39 seconds |
| Started | Feb 08 01:39:26 PM UTC 25 |
| Finished | Feb 08 02:13:25 PM UTC 25 |
| Peak memory | 262508 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom _ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3652916444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl _stress_all_with_rand_reset.3652916444 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_alert_test.1596166400 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 254992672 ps |
| CPU time | 11.79 seconds |
| Started | Feb 08 01:44:51 PM UTC 25 |
| Finished | Feb 08 01:45:04 PM UTC 25 |
| Peak memory | 227624 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1596166400 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ct rl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.1596166400 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/20.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.2542001698 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 16347391453 ps |
| CPU time | 248.72 seconds |
| Started | Feb 08 01:44:44 PM UTC 25 |
| Finished | Feb 08 01:48:56 PM UTC 25 |
| Peak memory | 256360 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2542001698 -assert nopostproc +UVM_TESTNAME=rom_c trl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_corrupt_sig_fatal_chk.2542001698 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/20.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_kmac_err_chk.2557488007 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 688992963 ps |
| CPU time | 26.07 seconds |
| Started | Feb 08 01:44:45 PM UTC 25 |
| Finished | Feb 08 01:45:12 PM UTC 25 |
| Peak memory | 225332 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2557488007 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.2557488007 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/20.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_max_throughput_chk.2694669574 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 274270582 ps |
| CPU time | 17.19 seconds |
| Started | Feb 08 01:44:34 PM UTC 25 |
| Finished | Feb 08 01:44:52 PM UTC 25 |
| Peak memory | 228516 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694669574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.2694669574 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/20.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all.575172546 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 706133229 ps |
| CPU time | 27.8 seconds |
| Started | Feb 08 01:44:30 PM UTC 25 |
| Finished | Feb 08 01:44:59 PM UTC 25 |
| Peak memory | 228520 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575172546 -assert no postproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all.575172546 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/20.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.1025267774 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 51380032009 ps |
| CPU time | 2503.2 seconds |
| Started | Feb 08 01:44:46 PM UTC 25 |
| Finished | Feb 08 02:26:57 PM UTC 25 |
| Peak memory | 248172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom _ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1025267774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctr l_stress_all_with_rand_reset.1025267774 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/20.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_alert_test.1372964896 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 260834340 ps |
| CPU time | 15.9 seconds |
| Started | Feb 08 01:45:09 PM UTC 25 |
| Finished | Feb 08 01:45:26 PM UTC 25 |
| Peak memory | 227640 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1372964896 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ct rl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.1372964896 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/21.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.2080040486 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 17673328795 ps |
| CPU time | 252.31 seconds |
| Started | Feb 08 01:45:00 PM UTC 25 |
| Finished | Feb 08 01:49:17 PM UTC 25 |
| Peak memory | 228044 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2080040486 -assert nopostproc +UVM_TESTNAME=rom_c trl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_corrupt_sig_fatal_chk.2080040486 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/21.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_kmac_err_chk.983603866 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 675671588 ps |
| CPU time | 23.14 seconds |
| Started | Feb 08 01:45:04 PM UTC 25 |
| Finished | Feb 08 01:45:29 PM UTC 25 |
| Peak memory | 228456 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=983603866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.983603866 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/21.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_max_throughput_chk.384798510 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 259416696 ps |
| CPU time | 15.12 seconds |
| Started | Feb 08 01:44:55 PM UTC 25 |
| Finished | Feb 08 01:45:12 PM UTC 25 |
| Peak memory | 228444 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=384798510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.384798510 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/21.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all.1086108798 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 1100722753 ps |
| CPU time | 30.52 seconds |
| Started | Feb 08 01:44:53 PM UTC 25 |
| Finished | Feb 08 01:45:26 PM UTC 25 |
| Peak memory | 228588 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1086108798 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all.1086108798 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/21.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_alert_test.1337516305 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 506855679 ps |
| CPU time | 13.78 seconds |
| Started | Feb 08 01:45:27 PM UTC 25 |
| Finished | Feb 08 01:45:42 PM UTC 25 |
| Peak memory | 227704 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1337516305 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ct rl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.1337516305 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/22.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.1414184161 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 4876152651 ps |
| CPU time | 267.12 seconds |
| Started | Feb 08 01:45:19 PM UTC 25 |
| Finished | Feb 08 01:49:50 PM UTC 25 |
| Peak memory | 228460 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1414184161 -assert nopostproc +UVM_TESTNAME=rom_c trl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_corrupt_sig_fatal_chk.1414184161 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/22.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_kmac_err_chk.3690307242 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 1414355807 ps |
| CPU time | 26.03 seconds |
| Started | Feb 08 01:45:23 PM UTC 25 |
| Finished | Feb 08 01:45:51 PM UTC 25 |
| Peak memory | 228532 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3690307242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.3690307242 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/22.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_max_throughput_chk.1145922078 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 178664442 ps |
| CPU time | 15.18 seconds |
| Started | Feb 08 01:45:14 PM UTC 25 |
| Finished | Feb 08 01:45:30 PM UTC 25 |
| Peak memory | 228452 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1145922078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.1145922078 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/22.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all.2770309291 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 1118668902 ps |
| CPU time | 47.3 seconds |
| Started | Feb 08 01:45:13 PM UTC 25 |
| Finished | Feb 08 01:46:02 PM UTC 25 |
| Peak memory | 228584 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2770309291 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all.2770309291 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/22.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.2155249730 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 53019181753 ps |
| CPU time | 923.65 seconds |
| Started | Feb 08 01:45:24 PM UTC 25 |
| Finished | Feb 08 02:00:58 PM UTC 25 |
| Peak memory | 245028 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom _ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=2155249730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctr l_stress_all_with_rand_reset.2155249730 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/22.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_alert_test.3532493278 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 2368091465 ps |
| CPU time | 12.38 seconds |
| Started | Feb 08 01:45:49 PM UTC 25 |
| Finished | Feb 08 01:46:03 PM UTC 25 |
| Peak memory | 227656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3532493278 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ct rl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.3532493278 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/23.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.4202922778 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 8995503788 ps |
| CPU time | 262.81 seconds |
| Started | Feb 08 01:45:31 PM UTC 25 |
| Finished | Feb 08 01:49:58 PM UTC 25 |
| Peak memory | 256392 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4202922778 -assert nopostproc +UVM_TESTNAME=rom_c trl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_corrupt_sig_fatal_chk.4202922778 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/23.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_kmac_err_chk.1498613505 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 519221497 ps |
| CPU time | 32.49 seconds |
| Started | Feb 08 01:45:35 PM UTC 25 |
| Finished | Feb 08 01:46:09 PM UTC 25 |
| Peak memory | 227380 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1498613505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.1498613505 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/23.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_max_throughput_chk.2725572743 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 264401664 ps |
| CPU time | 16.75 seconds |
| Started | Feb 08 01:45:30 PM UTC 25 |
| Finished | Feb 08 01:45:48 PM UTC 25 |
| Peak memory | 228452 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725572743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.2725572743 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/23.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all.3853827457 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 385037110 ps |
| CPU time | 38.15 seconds |
| Started | Feb 08 01:45:27 PM UTC 25 |
| Finished | Feb 08 01:46:07 PM UTC 25 |
| Peak memory | 228460 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3853827457 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all.3853827457 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/23.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_alert_test.4248615957 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 250017911 ps |
| CPU time | 15.6 seconds |
| Started | Feb 08 01:46:19 PM UTC 25 |
| Finished | Feb 08 01:46:36 PM UTC 25 |
| Peak memory | 227560 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4248615957 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ct rl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.4248615957 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/24.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.865776131 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 7131966734 ps |
| CPU time | 300.17 seconds |
| Started | Feb 08 01:46:04 PM UTC 25 |
| Finished | Feb 08 01:51:08 PM UTC 25 |
| Peak memory | 246156 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=865776131 -assert nopostproc +UVM_TESTNAME=rom_ct rl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_corrupt_sig_fatal_chk.865776131 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/24.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_kmac_err_chk.3716237406 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 2467401808 ps |
| CPU time | 33.04 seconds |
| Started | Feb 08 01:46:08 PM UTC 25 |
| Finished | Feb 08 01:46:43 PM UTC 25 |
| Peak memory | 228580 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3716237406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.3716237406 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/24.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_max_throughput_chk.1218828666 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 1078576675 ps |
| CPU time | 16.93 seconds |
| Started | Feb 08 01:46:03 PM UTC 25 |
| Finished | Feb 08 01:46:21 PM UTC 25 |
| Peak memory | 228452 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218828666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.1218828666 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/24.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all.1511985524 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 376412453 ps |
| CPU time | 37.96 seconds |
| Started | Feb 08 01:45:52 PM UTC 25 |
| Finished | Feb 08 01:46:31 PM UTC 25 |
| Peak memory | 228460 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1511985524 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all.1511985524 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/24.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_alert_test.259433606 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 3644100585 ps |
| CPU time | 25.13 seconds |
| Started | Feb 08 01:46:44 PM UTC 25 |
| Finished | Feb 08 01:47:11 PM UTC 25 |
| Peak memory | 227560 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259433606 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctr l_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.259433606 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/25.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.4128116286 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 7300468231 ps |
| CPU time | 235.33 seconds |
| Started | Feb 08 01:46:37 PM UTC 25 |
| Finished | Feb 08 01:50:36 PM UTC 25 |
| Peak memory | 228840 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4128116286 -assert nopostproc +UVM_TESTNAME=rom_c trl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_corrupt_sig_fatal_chk.4128116286 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/25.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_kmac_err_chk.3667631227 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 1380694059 ps |
| CPU time | 21.98 seconds |
| Started | Feb 08 01:46:41 PM UTC 25 |
| Finished | Feb 08 01:47:05 PM UTC 25 |
| Peak memory | 228532 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667631227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.3667631227 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/25.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_max_throughput_chk.2057826262 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 727360604 ps |
| CPU time | 14.77 seconds |
| Started | Feb 08 01:46:32 PM UTC 25 |
| Finished | Feb 08 01:46:48 PM UTC 25 |
| Peak memory | 228452 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057826262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.2057826262 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/25.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all.3101235667 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 9254837187 ps |
| CPU time | 36.08 seconds |
| Started | Feb 08 01:46:22 PM UTC 25 |
| Finished | Feb 08 01:47:00 PM UTC 25 |
| Peak memory | 225452 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3101235667 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all.3101235667 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/25.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_alert_test.3427000551 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 1183811343 ps |
| CPU time | 14.03 seconds |
| Started | Feb 08 01:47:06 PM UTC 25 |
| Finished | Feb 08 01:47:21 PM UTC 25 |
| Peak memory | 227648 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3427000551 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ct rl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.3427000551 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/26.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.4110862652 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 5438192915 ps |
| CPU time | 308.3 seconds |
| Started | Feb 08 01:46:52 PM UTC 25 |
| Finished | Feb 08 01:52:04 PM UTC 25 |
| Peak memory | 257464 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4110862652 -assert nopostproc +UVM_TESTNAME=rom_c trl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_corrupt_sig_fatal_chk.4110862652 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/26.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_kmac_err_chk.1199778147 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 1376142290 ps |
| CPU time | 30.29 seconds |
| Started | Feb 08 01:47:01 PM UTC 25 |
| Finished | Feb 08 01:47:33 PM UTC 25 |
| Peak memory | 228532 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1199778147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.1199778147 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/26.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_max_throughput_chk.1085792134 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 1468717381 ps |
| CPU time | 15.01 seconds |
| Started | Feb 08 01:46:51 PM UTC 25 |
| Finished | Feb 08 01:47:07 PM UTC 25 |
| Peak memory | 228452 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1085792134 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.1085792134 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/26.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all.294853789 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 781837881 ps |
| CPU time | 32.1 seconds |
| Started | Feb 08 01:46:49 PM UTC 25 |
| Finished | Feb 08 01:47:23 PM UTC 25 |
| Peak memory | 228456 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=294853789 -assert no postproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all.294853789 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/26.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_alert_test.2350678896 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 756201630 ps |
| CPU time | 12.17 seconds |
| Started | Feb 08 01:47:36 PM UTC 25 |
| Finished | Feb 08 01:47:50 PM UTC 25 |
| Peak memory | 227528 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350678896 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ct rl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.2350678896 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/27.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.4148475158 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 2770166567 ps |
| CPU time | 165.61 seconds |
| Started | Feb 08 01:47:22 PM UTC 25 |
| Finished | Feb 08 01:50:11 PM UTC 25 |
| Peak memory | 259536 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4148475158 -assert nopostproc +UVM_TESTNAME=rom_c trl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_corrupt_sig_fatal_chk.4148475158 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/27.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_kmac_err_chk.432531152 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 8197942027 ps |
| CPU time | 55.06 seconds |
| Started | Feb 08 01:47:24 PM UTC 25 |
| Finished | Feb 08 01:48:21 PM UTC 25 |
| Peak memory | 228524 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=432531152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.432531152 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/27.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_max_throughput_chk.1434213576 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 1959855965 ps |
| CPU time | 22.36 seconds |
| Started | Feb 08 01:47:12 PM UTC 25 |
| Finished | Feb 08 01:47:36 PM UTC 25 |
| Peak memory | 227912 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1434213576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.1434213576 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/27.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all.1859632562 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 809752113 ps |
| CPU time | 39.67 seconds |
| Started | Feb 08 01:47:08 PM UTC 25 |
| Finished | Feb 08 01:47:49 PM UTC 25 |
| Peak memory | 228456 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1859632562 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all.1859632562 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/27.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_alert_test.2052127383 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 660425759 ps |
| CPU time | 12.88 seconds |
| Started | Feb 08 01:48:03 PM UTC 25 |
| Finished | Feb 08 01:48:17 PM UTC 25 |
| Peak memory | 227488 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2052127383 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ct rl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.2052127383 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/28.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.2829332814 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 5372129867 ps |
| CPU time | 285.27 seconds |
| Started | Feb 08 01:47:48 PM UTC 25 |
| Finished | Feb 08 01:52:37 PM UTC 25 |
| Peak memory | 245128 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2829332814 -assert nopostproc +UVM_TESTNAME=rom_c trl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_corrupt_sig_fatal_chk.2829332814 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/28.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_kmac_err_chk.276602877 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 4125987396 ps |
| CPU time | 31.36 seconds |
| Started | Feb 08 01:47:50 PM UTC 25 |
| Finished | Feb 08 01:48:22 PM UTC 25 |
| Peak memory | 227500 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276602877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.276602877 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/28.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_max_throughput_chk.751688999 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 731014738 ps |
| CPU time | 16.33 seconds |
| Started | Feb 08 01:47:44 PM UTC 25 |
| Finished | Feb 08 01:48:02 PM UTC 25 |
| Peak memory | 228444 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=751688999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.751688999 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/28.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all.2815696101 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 1112344543 ps |
| CPU time | 30.14 seconds |
| Started | Feb 08 01:47:43 PM UTC 25 |
| Finished | Feb 08 01:48:15 PM UTC 25 |
| Peak memory | 225324 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2815696101 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all.2815696101 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/28.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_alert_test.2918423892 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 689075809 ps |
| CPU time | 13.09 seconds |
| Started | Feb 08 01:48:37 PM UTC 25 |
| Finished | Feb 08 01:48:52 PM UTC 25 |
| Peak memory | 227632 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2918423892 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ct rl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.2918423892 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/29.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.562670352 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 14375958907 ps |
| CPU time | 180.01 seconds |
| Started | Feb 08 01:48:18 PM UTC 25 |
| Finished | Feb 08 01:51:21 PM UTC 25 |
| Peak memory | 245204 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562670352 -assert nopostproc +UVM_TESTNAME=rom_ct rl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_corrupt_sig_fatal_chk.562670352 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/29.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_kmac_err_chk.3634889270 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 497728361 ps |
| CPU time | 35.24 seconds |
| Started | Feb 08 01:48:22 PM UTC 25 |
| Finished | Feb 08 01:48:59 PM UTC 25 |
| Peak memory | 227508 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3634889270 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.3634889270 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/29.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_max_throughput_chk.3318559202 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 716399351 ps |
| CPU time | 16.95 seconds |
| Started | Feb 08 01:48:18 PM UTC 25 |
| Finished | Feb 08 01:48:36 PM UTC 25 |
| Peak memory | 228452 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3318559202 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.3318559202 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/29.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all.295362985 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 1119097314 ps |
| CPU time | 26.28 seconds |
| Started | Feb 08 01:48:16 PM UTC 25 |
| Finished | Feb 08 01:48:44 PM UTC 25 |
| Peak memory | 228520 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295362985 -assert no postproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all.295362985 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/29.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_alert_test.3702131729 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 6518952799 ps |
| CPU time | 14.94 seconds |
| Started | Feb 08 01:39:35 PM UTC 25 |
| Finished | Feb 08 01:39:51 PM UTC 25 |
| Peak memory | 227576 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3702131729 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ct rl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.3702131729 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.3202943556 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 32130774874 ps |
| CPU time | 238.76 seconds |
| Started | Feb 08 01:39:30 PM UTC 25 |
| Finished | Feb 08 01:43:32 PM UTC 25 |
| Peak memory | 246016 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3202943556 -assert nopostproc +UVM_TESTNAME=rom_c trl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_corrupt_sig_fatal_chk.3202943556 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_max_throughput_chk.2501619032 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 1998922714 ps |
| CPU time | 19.62 seconds |
| Started | Feb 08 01:39:29 PM UTC 25 |
| Finished | Feb 08 01:39:51 PM UTC 25 |
| Peak memory | 228444 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2501619032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.2501619032 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_sec_cm.2334121668 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 717341948 ps |
| CPU time | 165.25 seconds |
| Started | Feb 08 01:39:32 PM UTC 25 |
| Finished | Feb 08 01:42:21 PM UTC 25 |
| Peak memory | 256340 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334121668 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctr l_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.2334121668 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_smoke.642534848 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 1014981593 ps |
| CPU time | 14.56 seconds |
| Started | Feb 08 01:39:28 PM UTC 25 |
| Finished | Feb 08 01:39:44 PM UTC 25 |
| Peak memory | 228508 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=642534848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.642534848 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all.2552984465 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 2612451826 ps |
| CPU time | 34.94 seconds |
| Started | Feb 08 01:39:29 PM UTC 25 |
| Finished | Feb 08 01:40:06 PM UTC 25 |
| Peak memory | 228588 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2552984465 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all.2552984465 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.2541801826 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 19646683082 ps |
| CPU time | 958.93 seconds |
| Started | Feb 08 01:39:32 PM UTC 25 |
| Finished | Feb 08 01:55:43 PM UTC 25 |
| Peak memory | 239980 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom _ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=2541801826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl _stress_all_with_rand_reset.2541801826 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_alert_test.2562311827 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 174681773 ps |
| CPU time | 11.45 seconds |
| Started | Feb 08 01:48:57 PM UTC 25 |
| Finished | Feb 08 01:49:09 PM UTC 25 |
| Peak memory | 227736 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2562311827 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ct rl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.2562311827 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/30.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.567390920 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 2874669723 ps |
| CPU time | 238.62 seconds |
| Started | Feb 08 01:48:52 PM UTC 25 |
| Finished | Feb 08 01:52:55 PM UTC 25 |
| Peak memory | 259516 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=567390920 -assert nopostproc +UVM_TESTNAME=rom_ct rl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_corrupt_sig_fatal_chk.567390920 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/30.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_kmac_err_chk.299878039 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 5312152886 ps |
| CPU time | 48.27 seconds |
| Started | Feb 08 01:48:52 PM UTC 25 |
| Finished | Feb 08 01:49:43 PM UTC 25 |
| Peak memory | 228652 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=299878039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.299878039 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/30.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_max_throughput_chk.295509225 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 529922553 ps |
| CPU time | 12.64 seconds |
| Started | Feb 08 01:48:47 PM UTC 25 |
| Finished | Feb 08 01:49:01 PM UTC 25 |
| Peak memory | 228572 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295509225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.295509225 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/30.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all.608037713 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 548578682 ps |
| CPU time | 38.43 seconds |
| Started | Feb 08 01:48:44 PM UTC 25 |
| Finished | Feb 08 01:49:24 PM UTC 25 |
| Peak memory | 228456 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=608037713 -assert no postproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all.608037713 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/30.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.747874692 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 208740816106 ps |
| CPU time | 2635.36 seconds |
| Started | Feb 08 01:48:55 PM UTC 25 |
| Finished | Feb 08 02:33:19 PM UTC 25 |
| Peak memory | 262508 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom _ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=747874692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl _stress_all_with_rand_reset.747874692 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/30.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_alert_test.2403824634 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 1542883252 ps |
| CPU time | 15.05 seconds |
| Started | Feb 08 01:49:21 PM UTC 25 |
| Finished | Feb 08 01:49:37 PM UTC 25 |
| Peak memory | 227600 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403824634 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ct rl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.2403824634 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/31.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.426530704 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 13563647096 ps |
| CPU time | 348.56 seconds |
| Started | Feb 08 01:49:10 PM UTC 25 |
| Finished | Feb 08 01:55:03 PM UTC 25 |
| Peak memory | 258444 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426530704 -assert nopostproc +UVM_TESTNAME=rom_ct rl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_corrupt_sig_fatal_chk.426530704 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/31.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_kmac_err_chk.259605615 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 332195309 ps |
| CPU time | 19.91 seconds |
| Started | Feb 08 01:49:18 PM UTC 25 |
| Finished | Feb 08 01:49:39 PM UTC 25 |
| Peak memory | 227896 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259605615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.259605615 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/31.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_max_throughput_chk.1083106953 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 1910810917 ps |
| CPU time | 17.21 seconds |
| Started | Feb 08 01:49:02 PM UTC 25 |
| Finished | Feb 08 01:49:20 PM UTC 25 |
| Peak memory | 228452 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1083106953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.1083106953 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/31.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_stress_all.234476489 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 372447090 ps |
| CPU time | 28.54 seconds |
| Started | Feb 08 01:49:00 PM UTC 25 |
| Finished | Feb 08 01:49:30 PM UTC 25 |
| Peak memory | 227368 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234476489 -assert no postproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all.234476489 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/31.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_alert_test.3488551665 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 2057936655 ps |
| CPU time | 14.57 seconds |
| Started | Feb 08 01:49:40 PM UTC 25 |
| Finished | Feb 08 01:49:56 PM UTC 25 |
| Peak memory | 227608 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3488551665 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ct rl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.3488551665 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/32.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.855913530 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 3137912374 ps |
| CPU time | 249.47 seconds |
| Started | Feb 08 01:49:32 PM UTC 25 |
| Finished | Feb 08 01:53:45 PM UTC 25 |
| Peak memory | 259540 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=855913530 -assert nopostproc +UVM_TESTNAME=rom_ct rl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_corrupt_sig_fatal_chk.855913530 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/32.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_kmac_err_chk.2970756897 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 502235214 ps |
| CPU time | 23.68 seconds |
| Started | Feb 08 01:49:32 PM UTC 25 |
| Finished | Feb 08 01:49:57 PM UTC 25 |
| Peak memory | 228532 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2970756897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.2970756897 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/32.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_max_throughput_chk.2528061140 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 685995839 ps |
| CPU time | 15.88 seconds |
| Started | Feb 08 01:49:31 PM UTC 25 |
| Finished | Feb 08 01:49:48 PM UTC 25 |
| Peak memory | 228580 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2528061140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.2528061140 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/32.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all.1057139878 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 347875824 ps |
| CPU time | 18.7 seconds |
| Started | Feb 08 01:49:25 PM UTC 25 |
| Finished | Feb 08 01:49:45 PM UTC 25 |
| Peak memory | 228364 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1057139878 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all.1057139878 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/32.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_alert_test.2347556118 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 257660868 ps |
| CPU time | 13.72 seconds |
| Started | Feb 08 01:49:57 PM UTC 25 |
| Finished | Feb 08 01:50:12 PM UTC 25 |
| Peak memory | 227536 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2347556118 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ct rl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.2347556118 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/33.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.4264841430 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 46614560080 ps |
| CPU time | 396.78 seconds |
| Started | Feb 08 01:49:50 PM UTC 25 |
| Finished | Feb 08 01:56:32 PM UTC 25 |
| Peak memory | 257356 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264841430 -assert nopostproc +UVM_TESTNAME=rom_c trl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_corrupt_sig_fatal_chk.4264841430 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/33.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_kmac_err_chk.3184506813 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 338930117 ps |
| CPU time | 29.67 seconds |
| Started | Feb 08 01:49:51 PM UTC 25 |
| Finished | Feb 08 01:50:22 PM UTC 25 |
| Peak memory | 228464 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184506813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.3184506813 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/33.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_max_throughput_chk.2222058646 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 1024656031 ps |
| CPU time | 16.41 seconds |
| Started | Feb 08 01:49:46 PM UTC 25 |
| Finished | Feb 08 01:50:04 PM UTC 25 |
| Peak memory | 228452 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2222058646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.2222058646 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/33.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all.186140662 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 1037708669 ps |
| CPU time | 18.14 seconds |
| Started | Feb 08 01:49:44 PM UTC 25 |
| Finished | Feb 08 01:50:03 PM UTC 25 |
| Peak memory | 228508 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=186140662 -assert no postproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all.186140662 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/33.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_alert_test.3832652796 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 223727812 ps |
| CPU time | 12.69 seconds |
| Started | Feb 08 01:50:07 PM UTC 25 |
| Finished | Feb 08 01:50:21 PM UTC 25 |
| Peak memory | 227608 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3832652796 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ct rl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.3832652796 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/34.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.144322159 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 8630245489 ps |
| CPU time | 327.81 seconds |
| Started | Feb 08 01:49:59 PM UTC 25 |
| Finished | Feb 08 01:55:32 PM UTC 25 |
| Peak memory | 257492 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144322159 -assert nopostproc +UVM_TESTNAME=rom_ct rl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_corrupt_sig_fatal_chk.144322159 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/34.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_kmac_err_chk.2442898156 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 1327103987 ps |
| CPU time | 19.6 seconds |
| Started | Feb 08 01:50:04 PM UTC 25 |
| Finished | Feb 08 01:50:25 PM UTC 25 |
| Peak memory | 228468 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2442898156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.2442898156 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/34.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_max_throughput_chk.605887211 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 718617749 ps |
| CPU time | 14.12 seconds |
| Started | Feb 08 01:49:58 PM UTC 25 |
| Finished | Feb 08 01:50:14 PM UTC 25 |
| Peak memory | 228508 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605887211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.605887211 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/34.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all.796817306 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 1569555138 ps |
| CPU time | 39.22 seconds |
| Started | Feb 08 01:49:58 PM UTC 25 |
| Finished | Feb 08 01:50:39 PM UTC 25 |
| Peak memory | 228520 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=796817306 -assert no postproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all.796817306 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/34.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_alert_test.1387109734 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 169333413 ps |
| CPU time | 13.2 seconds |
| Started | Feb 08 01:50:26 PM UTC 25 |
| Finished | Feb 08 01:50:40 PM UTC 25 |
| Peak memory | 227640 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387109734 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ct rl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.1387109734 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/35.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.1721274793 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 3749994770 ps |
| CPU time | 224.93 seconds |
| Started | Feb 08 01:50:15 PM UTC 25 |
| Finished | Feb 08 01:54:03 PM UTC 25 |
| Peak memory | 257456 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1721274793 -assert nopostproc +UVM_TESTNAME=rom_c trl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_corrupt_sig_fatal_chk.1721274793 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/35.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_kmac_err_chk.855124862 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 496748964 ps |
| CPU time | 35.54 seconds |
| Started | Feb 08 01:50:23 PM UTC 25 |
| Finished | Feb 08 01:51:00 PM UTC 25 |
| Peak memory | 228524 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=855124862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.855124862 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/35.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_max_throughput_chk.196126794 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 255126933 ps |
| CPU time | 14.95 seconds |
| Started | Feb 08 01:50:12 PM UTC 25 |
| Finished | Feb 08 01:50:29 PM UTC 25 |
| Peak memory | 228444 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=196126794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.196126794 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/35.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all.530247756 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 524816402 ps |
| CPU time | 38.74 seconds |
| Started | Feb 08 01:50:11 PM UTC 25 |
| Finished | Feb 08 01:50:52 PM UTC 25 |
| Peak memory | 228456 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=530247756 -assert no postproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all.530247756 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/35.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_alert_test.34352135 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 203501847 ps |
| CPU time | 10.6 seconds |
| Started | Feb 08 01:50:48 PM UTC 25 |
| Finished | Feb 08 01:51:00 PM UTC 25 |
| Peak memory | 227556 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34352135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_ base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl _64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.34352135 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/36.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.791917591 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 2742423327 ps |
| CPU time | 296.06 seconds |
| Started | Feb 08 01:50:40 PM UTC 25 |
| Finished | Feb 08 01:55:41 PM UTC 25 |
| Peak memory | 259540 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791917591 -assert nopostproc +UVM_TESTNAME=rom_ct rl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_corrupt_sig_fatal_chk.791917591 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/36.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_kmac_err_chk.4019912553 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 690672225 ps |
| CPU time | 19 seconds |
| Started | Feb 08 01:50:41 PM UTC 25 |
| Finished | Feb 08 01:51:01 PM UTC 25 |
| Peak memory | 228468 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4019912553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.4019912553 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/36.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_max_throughput_chk.2705021994 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 264310660 ps |
| CPU time | 16.85 seconds |
| Started | Feb 08 01:50:37 PM UTC 25 |
| Finished | Feb 08 01:50:55 PM UTC 25 |
| Peak memory | 228452 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2705021994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.2705021994 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/36.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all.3817458459 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 1978427986 ps |
| CPU time | 36.7 seconds |
| Started | Feb 08 01:50:30 PM UTC 25 |
| Finished | Feb 08 01:51:08 PM UTC 25 |
| Peak memory | 228584 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3817458459 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all.3817458459 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/36.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_alert_test.3942212336 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 496215302 ps |
| CPU time | 13.25 seconds |
| Started | Feb 08 01:51:09 PM UTC 25 |
| Finished | Feb 08 01:51:23 PM UTC 25 |
| Peak memory | 227600 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3942212336 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ct rl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.3942212336 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/37.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.993924201 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 17012299654 ps |
| CPU time | 237.69 seconds |
| Started | Feb 08 01:51:00 PM UTC 25 |
| Finished | Feb 08 01:55:02 PM UTC 25 |
| Peak memory | 257356 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=993924201 -assert nopostproc +UVM_TESTNAME=rom_ct rl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_corrupt_sig_fatal_chk.993924201 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/37.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_kmac_err_chk.4095344414 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 2472746048 ps |
| CPU time | 27.97 seconds |
| Started | Feb 08 01:51:00 PM UTC 25 |
| Finished | Feb 08 01:51:30 PM UTC 25 |
| Peak memory | 227444 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095344414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.4095344414 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/37.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_max_throughput_chk.1139513901 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 752922911 ps |
| CPU time | 14.12 seconds |
| Started | Feb 08 01:50:56 PM UTC 25 |
| Finished | Feb 08 01:51:12 PM UTC 25 |
| Peak memory | 228516 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139513901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.1139513901 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/37.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all.2643554939 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 1509547151 ps |
| CPU time | 27.09 seconds |
| Started | Feb 08 01:50:52 PM UTC 25 |
| Finished | Feb 08 01:51:21 PM UTC 25 |
| Peak memory | 228456 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2643554939 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all.2643554939 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/37.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_alert_test.1847399896 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 515880947 ps |
| CPU time | 15.54 seconds |
| Started | Feb 08 01:51:30 PM UTC 25 |
| Finished | Feb 08 01:51:47 PM UTC 25 |
| Peak memory | 227672 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847399896 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ct rl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.1847399896 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/38.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.435528833 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 1799464093 ps |
| CPU time | 167.57 seconds |
| Started | Feb 08 01:51:22 PM UTC 25 |
| Finished | Feb 08 01:54:12 PM UTC 25 |
| Peak memory | 244556 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=435528833 -assert nopostproc +UVM_TESTNAME=rom_ct rl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_corrupt_sig_fatal_chk.435528833 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/38.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_kmac_err_chk.4222822851 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 3938539705 ps |
| CPU time | 45.72 seconds |
| Started | Feb 08 01:51:22 PM UTC 25 |
| Finished | Feb 08 01:52:09 PM UTC 25 |
| Peak memory | 228596 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4222822851 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.4222822851 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/38.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_max_throughput_chk.1652745116 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 188187697 ps |
| CPU time | 15.2 seconds |
| Started | Feb 08 01:51:13 PM UTC 25 |
| Finished | Feb 08 01:51:29 PM UTC 25 |
| Peak memory | 228452 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1652745116 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.1652745116 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/38.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all.1022311163 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 2143230075 ps |
| CPU time | 47.54 seconds |
| Started | Feb 08 01:51:10 PM UTC 25 |
| Finished | Feb 08 01:51:59 PM UTC 25 |
| Peak memory | 228460 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1022311163 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all.1022311163 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/38.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_alert_test.3191532416 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 992711116 ps |
| CPU time | 13.43 seconds |
| Started | Feb 08 01:52:02 PM UTC 25 |
| Finished | Feb 08 01:52:17 PM UTC 25 |
| Peak memory | 227560 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3191532416 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ct rl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.3191532416 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/39.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_kmac_err_chk.4196337657 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 498008132 ps |
| CPU time | 32.13 seconds |
| Started | Feb 08 01:51:59 PM UTC 25 |
| Finished | Feb 08 01:52:33 PM UTC 25 |
| Peak memory | 228468 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4196337657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.4196337657 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/39.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_max_throughput_chk.1321494182 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 577997133 ps |
| CPU time | 17.57 seconds |
| Started | Feb 08 01:51:44 PM UTC 25 |
| Finished | Feb 08 01:52:03 PM UTC 25 |
| Peak memory | 228452 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1321494182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.1321494182 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/39.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all.1547964808 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 767312407 ps |
| CPU time | 26.58 seconds |
| Started | Feb 08 01:51:31 PM UTC 25 |
| Finished | Feb 08 01:51:59 PM UTC 25 |
| Peak memory | 227372 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1547964808 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_stress_all.1547964808 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/39.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.709098215 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 89843961872 ps |
| CPU time | 1341.24 seconds |
| Started | Feb 08 01:52:00 PM UTC 25 |
| Finished | Feb 08 02:14:36 PM UTC 25 |
| Peak memory | 246192 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom _ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=709098215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl _stress_all_with_rand_reset.709098215 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/39.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_alert_test.1283154748 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 2760928085 ps |
| CPU time | 12.03 seconds |
| Started | Feb 08 01:39:55 PM UTC 25 |
| Finished | Feb 08 01:40:09 PM UTC 25 |
| Peak memory | 227648 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283154748 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ct rl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.1283154748 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_kmac_err_chk.2565323252 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 1970844038 ps |
| CPU time | 47.78 seconds |
| Started | Feb 08 01:39:52 PM UTC 25 |
| Finished | Feb 08 01:40:41 PM UTC 25 |
| Peak memory | 228456 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2565323252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.2565323252 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_sec_cm.3480336834 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 1167084927 ps |
| CPU time | 245.01 seconds |
| Started | Feb 08 01:39:54 PM UTC 25 |
| Finished | Feb 08 01:44:03 PM UTC 25 |
| Peak memory | 257300 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3480336834 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctr l_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.3480336834 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_smoke.3644506629 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 2504516233 ps |
| CPU time | 15.53 seconds |
| Started | Feb 08 01:39:39 PM UTC 25 |
| Finished | Feb 08 01:39:56 PM UTC 25 |
| Peak memory | 225396 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644506629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.3644506629 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all.2558435057 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 2090423129 ps |
| CPU time | 66.55 seconds |
| Started | Feb 08 01:39:43 PM UTC 25 |
| Finished | Feb 08 01:40:51 PM UTC 25 |
| Peak memory | 228524 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2558435057 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all.2558435057 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_alert_test.1703641602 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 347718022 ps |
| CPU time | 12.22 seconds |
| Started | Feb 08 01:52:34 PM UTC 25 |
| Finished | Feb 08 01:52:47 PM UTC 25 |
| Peak memory | 227608 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1703641602 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ct rl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.1703641602 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/40.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.1470578075 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 6283290535 ps |
| CPU time | 235.83 seconds |
| Started | Feb 08 01:52:10 PM UTC 25 |
| Finished | Feb 08 01:56:09 PM UTC 25 |
| Peak memory | 246128 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1470578075 -assert nopostproc +UVM_TESTNAME=rom_c trl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_corrupt_sig_fatal_chk.1470578075 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/40.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_kmac_err_chk.1623179210 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 1103026926 ps |
| CPU time | 31.89 seconds |
| Started | Feb 08 01:52:18 PM UTC 25 |
| Finished | Feb 08 01:52:51 PM UTC 25 |
| Peak memory | 228456 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1623179210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.1623179210 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/40.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_max_throughput_chk.967046899 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 1246670677 ps |
| CPU time | 16.69 seconds |
| Started | Feb 08 01:52:04 PM UTC 25 |
| Finished | Feb 08 01:52:23 PM UTC 25 |
| Peak memory | 228508 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967046899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.967046899 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/40.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all.2812314516 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 2943685589 ps |
| CPU time | 54.62 seconds |
| Started | Feb 08 01:52:03 PM UTC 25 |
| Finished | Feb 08 01:53:00 PM UTC 25 |
| Peak memory | 228524 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2812314516 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all.2812314516 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/40.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_alert_test.1724190679 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 1033555948 ps |
| CPU time | 15.63 seconds |
| Started | Feb 08 01:52:55 PM UTC 25 |
| Finished | Feb 08 01:53:12 PM UTC 25 |
| Peak memory | 227536 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1724190679 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ct rl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.1724190679 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/41.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.2951739235 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 8085551194 ps |
| CPU time | 115.01 seconds |
| Started | Feb 08 01:52:48 PM UTC 25 |
| Finished | Feb 08 01:54:45 PM UTC 25 |
| Peak memory | 246828 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2951739235 -assert nopostproc +UVM_TESTNAME=rom_c trl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_corrupt_sig_fatal_chk.2951739235 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/41.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_kmac_err_chk.2292566823 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 333368805 ps |
| CPU time | 30.6 seconds |
| Started | Feb 08 01:52:51 PM UTC 25 |
| Finished | Feb 08 01:53:23 PM UTC 25 |
| Peak memory | 228528 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292566823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.2292566823 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/41.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_max_throughput_chk.1587433115 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 1474266161 ps |
| CPU time | 10.6 seconds |
| Started | Feb 08 01:52:38 PM UTC 25 |
| Finished | Feb 08 01:52:50 PM UTC 25 |
| Peak memory | 228452 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1587433115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.1587433115 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/41.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all.4222410048 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 2267406696 ps |
| CPU time | 52.47 seconds |
| Started | Feb 08 01:52:36 PM UTC 25 |
| Finished | Feb 08 01:53:30 PM UTC 25 |
| Peak memory | 228524 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4222410048 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all.4222410048 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/41.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_alert_test.3023654522 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 1237637604 ps |
| CPU time | 13.89 seconds |
| Started | Feb 08 01:53:47 PM UTC 25 |
| Finished | Feb 08 01:54:02 PM UTC 25 |
| Peak memory | 227688 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3023654522 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ct rl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.3023654522 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/42.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.1530482774 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 3563693540 ps |
| CPU time | 286.14 seconds |
| Started | Feb 08 01:53:24 PM UTC 25 |
| Finished | Feb 08 01:58:15 PM UTC 25 |
| Peak memory | 259536 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1530482774 -assert nopostproc +UVM_TESTNAME=rom_c trl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_corrupt_sig_fatal_chk.1530482774 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/42.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_kmac_err_chk.3245512210 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 1744276159 ps |
| CPU time | 27.71 seconds |
| Started | Feb 08 01:53:30 PM UTC 25 |
| Finished | Feb 08 01:54:00 PM UTC 25 |
| Peak memory | 228468 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3245512210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.3245512210 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/42.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_max_throughput_chk.588369539 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 1068476783 ps |
| CPU time | 18.93 seconds |
| Started | Feb 08 01:53:13 PM UTC 25 |
| Finished | Feb 08 01:53:34 PM UTC 25 |
| Peak memory | 228444 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=588369539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.588369539 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/42.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all.2784224778 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 2472331148 ps |
| CPU time | 56.86 seconds |
| Started | Feb 08 01:53:00 PM UTC 25 |
| Finished | Feb 08 01:53:59 PM UTC 25 |
| Peak memory | 228524 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2784224778 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all.2784224778 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/42.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_alert_test.3381114842 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 338502243 ps |
| CPU time | 11.8 seconds |
| Started | Feb 08 01:54:13 PM UTC 25 |
| Finished | Feb 08 01:54:26 PM UTC 25 |
| Peak memory | 227784 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381114842 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ct rl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.3381114842 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/43.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.307183373 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 43741235175 ps |
| CPU time | 298.58 seconds |
| Started | Feb 08 01:54:03 PM UTC 25 |
| Finished | Feb 08 01:59:05 PM UTC 25 |
| Peak memory | 228244 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=307183373 -assert nopostproc +UVM_TESTNAME=rom_ct rl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_corrupt_sig_fatal_chk.307183373 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/43.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_kmac_err_chk.3651691931 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 1058895225 ps |
| CPU time | 24.15 seconds |
| Started | Feb 08 01:54:04 PM UTC 25 |
| Finished | Feb 08 01:54:29 PM UTC 25 |
| Peak memory | 228468 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3651691931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.3651691931 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/43.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_max_throughput_chk.4168065664 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 357320584 ps |
| CPU time | 10.47 seconds |
| Started | Feb 08 01:54:01 PM UTC 25 |
| Finished | Feb 08 01:54:12 PM UTC 25 |
| Peak memory | 228452 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4168065664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.4168065664 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/43.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all.972159236 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 804655860 ps |
| CPU time | 28.44 seconds |
| Started | Feb 08 01:54:00 PM UTC 25 |
| Finished | Feb 08 01:54:30 PM UTC 25 |
| Peak memory | 228456 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=972159236 -assert no postproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all.972159236 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/43.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.3494501867 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 20892582983 ps |
| CPU time | 9273.62 seconds |
| Started | Feb 08 01:54:13 PM UTC 25 |
| Finished | Feb 08 04:29:55 PM UTC 25 |
| Peak memory | 244124 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom _ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3494501867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctr l_stress_all_with_rand_reset.3494501867 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/43.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_alert_test.847907440 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 1080394712 ps |
| CPU time | 14.77 seconds |
| Started | Feb 08 01:55:02 PM UTC 25 |
| Finished | Feb 08 01:55:19 PM UTC 25 |
| Peak memory | 227552 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=847907440 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctr l_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.847907440 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/44.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.4282061927 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 25845454659 ps |
| CPU time | 432.25 seconds |
| Started | Feb 08 01:54:30 PM UTC 25 |
| Finished | Feb 08 02:01:48 PM UTC 25 |
| Peak memory | 259536 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4282061927 -assert nopostproc +UVM_TESTNAME=rom_c trl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_corrupt_sig_fatal_chk.4282061927 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/44.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_kmac_err_chk.4237889503 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 1438924727 ps |
| CPU time | 26.68 seconds |
| Started | Feb 08 01:54:46 PM UTC 25 |
| Finished | Feb 08 01:55:14 PM UTC 25 |
| Peak memory | 228468 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4237889503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.4237889503 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/44.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_max_throughput_chk.3403975057 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 187567674 ps |
| CPU time | 16.41 seconds |
| Started | Feb 08 01:54:30 PM UTC 25 |
| Finished | Feb 08 01:54:48 PM UTC 25 |
| Peak memory | 228452 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3403975057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.3403975057 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/44.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all.1366230897 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 563656911 ps |
| CPU time | 42.24 seconds |
| Started | Feb 08 01:54:27 PM UTC 25 |
| Finished | Feb 08 01:55:11 PM UTC 25 |
| Peak memory | 228524 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1366230897 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all.1366230897 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/44.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_alert_test.3587677371 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 1902146061 ps |
| CPU time | 15.09 seconds |
| Started | Feb 08 01:55:30 PM UTC 25 |
| Finished | Feb 08 01:55:46 PM UTC 25 |
| Peak memory | 227688 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3587677371 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ct rl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.3587677371 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/45.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.1268790046 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 18401894676 ps |
| CPU time | 393.64 seconds |
| Started | Feb 08 01:55:16 PM UTC 25 |
| Finished | Feb 08 02:01:55 PM UTC 25 |
| Peak memory | 258392 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1268790046 -assert nopostproc +UVM_TESTNAME=rom_c trl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_corrupt_sig_fatal_chk.1268790046 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/45.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_kmac_err_chk.345588335 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 3304699692 ps |
| CPU time | 26.06 seconds |
| Started | Feb 08 01:55:20 PM UTC 25 |
| Finished | Feb 08 01:55:47 PM UTC 25 |
| Peak memory | 228524 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=345588335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.345588335 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/45.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_max_throughput_chk.4090024318 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 181255149 ps |
| CPU time | 15.69 seconds |
| Started | Feb 08 01:55:12 PM UTC 25 |
| Finished | Feb 08 01:55:29 PM UTC 25 |
| Peak memory | 228452 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4090024318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.4090024318 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/45.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all.3077915099 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 396490413 ps |
| CPU time | 36.22 seconds |
| Started | Feb 08 01:55:04 PM UTC 25 |
| Finished | Feb 08 01:55:41 PM UTC 25 |
| Peak memory | 228460 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3077915099 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all.3077915099 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/45.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_alert_test.535335545 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 992738804 ps |
| CPU time | 13.88 seconds |
| Started | Feb 08 01:55:47 PM UTC 25 |
| Finished | Feb 08 01:56:03 PM UTC 25 |
| Peak memory | 227552 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=535335545 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctr l_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.535335545 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/46.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1491637394 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 4773166619 ps |
| CPU time | 270.68 seconds |
| Started | Feb 08 01:55:41 PM UTC 25 |
| Finished | Feb 08 02:00:16 PM UTC 25 |
| Peak memory | 259504 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1491637394 -assert nopostproc +UVM_TESTNAME=rom_c trl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_corrupt_sig_fatal_chk.1491637394 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/46.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_kmac_err_chk.3468800449 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 12258989241 ps |
| CPU time | 32.37 seconds |
| Started | Feb 08 01:55:42 PM UTC 25 |
| Finished | Feb 08 01:56:17 PM UTC 25 |
| Peak memory | 228500 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3468800449 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.3468800449 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/46.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_max_throughput_chk.1359197704 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 687690472 ps |
| CPU time | 16.3 seconds |
| Started | Feb 08 01:55:36 PM UTC 25 |
| Finished | Feb 08 01:55:54 PM UTC 25 |
| Peak memory | 228452 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1359197704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.1359197704 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/46.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all.1999980562 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 1500278530 ps |
| CPU time | 29.6 seconds |
| Started | Feb 08 01:55:32 PM UTC 25 |
| Finished | Feb 08 01:56:03 PM UTC 25 |
| Peak memory | 228436 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1999980562 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all.1999980562 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/46.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.1855411632 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 19707482577 ps |
| CPU time | 779.58 seconds |
| Started | Feb 08 01:55:43 PM UTC 25 |
| Finished | Feb 08 02:08:52 PM UTC 25 |
| Peak memory | 240908 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom _ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1855411632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctr l_stress_all_with_rand_reset.1855411632 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/46.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_alert_test.3027192571 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 356493021 ps |
| CPU time | 10.95 seconds |
| Started | Feb 08 01:56:12 PM UTC 25 |
| Finished | Feb 08 01:56:24 PM UTC 25 |
| Peak memory | 227640 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3027192571 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ct rl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.3027192571 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/47.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.575306902 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 32840197646 ps |
| CPU time | 615.72 seconds |
| Started | Feb 08 01:56:04 PM UTC 25 |
| Finished | Feb 08 02:06:27 PM UTC 25 |
| Peak memory | 228532 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575306902 -assert nopostproc +UVM_TESTNAME=rom_ct rl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_corrupt_sig_fatal_chk.575306902 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/47.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_kmac_err_chk.3226866704 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 1770912714 ps |
| CPU time | 26.32 seconds |
| Started | Feb 08 01:56:04 PM UTC 25 |
| Finished | Feb 08 01:56:32 PM UTC 25 |
| Peak memory | 228468 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3226866704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.3226866704 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/47.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_max_throughput_chk.3590942073 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 1072970435 ps |
| CPU time | 15.31 seconds |
| Started | Feb 08 01:55:55 PM UTC 25 |
| Finished | Feb 08 01:56:11 PM UTC 25 |
| Peak memory | 228452 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3590942073 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.3590942073 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/47.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all.1141068138 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 751121086 ps |
| CPU time | 26.54 seconds |
| Started | Feb 08 01:55:48 PM UTC 25 |
| Finished | Feb 08 01:56:17 PM UTC 25 |
| Peak memory | 228524 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1141068138 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all.1141068138 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/47.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.1742215966 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 224368428724 ps |
| CPU time | 2317.63 seconds |
| Started | Feb 08 01:56:10 PM UTC 25 |
| Finished | Feb 08 02:35:12 PM UTC 25 |
| Peak memory | 258412 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom _ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1742215966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctr l_stress_all_with_rand_reset.1742215966 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/47.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_alert_test.1735035159 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 507556670 ps |
| CPU time | 14.43 seconds |
| Started | Feb 08 01:56:36 PM UTC 25 |
| Finished | Feb 08 01:56:52 PM UTC 25 |
| Peak memory | 227536 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1735035159 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ct rl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.1735035159 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/48.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.72135248 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 4875987291 ps |
| CPU time | 395.37 seconds |
| Started | Feb 08 01:56:25 PM UTC 25 |
| Finished | Feb 08 02:03:05 PM UTC 25 |
| Peak memory | 258652 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=72135248 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_corrupt_sig_fatal_chk.72135248 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/48.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_kmac_err_chk.2414563451 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 396627433 ps |
| CPU time | 18.98 seconds |
| Started | Feb 08 01:56:32 PM UTC 25 |
| Finished | Feb 08 01:56:52 PM UTC 25 |
| Peak memory | 228456 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414563451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.2414563451 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/48.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_max_throughput_chk.1942443161 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 261600848 ps |
| CPU time | 16.29 seconds |
| Started | Feb 08 01:56:18 PM UTC 25 |
| Finished | Feb 08 01:56:36 PM UTC 25 |
| Peak memory | 228452 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942443161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.1942443161 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/48.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all.3170907912 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 349864033 ps |
| CPU time | 21.49 seconds |
| Started | Feb 08 01:56:17 PM UTC 25 |
| Finished | Feb 08 01:56:40 PM UTC 25 |
| Peak memory | 228300 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3170907912 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all.3170907912 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/48.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_alert_test.1813026155 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 169976736 ps |
| CPU time | 11.18 seconds |
| Started | Feb 08 01:57:11 PM UTC 25 |
| Finished | Feb 08 01:57:23 PM UTC 25 |
| Peak memory | 227728 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1813026155 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ct rl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.1813026155 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/49.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1754231932 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 15815892489 ps |
| CPU time | 288.48 seconds |
| Started | Feb 08 01:56:53 PM UTC 25 |
| Finished | Feb 08 02:01:46 PM UTC 25 |
| Peak memory | 261576 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754231932 -assert nopostproc +UVM_TESTNAME=rom_c trl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_corrupt_sig_fatal_chk.1754231932 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/49.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_kmac_err_chk.361994392 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 1706096307 ps |
| CPU time | 22.58 seconds |
| Started | Feb 08 01:57:04 PM UTC 25 |
| Finished | Feb 08 01:57:27 PM UTC 25 |
| Peak memory | 228460 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=361994392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.361994392 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/49.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_max_throughput_chk.4203938037 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 1747701443 ps |
| CPU time | 14.53 seconds |
| Started | Feb 08 01:56:52 PM UTC 25 |
| Finished | Feb 08 01:57:08 PM UTC 25 |
| Peak memory | 228516 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4203938037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.4203938037 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/49.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all.783631276 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 5776956394 ps |
| CPU time | 26.8 seconds |
| Started | Feb 08 01:56:41 PM UTC 25 |
| Finished | Feb 08 01:57:09 PM UTC 25 |
| Peak memory | 228584 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=783631276 -assert no postproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all.783631276 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/49.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_alert_test.2340341266 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 331931840 ps |
| CPU time | 12.01 seconds |
| Started | Feb 08 01:40:11 PM UTC 25 |
| Finished | Feb 08 01:40:24 PM UTC 25 |
| Peak memory | 227664 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2340341266 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ct rl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.2340341266 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3928319652 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 59545909145 ps |
| CPU time | 193.78 seconds |
| Started | Feb 08 01:40:05 PM UTC 25 |
| Finished | Feb 08 01:43:22 PM UTC 25 |
| Peak memory | 259384 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3928319652 -assert nopostproc +UVM_TESTNAME=rom_c trl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_corrupt_sig_fatal_chk.3928319652 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_max_throughput_chk.326678487 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 259626729 ps |
| CPU time | 17.48 seconds |
| Started | Feb 08 01:40:02 PM UTC 25 |
| Finished | Feb 08 01:40:21 PM UTC 25 |
| Peak memory | 228512 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=326678487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.326678487 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_smoke.2006965775 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 740036479 ps |
| CPU time | 15.47 seconds |
| Started | Feb 08 01:39:57 PM UTC 25 |
| Finished | Feb 08 01:40:14 PM UTC 25 |
| Peak memory | 225332 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2006965775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.2006965775 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_alert_test.2872038828 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 170905670 ps |
| CPU time | 10 seconds |
| Started | Feb 08 01:40:38 PM UTC 25 |
| Finished | Feb 08 01:40:49 PM UTC 25 |
| Peak memory | 227544 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2872038828 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ct rl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.2872038828 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.607348907 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 3399683191 ps |
| CPU time | 274.44 seconds |
| Started | Feb 08 01:40:25 PM UTC 25 |
| Finished | Feb 08 01:45:03 PM UTC 25 |
| Peak memory | 257356 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=607348907 -assert nopostproc +UVM_TESTNAME=rom_ct rl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_corrupt_sig_fatal_chk.607348907 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_kmac_err_chk.2206827383 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 1768609960 ps |
| CPU time | 34.07 seconds |
| Started | Feb 08 01:40:36 PM UTC 25 |
| Finished | Feb 08 01:41:12 PM UTC 25 |
| Peak memory | 228408 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2206827383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.2206827383 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_max_throughput_chk.2255265715 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 716056960 ps |
| CPU time | 15.4 seconds |
| Started | Feb 08 01:40:25 PM UTC 25 |
| Finished | Feb 08 01:40:42 PM UTC 25 |
| Peak memory | 228444 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2255265715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.2255265715 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_smoke.1591253289 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 1343422588 ps |
| CPU time | 18.6 seconds |
| Started | Feb 08 01:40:16 PM UTC 25 |
| Finished | Feb 08 01:40:36 PM UTC 25 |
| Peak memory | 228464 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1591253289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.1591253289 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all.3916356261 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 525034394 ps |
| CPU time | 27.28 seconds |
| Started | Feb 08 01:40:22 PM UTC 25 |
| Finished | Feb 08 01:40:51 PM UTC 25 |
| Peak memory | 228456 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3916356261 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all.3916356261 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_alert_test.662557528 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 332398139 ps |
| CPU time | 12.37 seconds |
| Started | Feb 08 01:40:54 PM UTC 25 |
| Finished | Feb 08 01:41:07 PM UTC 25 |
| Peak memory | 227572 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=662557528 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctr l_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.662557528 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1210827592 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 12593833642 ps |
| CPU time | 406.99 seconds |
| Started | Feb 08 01:40:50 PM UTC 25 |
| Finished | Feb 08 01:47:43 PM UTC 25 |
| Peak memory | 258424 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1210827592 -assert nopostproc +UVM_TESTNAME=rom_c trl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_corrupt_sig_fatal_chk.1210827592 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_kmac_err_chk.3420830552 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 1576269319 ps |
| CPU time | 24.49 seconds |
| Started | Feb 08 01:40:52 PM UTC 25 |
| Finished | Feb 08 01:41:18 PM UTC 25 |
| Peak memory | 225388 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420830552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.3420830552 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_max_throughput_chk.1818283411 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 259803239 ps |
| CPU time | 18.31 seconds |
| Started | Feb 08 01:40:42 PM UTC 25 |
| Finished | Feb 08 01:41:02 PM UTC 25 |
| Peak memory | 228444 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1818283411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.1818283411 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_smoke.4217056902 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 715017260 ps |
| CPU time | 14.33 seconds |
| Started | Feb 08 01:40:39 PM UTC 25 |
| Finished | Feb 08 01:40:55 PM UTC 25 |
| Peak memory | 225332 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4217056902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.4217056902 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all.2321973980 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 3817869375 ps |
| CPU time | 67.03 seconds |
| Started | Feb 08 01:40:42 PM UTC 25 |
| Finished | Feb 08 01:41:51 PM UTC 25 |
| Peak memory | 228524 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2321973980 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all.2321973980 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.2226973857 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 31733402561 ps |
| CPU time | 1225.02 seconds |
| Started | Feb 08 01:40:53 PM UTC 25 |
| Finished | Feb 08 02:01:31 PM UTC 25 |
| Peak memory | 242980 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom _ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=2226973857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl _stress_all_with_rand_reset.2226973857 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_alert_test.610785655 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 181639073 ps |
| CPU time | 12.13 seconds |
| Started | Feb 08 01:41:18 PM UTC 25 |
| Finished | Feb 08 01:41:32 PM UTC 25 |
| Peak memory | 227712 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=610785655 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctr l_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.610785655 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.2159347655 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 6198607998 ps |
| CPU time | 329.26 seconds |
| Started | Feb 08 01:41:10 PM UTC 25 |
| Finished | Feb 08 01:46:44 PM UTC 25 |
| Peak memory | 246136 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2159347655 -assert nopostproc +UVM_TESTNAME=rom_c trl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_corrupt_sig_fatal_chk.2159347655 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_kmac_err_chk.2978941973 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 805645831 ps |
| CPU time | 26.68 seconds |
| Started | Feb 08 01:41:12 PM UTC 25 |
| Finished | Feb 08 01:41:40 PM UTC 25 |
| Peak memory | 228460 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2978941973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.2978941973 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_max_throughput_chk.3644153558 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 1846404593 ps |
| CPU time | 18.92 seconds |
| Started | Feb 08 01:41:08 PM UTC 25 |
| Finished | Feb 08 01:41:28 PM UTC 25 |
| Peak memory | 228444 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644153558 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.3644153558 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_smoke.1754804008 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 375472980 ps |
| CPU time | 17.88 seconds |
| Started | Feb 08 01:40:56 PM UTC 25 |
| Finished | Feb 08 01:41:15 PM UTC 25 |
| Peak memory | 228020 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754804008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.1754804008 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all.2324404351 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 530650779 ps |
| CPU time | 35.58 seconds |
| Started | Feb 08 01:41:03 PM UTC 25 |
| Finished | Feb 08 01:41:40 PM UTC 25 |
| Peak memory | 227372 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2324404351 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all.2324404351 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_alert_test.1788483309 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 262549944 ps |
| CPU time | 11.57 seconds |
| Started | Feb 08 01:41:47 PM UTC 25 |
| Finished | Feb 08 01:42:00 PM UTC 25 |
| Peak memory | 227636 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1788483309 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ct rl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.1788483309 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.546421706 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 13172952163 ps |
| CPU time | 304.32 seconds |
| Started | Feb 08 01:41:41 PM UTC 25 |
| Finished | Feb 08 01:46:49 PM UTC 25 |
| Peak memory | 249292 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=546421706 -assert nopostproc +UVM_TESTNAME=rom_ct rl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_corrupt_sig_fatal_chk.546421706 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_kmac_err_chk.2379279210 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 343447682 ps |
| CPU time | 23.52 seconds |
| Started | Feb 08 01:41:42 PM UTC 25 |
| Finished | Feb 08 01:42:07 PM UTC 25 |
| Peak memory | 228524 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2379279210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.2379279210 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_max_throughput_chk.2234121364 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 963284908 ps |
| CPU time | 14.92 seconds |
| Started | Feb 08 01:41:41 PM UTC 25 |
| Finished | Feb 08 01:41:57 PM UTC 25 |
| Peak memory | 228444 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2234121364 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.2234121364 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_smoke.680850178 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 1937357254 ps |
| CPU time | 24.26 seconds |
| Started | Feb 08 01:41:29 PM UTC 25 |
| Finished | Feb 08 01:41:55 PM UTC 25 |
| Peak memory | 225396 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=680850178 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.680850178 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all.809124414 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 806657052 ps |
| CPU time | 60.29 seconds |
| Started | Feb 08 01:41:32 PM UTC 25 |
| Finished | Feb 08 01:42:35 PM UTC 25 |
| Peak memory | 228516 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=809124414 -assert no postproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all.809124414 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_stress_all/latest |
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