| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 97.28 | 96.89 | 92.13 | 97.68 | 100.00 | 98.62 | 97.30 | 98.37 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP | |||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 64.00 | 64.00 | 92.58 | 92.58 | 68.12 | 68.12 | 52.02 | 52.02 | 40.00 | 40.00 | 88.97 | 88.97 | 93.69 | 93.69 | 12.59 | 12.59 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all.4065703355 |
| 73.00 | 9.00 | 92.58 | 0.00 | 70.37 | 2.25 | 77.31 | 25.29 | 73.33 | 33.33 | 89.31 | 0.34 | 93.84 | 0.15 | 14.22 | 1.63 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3808242218 |
| 81.21 | 8.22 | 92.94 | 0.36 | 76.83 | 6.46 | 78.39 | 1.07 | 73.33 | 0.00 | 91.03 | 1.72 | 95.35 | 1.50 | 60.61 | 46.39 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.2352074337 |
| 85.67 | 4.45 | 93.30 | 0.36 | 77.25 | 0.42 | 79.04 | 0.65 | 86.67 | 13.33 | 92.07 | 1.03 | 95.35 | 0.00 | 75.99 | 15.38 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_max_throughput_chk.3198844352 |
| 88.58 | 2.91 | 93.54 | 0.24 | 83.85 | 6.60 | 89.83 | 10.79 | 86.67 | 0.00 | 94.14 | 2.07 | 95.35 | 0.00 | 76.69 | 0.70 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_kmac_err_chk.2357016574 |
| 90.86 | 2.28 | 93.66 | 0.12 | 84.83 | 0.98 | 89.83 | 0.00 | 100.00 | 13.33 | 95.17 | 1.03 | 95.35 | 0.00 | 77.16 | 0.47 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.555897626 |
| 92.18 | 1.33 | 96.65 | 2.99 | 87.50 | 2.67 | 90.25 | 0.42 | 100.00 | 0.00 | 96.21 | 1.03 | 95.65 | 0.30 | 79.02 | 1.86 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_alert_test.1465045646 |
| 93.36 | 1.18 | 96.65 | 0.00 | 87.92 | 0.42 | 90.85 | 0.60 | 100.00 | 0.00 | 96.21 | 0.00 | 95.65 | 0.00 | 86.25 | 7.23 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_max_throughput_chk.1959265924 |
| 94.44 | 1.08 | 96.89 | 0.24 | 88.62 | 0.70 | 90.85 | 0.00 | 100.00 | 0.00 | 97.24 | 1.03 | 95.65 | 0.00 | 91.84 | 5.59 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2758782822 |
| 95.23 | 0.78 | 96.89 | 0.00 | 90.45 | 1.83 | 93.13 | 2.27 | 100.00 | 0.00 | 97.93 | 0.69 | 95.65 | 0.00 | 92.54 | 0.70 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all.2180343225 |
| 95.68 | 0.46 | 96.89 | 0.00 | 90.59 | 0.14 | 95.73 | 2.60 | 100.00 | 0.00 | 97.93 | 0.00 | 95.65 | 0.00 | 93.01 | 0.47 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all.3786960895 |
| 95.99 | 0.31 | 96.89 | 0.00 | 91.15 | 0.56 | 96.08 | 0.35 | 100.00 | 0.00 | 97.93 | 0.00 | 95.95 | 0.30 | 93.94 | 0.93 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_sec_cm.3792947949 |
| 96.24 | 0.25 | 96.89 | 0.00 | 91.15 | 0.00 | 96.65 | 0.57 | 100.00 | 0.00 | 97.93 | 0.00 | 95.95 | 0.00 | 95.10 | 1.17 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all.1429709718 |
| 96.41 | 0.17 | 96.89 | 0.00 | 91.15 | 0.00 | 96.65 | 0.00 | 100.00 | 0.00 | 97.93 | 0.00 | 97.15 | 1.20 | 95.10 | 0.00 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.716631299 |
| 96.56 | 0.15 | 96.89 | 0.00 | 91.43 | 0.28 | 97.10 | 0.45 | 100.00 | 0.00 | 98.28 | 0.34 | 97.15 | 0.00 | 95.10 | 0.00 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_kmac_err_chk.895843983 |
| 96.70 | 0.13 | 96.89 | 0.00 | 91.43 | 0.00 | 97.10 | 0.00 | 100.00 | 0.00 | 98.28 | 0.00 | 97.15 | 0.00 | 96.04 | 0.93 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.414581385 |
| 96.80 | 0.10 | 96.89 | 0.00 | 91.57 | 0.14 | 97.33 | 0.22 | 100.00 | 0.00 | 98.62 | 0.34 | 97.15 | 0.00 | 96.04 | 0.00 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_kmac_err_chk.2734854427 |
| 96.90 | 0.10 | 96.89 | 0.00 | 91.57 | 0.00 | 97.33 | 0.00 | 100.00 | 0.00 | 98.62 | 0.00 | 97.15 | 0.00 | 96.74 | 0.70 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1007835668 |
| 96.99 | 0.09 | 96.89 | 0.00 | 91.71 | 0.14 | 97.33 | 0.00 | 100.00 | 0.00 | 98.62 | 0.00 | 97.15 | 0.00 | 97.20 | 0.47 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3095836652 |
| 97.06 | 0.08 | 96.89 | 0.00 | 91.99 | 0.28 | 97.35 | 0.02 | 100.00 | 0.00 | 98.62 | 0.00 | 97.15 | 0.00 | 97.44 | 0.23 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.2193846442 |
| 97.13 | 0.07 | 96.89 | 0.00 | 91.99 | 0.00 | 97.38 | 0.02 | 100.00 | 0.00 | 98.62 | 0.00 | 97.15 | 0.00 | 97.90 | 0.47 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_max_throughput_chk.3641009100 |
| 97.17 | 0.04 | 96.89 | 0.00 | 91.99 | 0.00 | 97.63 | 0.25 | 100.00 | 0.00 | 98.62 | 0.00 | 97.15 | 0.00 | 97.90 | 0.00 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all.2893317696 |
| 97.20 | 0.03 | 96.89 | 0.00 | 91.99 | 0.00 | 97.63 | 0.00 | 100.00 | 0.00 | 98.62 | 0.00 | 97.15 | 0.00 | 98.14 | 0.23 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1083715278 |
| 97.24 | 0.03 | 96.89 | 0.00 | 91.99 | 0.00 | 97.63 | 0.00 | 100.00 | 0.00 | 98.62 | 0.00 | 97.15 | 0.00 | 98.37 | 0.23 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.4001070888 |
| 97.26 | 0.02 | 96.89 | 0.00 | 91.99 | 0.00 | 97.63 | 0.00 | 100.00 | 0.00 | 98.62 | 0.00 | 97.30 | 0.15 | 98.37 | 0.00 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.306784487 |
| 97.28 | 0.02 | 96.89 | 0.00 | 92.13 | 0.14 | 97.63 | 0.00 | 100.00 | 0.00 | 98.62 | 0.00 | 97.30 | 0.00 | 98.37 | 0.00 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.3114159917 |
| 97.28 | 0.01 | 96.89 | 0.00 | 92.13 | 0.00 | 97.68 | 0.05 | 100.00 | 0.00 | 98.62 | 0.00 | 97.30 | 0.00 | 98.37 | 0.00 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_kmac_err_chk.380144298 |
| Name |
|---|
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.134478133 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1044057363 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1776206640 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.4100586736 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_rw.4087578677 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1129241651 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2607659275 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3903277707 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1161112683 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.99946567 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1267304879 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3718600596 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2098645042 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1697000965 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3738622108 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2238762930 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_errors.818911234 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1588508560 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3739661919 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1998888354 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1197944377 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.617729435 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3130941362 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3211835716 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1329264130 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2848134922 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2393531120 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3031950203 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3762797928 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1846844783 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1328869110 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2156561211 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.4095509429 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3308886898 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2559341115 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_rw.668262002 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3775901523 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2146179529 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_errors.479985649 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3806025187 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_rw.4242518745 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3328657004 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.427905725 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_errors.987977941 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.4090442648 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2771297561 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3845674301 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1802545631 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3032378305 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3968700793 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.924194980 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.4168452022 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3013748660 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1972458723 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3590068825 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3095767888 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1297303990 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1365501736 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2321420186 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.832770466 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2368012064 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3147803714 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1343312899 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3625530179 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1788831957 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.813852916 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.4152649118 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2379997349 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.167666207 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3390003747 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2469547371 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1973886234 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1007699841 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1020185216 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.638077040 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.390838522 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3582368960 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.73776179 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3260047878 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_rw.184351954 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1699722111 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1426960618 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3984622134 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.4191259761 |
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| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_max_throughput_chk.3644153558 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_smoke.1754804008 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all.2324404351 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_alert_test.1788483309 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.546421706 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_kmac_err_chk.2379279210 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_max_throughput_chk.2234121364 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_smoke.680850178 |
| /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all.809124414 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_smoke.142700926 | Feb 08 01:38:55 PM UTC 25 | Feb 08 01:39:12 PM UTC 25 | 325301989 ps | ||
| T2 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_alert_test.1465045646 | Feb 08 01:38:58 PM UTC 25 | Feb 08 01:39:12 PM UTC 25 | 1455988507 ps | ||
| T3 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_max_throughput_chk.3198844352 | Feb 08 01:38:58 PM UTC 25 | Feb 08 01:39:13 PM UTC 25 | 727386726 ps | ||
| T4 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_max_throughput_chk.1992092928 | Feb 08 01:38:56 PM UTC 25 | Feb 08 01:39:14 PM UTC 25 | 189621699 ps | ||
| T5 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_smoke.3635136370 | Feb 08 01:38:58 PM UTC 25 | Feb 08 01:39:15 PM UTC 25 | 1064838314 ps | ||
| T6 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_kmac_err_chk.2734854427 | Feb 08 01:38:58 PM UTC 25 | Feb 08 01:39:19 PM UTC 25 | 342793165 ps | ||
| T7 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_alert_test.4124862449 | Feb 08 01:39:13 PM UTC 25 | Feb 08 01:39:27 PM UTC 25 | 477609336 ps | ||
| T8 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_max_throughput_chk.2536285096 | Feb 08 01:39:15 PM UTC 25 | Feb 08 01:39:28 PM UTC 25 | 185345600 ps | ||
| T9 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_smoke.1490032480 | Feb 08 01:39:14 PM UTC 25 | Feb 08 01:39:29 PM UTC 25 | 186734610 ps | ||
| T10 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all.4065703355 | Feb 08 01:38:55 PM UTC 25 | Feb 08 01:39:29 PM UTC 25 | 1978270295 ps | ||
| T11 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all.1429709718 | Feb 08 01:38:58 PM UTC 25 | Feb 08 01:39:32 PM UTC 25 | 1098577012 ps | ||
| T28 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_kmac_err_chk.380144298 | Feb 08 01:38:56 PM UTC 25 | Feb 08 01:39:34 PM UTC 25 | 7890789455 ps | ||
| T30 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_alert_test.1959654177 | Feb 08 01:39:28 PM UTC 25 | Feb 08 01:39:38 PM UTC 25 | 1377003825 ps | ||
| T15 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all.3786960895 | Feb 08 01:39:15 PM UTC 25 | Feb 08 01:39:42 PM UTC 25 | 1033908416 ps | ||
| T21 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_smoke.642534848 | Feb 08 01:39:28 PM UTC 25 | Feb 08 01:39:44 PM UTC 25 | 1014981593 ps | ||
| T29 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_kmac_err_chk.2418931100 | Feb 08 01:39:21 PM UTC 25 | Feb 08 01:39:46 PM UTC 25 | 5500496261 ps | ||
| T16 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_max_throughput_chk.2501619032 | Feb 08 01:39:29 PM UTC 25 | Feb 08 01:39:51 PM UTC 25 | 1998922714 ps | ||
| T75 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_alert_test.3702131729 | Feb 08 01:39:35 PM UTC 25 | Feb 08 01:39:51 PM UTC 25 | 6518952799 ps | ||
| T71 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_smoke.3644506629 | Feb 08 01:39:39 PM UTC 25 | Feb 08 01:39:56 PM UTC 25 | 2504516233 ps | ||
| T31 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_kmac_err_chk.2357016574 | Feb 08 01:39:30 PM UTC 25 | Feb 08 01:40:01 PM UTC 25 | 1952010041 ps | ||
| T32 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all.2552984465 | Feb 08 01:39:29 PM UTC 25 | Feb 08 01:40:06 PM UTC 25 | 2612451826 ps | ||
| T76 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_alert_test.1283154748 | Feb 08 01:39:55 PM UTC 25 | Feb 08 01:40:09 PM UTC 25 | 2760928085 ps | ||
| T118 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_max_throughput_chk.3641009100 | Feb 08 01:39:45 PM UTC 25 | Feb 08 01:40:10 PM UTC 25 | 3963552699 ps | ||
| T18 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_smoke.2006965775 | Feb 08 01:39:57 PM UTC 25 | Feb 08 01:40:14 PM UTC 25 | 740036479 ps | ||
| T119 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_max_throughput_chk.326678487 | Feb 08 01:40:02 PM UTC 25 | Feb 08 01:40:21 PM UTC 25 | 259626729 ps | ||
| T77 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_alert_test.2340341266 | Feb 08 01:40:11 PM UTC 25 | Feb 08 01:40:24 PM UTC 25 | 331931840 ps | ||
| T90 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_smoke.1591253289 | Feb 08 01:40:16 PM UTC 25 | Feb 08 01:40:36 PM UTC 25 | 1343422588 ps | ||
| T19 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all.2180343225 | Feb 08 01:39:57 PM UTC 25 | Feb 08 01:40:37 PM UTC 25 | 574822205 ps | ||
| T33 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_kmac_err_chk.895843983 | Feb 08 01:40:07 PM UTC 25 | Feb 08 01:40:38 PM UTC 25 | 2059434785 ps | ||
| T34 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_kmac_err_chk.2565323252 | Feb 08 01:39:52 PM UTC 25 | Feb 08 01:40:41 PM UTC 25 | 1970844038 ps | ||
| T120 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_max_throughput_chk.2255265715 | Feb 08 01:40:25 PM UTC 25 | Feb 08 01:40:42 PM UTC 25 | 716056960 ps | ||
| T78 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_alert_test.2872038828 | Feb 08 01:40:38 PM UTC 25 | Feb 08 01:40:49 PM UTC 25 | 170905670 ps | ||
| T91 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all.3916356261 | Feb 08 01:40:22 PM UTC 25 | Feb 08 01:40:51 PM UTC 25 | 525034394 ps | ||
| T139 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all.2558435057 | Feb 08 01:39:43 PM UTC 25 | Feb 08 01:40:51 PM UTC 25 | 2090423129 ps | ||
| T92 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_smoke.4217056902 | Feb 08 01:40:39 PM UTC 25 | Feb 08 01:40:55 PM UTC 25 | 715017260 ps | ||
| T121 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_max_throughput_chk.1818283411 | Feb 08 01:40:42 PM UTC 25 | Feb 08 01:41:02 PM UTC 25 | 259803239 ps | ||
| T79 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_alert_test.662557528 | Feb 08 01:40:54 PM UTC 25 | Feb 08 01:41:07 PM UTC 25 | 332398139 ps | ||
| T181 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_kmac_err_chk.2206827383 | Feb 08 01:40:36 PM UTC 25 | Feb 08 01:41:12 PM UTC 25 | 1768609960 ps | ||
| T93 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_smoke.1754804008 | Feb 08 01:40:56 PM UTC 25 | Feb 08 01:41:15 PM UTC 25 | 375472980 ps | ||
| T182 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_kmac_err_chk.3420830552 | Feb 08 01:40:52 PM UTC 25 | Feb 08 01:41:18 PM UTC 25 | 1576269319 ps | ||
| T137 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_max_throughput_chk.3644153558 | Feb 08 01:41:08 PM UTC 25 | Feb 08 01:41:28 PM UTC 25 | 1846404593 ps | ||
| T80 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_alert_test.610785655 | Feb 08 01:41:18 PM UTC 25 | Feb 08 01:41:32 PM UTC 25 | 181639073 ps | ||
| T138 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all.2324404351 | Feb 08 01:41:03 PM UTC 25 | Feb 08 01:41:40 PM UTC 25 | 530650779 ps | ||
| T47 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_kmac_err_chk.2978941973 | Feb 08 01:41:12 PM UTC 25 | Feb 08 01:41:40 PM UTC 25 | 805645831 ps | ||
| T152 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all.2321973980 | Feb 08 01:40:42 PM UTC 25 | Feb 08 01:41:51 PM UTC 25 | 3817869375 ps | ||
| T163 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_smoke.680850178 | Feb 08 01:41:29 PM UTC 25 | Feb 08 01:41:55 PM UTC 25 | 1937357254 ps | ||
| T140 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_max_throughput_chk.2234121364 | Feb 08 01:41:41 PM UTC 25 | Feb 08 01:41:57 PM UTC 25 | 963284908 ps | ||
| T81 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_alert_test.1788483309 | Feb 08 01:41:47 PM UTC 25 | Feb 08 01:42:00 PM UTC 25 | 262549944 ps | ||
| T175 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_kmac_err_chk.2379279210 | Feb 08 01:41:42 PM UTC 25 | Feb 08 01:42:07 PM UTC 25 | 343447682 ps | ||
| T141 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_max_throughput_chk.2378880627 | Feb 08 01:41:52 PM UTC 25 | Feb 08 01:42:10 PM UTC 25 | 1073649566 ps | ||
| T158 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_alert_test.276583891 | Feb 08 01:42:07 PM UTC 25 | Feb 08 01:42:19 PM UTC 25 | 174960771 ps | ||
| T25 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_sec_cm.2334121668 | Feb 08 01:39:32 PM UTC 25 | Feb 08 01:42:21 PM UTC 25 | 717341948 ps | ||
| T37 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_kmac_err_chk.1700617680 | Feb 08 01:41:57 PM UTC 25 | Feb 08 01:42:28 PM UTC 25 | 652587770 ps | ||
| T38 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_max_throughput_chk.1959265924 | Feb 08 01:42:20 PM UTC 25 | Feb 08 01:42:33 PM UTC 25 | 2144979520 ps | ||
| T39 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all.809124414 | Feb 08 01:41:32 PM UTC 25 | Feb 08 01:42:35 PM UTC 25 | 806657052 ps | ||
| T40 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_alert_test.453248430 | Feb 08 01:42:24 PM UTC 25 | Feb 08 01:42:38 PM UTC 25 | 2753304837 ps | ||
| T41 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_kmac_err_chk.2456360184 | Feb 08 01:42:21 PM UTC 25 | Feb 08 01:42:48 PM UTC 25 | 2545617708 ps | ||
| T42 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_max_throughput_chk.1755891087 | Feb 08 01:42:34 PM UTC 25 | Feb 08 01:42:49 PM UTC 25 | 726520130 ps | ||
| T43 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all.2893317696 | Feb 08 01:41:47 PM UTC 25 | Feb 08 01:42:49 PM UTC 25 | 5530079907 ps | ||
| T26 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_sec_cm.207661229 | Feb 08 01:38:56 PM UTC 25 | Feb 08 01:42:59 PM UTC 25 | 607384508 ps | ||
| T44 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all.2518581006 | Feb 08 01:42:29 PM UTC 25 | Feb 08 01:43:03 PM UTC 25 | 1446571449 ps | ||
| T20 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all.897914116 | Feb 08 01:42:11 PM UTC 25 | Feb 08 01:43:04 PM UTC 25 | 1587316148 ps | ||
| T183 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_alert_test.449851500 | Feb 08 01:42:50 PM UTC 25 | Feb 08 01:43:05 PM UTC 25 | 505725013 ps | ||
| T142 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_max_throughput_chk.1066576148 | Feb 08 01:42:52 PM UTC 25 | Feb 08 01:43:09 PM UTC 25 | 511125115 ps | ||
| T22 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3808242218 | Feb 08 01:38:56 PM UTC 25 | Feb 08 01:43:15 PM UTC 25 | 7250075969 ps | ||
| T164 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_kmac_err_chk.395736044 | Feb 08 01:42:39 PM UTC 25 | Feb 08 01:43:16 PM UTC 25 | 506838598 ps | ||
| T184 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_max_throughput_chk.1827727028 | Feb 08 01:43:07 PM UTC 25 | Feb 08 01:43:21 PM UTC 25 | 1597413108 ps | ||
| T159 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_alert_test.376225233 | Feb 08 01:43:05 PM UTC 25 | Feb 08 01:43:22 PM UTC 25 | 327033728 ps | ||
| T23 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3928319652 | Feb 08 01:40:05 PM UTC 25 | Feb 08 01:43:22 PM UTC 25 | 59545909145 ps | ||
| T24 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.555897626 | Feb 08 01:39:47 PM UTC 25 | Feb 08 01:43:24 PM UTC 25 | 15081120802 ps | ||
| T27 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_sec_cm.1032058095 | Feb 08 01:39:13 PM UTC 25 | Feb 08 01:43:24 PM UTC 25 | 2283037410 ps | ||
| T148 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all.13807975 | Feb 08 01:42:50 PM UTC 25 | Feb 08 01:43:29 PM UTC 25 | 841294655 ps | ||
| T45 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.3202943556 | Feb 08 01:39:30 PM UTC 25 | Feb 08 01:43:32 PM UTC 25 | 32130774874 ps | ||
| T185 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all.1318918964 | Feb 08 01:43:05 PM UTC 25 | Feb 08 01:43:33 PM UTC 25 | 205392891 ps | ||
| T143 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_max_throughput_chk.1092612627 | Feb 08 01:43:23 PM UTC 25 | Feb 08 01:43:35 PM UTC 25 | 357744950 ps | ||
| T186 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_alert_test.1230182986 | Feb 08 01:43:22 PM UTC 25 | Feb 08 01:43:36 PM UTC 25 | 348025436 ps | ||
| T153 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_kmac_err_chk.860038489 | Feb 08 01:43:04 PM UTC 25 | Feb 08 01:43:38 PM UTC 25 | 519512071 ps | ||
| T187 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_kmac_err_chk.689881074 | Feb 08 01:43:15 PM UTC 25 | Feb 08 01:43:39 PM UTC 25 | 639426677 ps | ||
| T160 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_alert_test.1138858054 | Feb 08 01:43:33 PM UTC 25 | Feb 08 01:43:50 PM UTC 25 | 383567808 ps | ||
| T188 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_max_throughput_chk.1589915266 | Feb 08 01:43:34 PM UTC 25 | Feb 08 01:43:50 PM UTC 25 | 187264536 ps | ||
| T165 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all.611562869 | Feb 08 01:43:34 PM UTC 25 | Feb 08 01:43:55 PM UTC 25 | 1128330059 ps | ||
| T189 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_kmac_err_chk.3877272377 | Feb 08 01:43:25 PM UTC 25 | Feb 08 01:44:00 PM UTC 25 | 1034192079 ps | ||
| T46 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.829583274 | Feb 08 01:39:20 PM UTC 25 | Feb 08 01:44:00 PM UTC 25 | 4413796074 ps | ||
| T35 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_sec_cm.3792947949 | Feb 08 01:39:28 PM UTC 25 | Feb 08 01:44:03 PM UTC 25 | 500633174 ps | ||
| T36 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_sec_cm.3480336834 | Feb 08 01:39:54 PM UTC 25 | Feb 08 01:44:03 PM UTC 25 | 1167084927 ps | ||
| T150 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all.3662487770 | Feb 08 01:43:23 PM UTC 25 | Feb 08 01:44:04 PM UTC 25 | 754651932 ps | ||
| T155 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_alert_test.2962720311 | Feb 08 01:43:40 PM UTC 25 | Feb 08 01:44:04 PM UTC 25 | 4086105897 ps | ||
| T190 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_max_throughput_chk.3163609316 | Feb 08 01:43:52 PM UTC 25 | Feb 08 01:44:05 PM UTC 25 | 2498023939 ps | ||
| T191 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_kmac_err_chk.1150289040 | Feb 08 01:43:36 PM UTC 25 | Feb 08 01:44:12 PM UTC 25 | 1015355718 ps | ||
| T167 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_alert_test.3704538648 | Feb 08 01:44:01 PM UTC 25 | Feb 08 01:44:15 PM UTC 25 | 518792515 ps | ||
| T177 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_kmac_err_chk.905555035 | Feb 08 01:43:57 PM UTC 25 | Feb 08 01:44:19 PM UTC 25 | 337453302 ps | ||
| T192 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_max_throughput_chk.1785641693 | Feb 08 01:44:04 PM UTC 25 | Feb 08 01:44:20 PM UTC 25 | 534675860 ps | ||
| T180 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_alert_test.2208102208 | Feb 08 01:44:10 PM UTC 25 | Feb 08 01:44:24 PM UTC 25 | 692777836 ps | ||
| T193 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_kmac_err_chk.533842177 | Feb 08 01:44:05 PM UTC 25 | Feb 08 01:44:27 PM UTC 25 | 348419519 ps | ||
| T194 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_max_throughput_chk.3408798077 | Feb 08 01:44:15 PM UTC 25 | Feb 08 01:44:29 PM UTC 25 | 525502151 ps | ||
| T53 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.2193846442 | Feb 08 01:38:58 PM UTC 25 | Feb 08 01:44:33 PM UTC 25 | 14969081785 ps | ||
| T48 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_kmac_err_chk.238157804 | Feb 08 01:44:22 PM UTC 25 | Feb 08 01:44:44 PM UTC 25 | 347642359 ps | ||
| T166 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_alert_test.3749669505 | Feb 08 01:44:28 PM UTC 25 | Feb 08 01:44:44 PM UTC 25 | 1234901256 ps | ||
| T195 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all.1442226139 | Feb 08 01:43:52 PM UTC 25 | Feb 08 01:44:45 PM UTC 25 | 394253908 ps | ||
| T196 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all.897337899 | Feb 08 01:44:04 PM UTC 25 | Feb 08 01:44:50 PM UTC 25 | 562408423 ps | ||
| T197 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_max_throughput_chk.2694669574 | Feb 08 01:44:34 PM UTC 25 | Feb 08 01:44:52 PM UTC 25 | 274270582 ps | ||
| T145 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all.1015591135 | Feb 08 01:44:12 PM UTC 25 | Feb 08 01:44:55 PM UTC 25 | 2277527736 ps | ||
| T146 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all.575172546 | Feb 08 01:44:30 PM UTC 25 | Feb 08 01:44:59 PM UTC 25 | 706133229 ps | ||
| T51 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.607348907 | Feb 08 01:40:25 PM UTC 25 | Feb 08 01:45:03 PM UTC 25 | 3399683191 ps | ||
| T198 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_alert_test.1596166400 | Feb 08 01:44:51 PM UTC 25 | Feb 08 01:45:04 PM UTC 25 | 254992672 ps | ||
| T199 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_max_throughput_chk.384798510 | Feb 08 01:44:55 PM UTC 25 | Feb 08 01:45:12 PM UTC 25 | 259416696 ps | ||
| T200 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_kmac_err_chk.2557488007 | Feb 08 01:44:45 PM UTC 25 | Feb 08 01:45:12 PM UTC 25 | 688992963 ps | ||
| T149 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all.1086108798 | Feb 08 01:44:53 PM UTC 25 | Feb 08 01:45:26 PM UTC 25 | 1100722753 ps | ||
| T201 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_alert_test.1372964896 | Feb 08 01:45:09 PM UTC 25 | Feb 08 01:45:26 PM UTC 25 | 260834340 ps | ||
| T147 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_kmac_err_chk.983603866 | Feb 08 01:45:04 PM UTC 25 | Feb 08 01:45:29 PM UTC 25 | 675671588 ps | ||
| T202 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_max_throughput_chk.1145922078 | Feb 08 01:45:14 PM UTC 25 | Feb 08 01:45:30 PM UTC 25 | 178664442 ps | ||
| T203 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_alert_test.1337516305 | Feb 08 01:45:27 PM UTC 25 | Feb 08 01:45:42 PM UTC 25 | 506855679 ps | ||
| T204 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_max_throughput_chk.2725572743 | Feb 08 01:45:30 PM UTC 25 | Feb 08 01:45:48 PM UTC 25 | 264401664 ps | ||
| T205 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_kmac_err_chk.3690307242 | Feb 08 01:45:23 PM UTC 25 | Feb 08 01:45:51 PM UTC 25 | 1414355807 ps | ||
| T157 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all.2770309291 | Feb 08 01:45:13 PM UTC 25 | Feb 08 01:46:02 PM UTC 25 | 1118668902 ps | ||
| T206 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_alert_test.3532493278 | Feb 08 01:45:49 PM UTC 25 | Feb 08 01:46:03 PM UTC 25 | 2368091465 ps | ||
| T207 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all.3853827457 | Feb 08 01:45:27 PM UTC 25 | Feb 08 01:46:07 PM UTC 25 | 385037110 ps | ||
| T208 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_kmac_err_chk.1498613505 | Feb 08 01:45:35 PM UTC 25 | Feb 08 01:46:09 PM UTC 25 | 519221497 ps | ||
| T209 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_max_throughput_chk.1218828666 | Feb 08 01:46:03 PM UTC 25 | Feb 08 01:46:21 PM UTC 25 | 1078576675 ps | ||
| T171 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all.1511985524 | Feb 08 01:45:52 PM UTC 25 | Feb 08 01:46:31 PM UTC 25 | 376412453 ps | ||
| T210 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_alert_test.4248615957 | Feb 08 01:46:19 PM UTC 25 | Feb 08 01:46:36 PM UTC 25 | 250017911 ps | ||
| T135 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.3034047209 | Feb 08 01:41:56 PM UTC 25 | Feb 08 01:46:40 PM UTC 25 | 19490961284 ps | ||
| T211 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_kmac_err_chk.3716237406 | Feb 08 01:46:08 PM UTC 25 | Feb 08 01:46:43 PM UTC 25 | 2467401808 ps | ||
| T52 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.2159347655 | Feb 08 01:41:10 PM UTC 25 | Feb 08 01:46:44 PM UTC 25 | 6198607998 ps | ||
| T212 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_max_throughput_chk.2057826262 | Feb 08 01:46:32 PM UTC 25 | Feb 08 01:46:48 PM UTC 25 | 727360604 ps | ||
| T213 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.546421706 | Feb 08 01:41:41 PM UTC 25 | Feb 08 01:46:49 PM UTC 25 | 13172952163 ps | ||
| T214 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1167892298 | Feb 08 01:42:35 PM UTC 25 | Feb 08 01:46:51 PM UTC 25 | 10442320795 ps | ||
| T215 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all.3101235667 | Feb 08 01:46:22 PM UTC 25 | Feb 08 01:47:00 PM UTC 25 | 9254837187 ps | ||
| T216 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_kmac_err_chk.3667631227 | Feb 08 01:46:41 PM UTC 25 | Feb 08 01:47:05 PM UTC 25 | 1380694059 ps | ||
| T217 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_max_throughput_chk.1085792134 | Feb 08 01:46:51 PM UTC 25 | Feb 08 01:47:07 PM UTC 25 | 1468717381 ps | ||
| T218 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_alert_test.259433606 | Feb 08 01:46:44 PM UTC 25 | Feb 08 01:47:11 PM UTC 25 | 3644100585 ps | ||
| T161 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_alert_test.3427000551 | Feb 08 01:47:06 PM UTC 25 | Feb 08 01:47:21 PM UTC 25 | 1183811343 ps | ||
| T219 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all.294853789 | Feb 08 01:46:49 PM UTC 25 | Feb 08 01:47:23 PM UTC 25 | 781837881 ps | ||
| T162 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_kmac_err_chk.1199778147 | Feb 08 01:47:01 PM UTC 25 | Feb 08 01:47:33 PM UTC 25 | 1376142290 ps | ||
| T220 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_max_throughput_chk.1434213576 | Feb 08 01:47:12 PM UTC 25 | Feb 08 01:47:36 PM UTC 25 | 1959855965 ps | ||
| T136 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1210827592 | Feb 08 01:40:50 PM UTC 25 | Feb 08 01:47:43 PM UTC 25 | 12593833642 ps | ||
| T173 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3781905125 | Feb 08 01:42:59 PM UTC 25 | Feb 08 01:47:44 PM UTC 25 | 4655690782 ps | ||
| T221 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.397903820 | Feb 08 01:43:09 PM UTC 25 | Feb 08 01:47:46 PM UTC 25 | 2908438961 ps | ||
| T222 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all.1859632562 | Feb 08 01:47:08 PM UTC 25 | Feb 08 01:47:49 PM UTC 25 | 809752113 ps | ||
| T223 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_alert_test.2350678896 | Feb 08 01:47:36 PM UTC 25 | Feb 08 01:47:50 PM UTC 25 | 756201630 ps | ||
| T224 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_max_throughput_chk.751688999 | Feb 08 01:47:44 PM UTC 25 | Feb 08 01:48:02 PM UTC 25 | 731014738 ps | ||
| T225 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all.2815696101 | Feb 08 01:47:43 PM UTC 25 | Feb 08 01:48:15 PM UTC 25 | 1112344543 ps | ||
| T156 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.1856247677 | Feb 08 01:44:05 PM UTC 25 | Feb 08 01:48:17 PM UTC 25 | 42703171994 ps | ||
| T226 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_alert_test.2052127383 | Feb 08 01:48:03 PM UTC 25 | Feb 08 01:48:17 PM UTC 25 | 660425759 ps | ||
| T227 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_kmac_err_chk.432531152 | Feb 08 01:47:24 PM UTC 25 | Feb 08 01:48:21 PM UTC 25 | 8197942027 ps | ||
| T228 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_kmac_err_chk.276602877 | Feb 08 01:47:50 PM UTC 25 | Feb 08 01:48:22 PM UTC 25 | 4125987396 ps | ||
| T229 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_max_throughput_chk.3318559202 | Feb 08 01:48:18 PM UTC 25 | Feb 08 01:48:36 PM UTC 25 | 716399351 ps | ||
| T230 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all.295362985 | Feb 08 01:48:16 PM UTC 25 | Feb 08 01:48:44 PM UTC 25 | 1119097314 ps | ||
| T231 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_alert_test.2918423892 | Feb 08 01:48:37 PM UTC 25 | Feb 08 01:48:52 PM UTC 25 | 689075809 ps | ||
| T232 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.1070497779 | Feb 08 01:44:20 PM UTC 25 | Feb 08 01:48:52 PM UTC 25 | 48389086469 ps | ||
| T168 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.311172821 | Feb 08 01:43:36 PM UTC 25 | Feb 08 01:48:54 PM UTC 25 | 7141423716 ps | ||
| T233 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.2542001698 | Feb 08 01:44:44 PM UTC 25 | Feb 08 01:48:56 PM UTC 25 | 16347391453 ps | ||
| T234 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_kmac_err_chk.3634889270 | Feb 08 01:48:22 PM UTC 25 | Feb 08 01:48:59 PM UTC 25 | 497728361 ps | ||
| T235 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_max_throughput_chk.295509225 | Feb 08 01:48:47 PM UTC 25 | Feb 08 01:49:01 PM UTC 25 | 529922553 ps | ||
| T154 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_alert_test.2562311827 | Feb 08 01:48:57 PM UTC 25 | Feb 08 01:49:09 PM UTC 25 | 174681773 ps | ||
| T236 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.2080040486 | Feb 08 01:45:00 PM UTC 25 | Feb 08 01:49:17 PM UTC 25 | 17673328795 ps | ||
| T12 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.2352074337 | Feb 08 01:38:59 PM UTC 25 | Feb 08 01:49:17 PM UTC 25 | 13225342172 ps | ||
| T60 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_max_throughput_chk.1083106953 | Feb 08 01:49:02 PM UTC 25 | Feb 08 01:49:20 PM UTC 25 | 1910810917 ps | ||
| T61 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all.608037713 | Feb 08 01:48:44 PM UTC 25 | Feb 08 01:49:24 PM UTC 25 | 548578682 ps | ||
| T62 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_stress_all.234476489 | Feb 08 01:49:00 PM UTC 25 | Feb 08 01:49:30 PM UTC 25 | 372447090 ps | ||
| T63 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_alert_test.2403824634 | Feb 08 01:49:21 PM UTC 25 | Feb 08 01:49:37 PM UTC 25 | 1542883252 ps | ||
| T49 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1975110029 | Feb 08 01:43:25 PM UTC 25 | Feb 08 01:49:31 PM UTC 25 | 17715707947 ps | ||
| T64 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_kmac_err_chk.259605615 | Feb 08 01:49:18 PM UTC 25 | Feb 08 01:49:39 PM UTC 25 | 332195309 ps | ||
| T65 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_kmac_err_chk.299878039 | Feb 08 01:48:52 PM UTC 25 | Feb 08 01:49:43 PM UTC 25 | 5312152886 ps | ||
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| T67 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_max_throughput_chk.2528061140 | Feb 08 01:49:31 PM UTC 25 | Feb 08 01:49:48 PM UTC 25 | 685995839 ps | ||
| T237 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.1414184161 | Feb 08 01:45:19 PM UTC 25 | Feb 08 01:49:50 PM UTC 25 | 4876152651 ps | ||
| T151 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.1362281714 | Feb 08 01:42:21 PM UTC 25 | Feb 08 01:49:55 PM UTC 25 | 7037525473 ps | ||
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| T238 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_kmac_err_chk.2970756897 | Feb 08 01:49:32 PM UTC 25 | Feb 08 01:49:57 PM UTC 25 | 502235214 ps | ||
| T174 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.4202922778 | Feb 08 01:45:31 PM UTC 25 | Feb 08 01:49:58 PM UTC 25 | 8995503788 ps | ||
| T178 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all.186140662 | Feb 08 01:49:44 PM UTC 25 | Feb 08 01:50:03 PM UTC 25 | 1037708669 ps | ||
| T239 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_max_throughput_chk.2222058646 | Feb 08 01:49:46 PM UTC 25 | Feb 08 01:50:04 PM UTC 25 | 1024656031 ps | ||
| T240 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.4148475158 | Feb 08 01:47:22 PM UTC 25 | Feb 08 01:50:11 PM UTC 25 | 2770166567 ps | ||
| T241 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_alert_test.2347556118 | Feb 08 01:49:57 PM UTC 25 | Feb 08 01:50:12 PM UTC 25 | 257660868 ps | ||
| T242 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_max_throughput_chk.605887211 | Feb 08 01:49:58 PM UTC 25 | Feb 08 01:50:14 PM UTC 25 | 718617749 ps | ||
| T243 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_alert_test.3832652796 | Feb 08 01:50:07 PM UTC 25 | Feb 08 01:50:21 PM UTC 25 | 223727812 ps | ||
| T244 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_kmac_err_chk.3184506813 | Feb 08 01:49:51 PM UTC 25 | Feb 08 01:50:22 PM UTC 25 | 338930117 ps | ||
| T245 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_kmac_err_chk.2442898156 | Feb 08 01:50:04 PM UTC 25 | Feb 08 01:50:25 PM UTC 25 | 1327103987 ps | ||
| T246 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_max_throughput_chk.196126794 | Feb 08 01:50:12 PM UTC 25 | Feb 08 01:50:29 PM UTC 25 | 255126933 ps | ||
| T247 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.4128116286 | Feb 08 01:46:37 PM UTC 25 | Feb 08 01:50:36 PM UTC 25 | 7300468231 ps | ||
| T248 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_alert_test.3587677371 | Feb 08 01:55:30 PM UTC 25 | Feb 08 01:55:46 PM UTC 25 | 1902146061 ps | ||
| T179 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all.796817306 | Feb 08 01:49:58 PM UTC 25 | Feb 08 01:50:39 PM UTC 25 | 1569555138 ps | ||
| T249 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_alert_test.1387109734 | Feb 08 01:50:26 PM UTC 25 | Feb 08 01:50:40 PM UTC 25 | 169333413 ps | ||
| T50 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.4159886440 | Feb 08 01:43:56 PM UTC 25 | Feb 08 01:50:47 PM UTC 25 | 6563355205 ps | ||
| T250 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all.530247756 | Feb 08 01:50:11 PM UTC 25 | Feb 08 01:50:52 PM UTC 25 | 524816402 ps | ||
| T251 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_max_throughput_chk.2705021994 | Feb 08 01:50:37 PM UTC 25 | Feb 08 01:50:55 PM UTC 25 | 264310660 ps | ||
| T252 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_kmac_err_chk.855124862 | Feb 08 01:50:23 PM UTC 25 | Feb 08 01:51:00 PM UTC 25 | 496748964 ps | ||
| T253 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_alert_test.34352135 | Feb 08 01:50:48 PM UTC 25 | Feb 08 01:51:00 PM UTC 25 | 203501847 ps | ||
| T254 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_kmac_err_chk.4019912553 | Feb 08 01:50:41 PM UTC 25 | Feb 08 01:51:01 PM UTC 25 | 690672225 ps | ||
| T255 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.865776131 | Feb 08 01:46:04 PM UTC 25 | Feb 08 01:51:08 PM UTC 25 | 7131966734 ps | ||
| T256 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all.3817458459 | Feb 08 01:50:30 PM UTC 25 | Feb 08 01:51:08 PM UTC 25 | 1978427986 ps | ||
| T257 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_max_throughput_chk.1139513901 | Feb 08 01:50:56 PM UTC 25 | Feb 08 01:51:12 PM UTC 25 | 752922911 ps | ||
| T258 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.562670352 | Feb 08 01:48:18 PM UTC 25 | Feb 08 01:51:21 PM UTC 25 | 14375958907 ps | ||
| T259 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all.2643554939 | Feb 08 01:50:52 PM UTC 25 | Feb 08 01:51:21 PM UTC 25 | 1509547151 ps | ||
| T260 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_alert_test.3942212336 | Feb 08 01:51:09 PM UTC 25 | Feb 08 01:51:23 PM UTC 25 | 496215302 ps | ||
| T261 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_max_throughput_chk.1652745116 | Feb 08 01:51:13 PM UTC 25 | Feb 08 01:51:29 PM UTC 25 | 188187697 ps | ||
| T262 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_kmac_err_chk.4095344414 | Feb 08 01:51:00 PM UTC 25 | Feb 08 01:51:30 PM UTC 25 | 2472746048 ps | ||
| T263 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_alert_test.1847399896 | Feb 08 01:51:30 PM UTC 25 | Feb 08 01:51:47 PM UTC 25 | 515880947 ps | ||
| T176 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all.1022311163 | Feb 08 01:51:10 PM UTC 25 | Feb 08 01:51:59 PM UTC 25 | 2143230075 ps | ||
| T264 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all.1547964808 | Feb 08 01:51:31 PM UTC 25 | Feb 08 01:51:59 PM UTC 25 | 767312407 ps | ||
| T265 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_max_throughput_chk.1321494182 | Feb 08 01:51:44 PM UTC 25 | Feb 08 01:52:03 PM UTC 25 | 577997133 ps | ||
| T266 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.4110862652 | Feb 08 01:46:52 PM UTC 25 | Feb 08 01:52:04 PM UTC 25 | 5438192915 ps | ||
| T267 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_kmac_err_chk.4222822851 | Feb 08 01:51:22 PM UTC 25 | Feb 08 01:52:09 PM UTC 25 | 3938539705 ps | ||
| T172 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_alert_test.3191532416 | Feb 08 01:52:02 PM UTC 25 | Feb 08 01:52:17 PM UTC 25 | 992711116 ps | ||
| T268 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_max_throughput_chk.967046899 | Feb 08 01:52:04 PM UTC 25 | Feb 08 01:52:23 PM UTC 25 | 1246670677 ps | ||
| T269 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_kmac_err_chk.4196337657 | Feb 08 01:51:59 PM UTC 25 | Feb 08 01:52:33 PM UTC 25 | 498008132 ps | ||
| T270 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.2829332814 | Feb 08 01:47:48 PM UTC 25 | Feb 08 01:52:37 PM UTC 25 | 5372129867 ps | ||
| T271 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_alert_test.1703641602 | Feb 08 01:52:34 PM UTC 25 | Feb 08 01:52:47 PM UTC 25 | 347718022 ps | ||
| T272 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_max_throughput_chk.1587433115 | Feb 08 01:52:38 PM UTC 25 | Feb 08 01:52:50 PM UTC 25 | 1474266161 ps | ||
| T273 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_kmac_err_chk.1623179210 | Feb 08 01:52:18 PM UTC 25 | Feb 08 01:52:51 PM UTC 25 | 1103026926 ps | ||
| T144 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.567390920 | Feb 08 01:48:52 PM UTC 25 | Feb 08 01:52:55 PM UTC 25 | 2874669723 ps | ||
| T274 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all.2812314516 | Feb 08 01:52:03 PM UTC 25 | Feb 08 01:53:00 PM UTC 25 | 2943685589 ps | ||
| T275 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_alert_test.1724190679 | Feb 08 01:52:55 PM UTC 25 | Feb 08 01:53:12 PM UTC 25 | 1033555948 ps | ||
| T276 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_kmac_err_chk.2292566823 | Feb 08 01:52:51 PM UTC 25 | Feb 08 01:53:23 PM UTC 25 | 333368805 ps | ||
| T277 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all.4222410048 | Feb 08 01:52:36 PM UTC 25 | Feb 08 01:53:30 PM UTC 25 | 2267406696 ps | ||
| T278 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_max_throughput_chk.588369539 | Feb 08 01:53:13 PM UTC 25 | Feb 08 01:53:34 PM UTC 25 | 1068476783 ps | ||
| T279 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.855913530 | Feb 08 01:49:32 PM UTC 25 | Feb 08 01:53:45 PM UTC 25 | 3137912374 ps | ||
| T280 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all.2784224778 | Feb 08 01:53:00 PM UTC 25 | Feb 08 01:53:59 PM UTC 25 | 2472331148 ps | ||
| T281 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_kmac_err_chk.3245512210 | Feb 08 01:53:30 PM UTC 25 | Feb 08 01:54:00 PM UTC 25 | 1744276159 ps | ||
| T282 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_alert_test.3023654522 | Feb 08 01:53:47 PM UTC 25 | Feb 08 01:54:02 PM UTC 25 | 1237637604 ps | ||
| T283 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.1721274793 | Feb 08 01:50:15 PM UTC 25 | Feb 08 01:54:03 PM UTC 25 | 3749994770 ps | ||
| T284 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.435528833 | Feb 08 01:51:22 PM UTC 25 | Feb 08 01:54:12 PM UTC 25 | 1799464093 ps | ||
| T285 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_max_throughput_chk.4168065664 | Feb 08 01:54:01 PM UTC 25 | Feb 08 01:54:12 PM UTC 25 | 357320584 ps | ||
| T286 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_alert_test.3381114842 | Feb 08 01:54:13 PM UTC 25 | Feb 08 01:54:26 PM UTC 25 | 338502243 ps | ||
| T287 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_kmac_err_chk.3651691931 | Feb 08 01:54:04 PM UTC 25 | Feb 08 01:54:29 PM UTC 25 | 1058895225 ps | ||
| T288 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all.972159236 | Feb 08 01:54:00 PM UTC 25 | Feb 08 01:54:30 PM UTC 25 | 804655860 ps | ||
| T289 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.2951739235 | Feb 08 01:52:48 PM UTC 25 | Feb 08 01:54:45 PM UTC 25 | 8085551194 ps | ||
| T290 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_max_throughput_chk.3403975057 | Feb 08 01:54:30 PM UTC 25 | Feb 08 01:54:48 PM UTC 25 | 187567674 ps | ||
| T291 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.993924201 | Feb 08 01:51:00 PM UTC 25 | Feb 08 01:55:02 PM UTC 25 | 17012299654 ps | ||
| T292 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.426530704 | Feb 08 01:49:10 PM UTC 25 | Feb 08 01:55:03 PM UTC 25 | 13563647096 ps | ||
| T293 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all.1366230897 | Feb 08 01:54:27 PM UTC 25 | Feb 08 01:55:11 PM UTC 25 | 563656911 ps | ||
| T294 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_kmac_err_chk.4237889503 | Feb 08 01:54:46 PM UTC 25 | Feb 08 01:55:14 PM UTC 25 | 1438924727 ps | ||
| T295 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_alert_test.847907440 | Feb 08 01:55:02 PM UTC 25 | Feb 08 01:55:19 PM UTC 25 | 1080394712 ps | ||
| T296 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_max_throughput_chk.4090024318 | Feb 08 01:55:12 PM UTC 25 | Feb 08 01:55:29 PM UTC 25 | 181255149 ps | ||
| T170 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.144322159 | Feb 08 01:49:59 PM UTC 25 | Feb 08 01:55:32 PM UTC 25 | 8630245489 ps | ||
| T297 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.791917591 | Feb 08 01:50:40 PM UTC 25 | Feb 08 01:55:41 PM UTC 25 | 2742423327 ps | ||
| T298 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all.3077915099 | Feb 08 01:55:04 PM UTC 25 | Feb 08 01:55:41 PM UTC 25 | 396490413 ps | ||
| T299 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_kmac_err_chk.345588335 | Feb 08 01:55:20 PM UTC 25 | Feb 08 01:55:47 PM UTC 25 | 3304699692 ps | ||
| T13 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.2541801826 | Feb 08 01:39:32 PM UTC 25 | Feb 08 01:55:43 PM UTC 25 | 19646683082 ps | ||
| T300 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_max_throughput_chk.1359197704 | Feb 08 01:55:36 PM UTC 25 | Feb 08 01:55:54 PM UTC 25 | 687690472 ps | ||
| T301 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_alert_test.535335545 | Feb 08 01:55:47 PM UTC 25 | Feb 08 01:56:03 PM UTC 25 | 992738804 ps | ||
| T302 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all.1999980562 | Feb 08 01:55:32 PM UTC 25 | Feb 08 01:56:03 PM UTC 25 | 1500278530 ps | ||
| T303 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.1470578075 | Feb 08 01:52:10 PM UTC 25 | Feb 08 01:56:09 PM UTC 25 | 6283290535 ps | ||
| T304 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_max_throughput_chk.3590942073 | Feb 08 01:55:55 PM UTC 25 | Feb 08 01:56:11 PM UTC 25 | 1072970435 ps | ||
| T305 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all.1141068138 | Feb 08 01:55:48 PM UTC 25 | Feb 08 01:56:17 PM UTC 25 | 751121086 ps | ||
| T306 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_kmac_err_chk.3468800449 | Feb 08 01:55:42 PM UTC 25 | Feb 08 01:56:17 PM UTC 25 | 12258989241 ps | ||
| T307 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_alert_test.3027192571 | Feb 08 01:56:12 PM UTC 25 | Feb 08 01:56:24 PM UTC 25 | 356493021 ps | ||
| T308 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_kmac_err_chk.3226866704 | Feb 08 01:56:04 PM UTC 25 | Feb 08 01:56:32 PM UTC 25 | 1770912714 ps | ||
| T309 | /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.4264841430 | Feb 08 01:49:50 PM UTC 25 | Feb 08 01:56:32 PM UTC 25 | 46614560080 ps |
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