RSTMGR Simulation Results

Thursday May 18 2023 07:04:58 UTC

GitHub Revision: ac0bef2ce

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2907120974

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rstmgr_smoke 1.510s 254.327us 50 50 100.00
V1 csr_hw_reset rstmgr_csr_hw_reset 0.890s 144.242us 5 5 100.00
V1 csr_rw rstmgr_csr_rw 0.860s 88.480us 20 20 100.00
V1 csr_bit_bash rstmgr_csr_bit_bash 7.790s 1.551ms 5 5 100.00
V1 csr_aliasing rstmgr_csr_aliasing 2.580s 426.330us 5 5 100.00
V1 csr_mem_rw_with_rand_reset rstmgr_csr_mem_rw_with_rand_reset 1.760s 189.985us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rstmgr_csr_rw 0.860s 88.480us 20 20 100.00
rstmgr_csr_aliasing 2.580s 426.330us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 reset_stretcher rstmgr_por_stretcher 0.990s 204.367us 50 50 100.00
V2 sw_rst rstmgr_sw_rst 2.640s 484.575us 50 50 100.00
V2 sw_rst_reset_race rstmgr_sw_rst_reset_race 1.440s 223.981us 50 50 100.00
V2 reset_info rstmgr_reset 7.200s 2.107ms 50 50 100.00
V2 cpu_info rstmgr_reset 7.200s 2.107ms 50 50 100.00
V2 alert_info rstmgr_reset 7.200s 2.107ms 50 50 100.00
V2 reset_info_capture rstmgr_reset 7.200s 2.107ms 50 50 100.00
V2 stress_all rstmgr_stress_all 45.810s 15.048ms 50 50 100.00
V2 alert_test rstmgr_alert_test 0.830s 95.654us 50 50 100.00
V2 tl_d_oob_addr_access rstmgr_tl_errors 3.260s 455.209us 20 20 100.00
V2 tl_d_illegal_access rstmgr_tl_errors 3.260s 455.209us 20 20 100.00
V2 tl_d_outstanding_access rstmgr_csr_hw_reset 0.890s 144.242us 5 5 100.00
rstmgr_csr_rw 0.860s 88.480us 20 20 100.00
rstmgr_csr_aliasing 2.580s 426.330us 5 5 100.00
rstmgr_same_csr_outstanding 1.470s 256.492us 20 20 100.00
V2 tl_d_partial_access rstmgr_csr_hw_reset 0.890s 144.242us 5 5 100.00
rstmgr_csr_rw 0.860s 88.480us 20 20 100.00
rstmgr_csr_aliasing 2.580s 426.330us 5 5 100.00
rstmgr_same_csr_outstanding 1.470s 256.492us 20 20 100.00
V2 TOTAL 340 340 100.00
V2S tl_intg_err rstmgr_sec_cm 23.060s 16.804ms 5 5 100.00
rstmgr_tl_intg_err 3.260s 1.301ms 20 20 100.00
V2S prim_count_check rstmgr_sec_cm 23.060s 16.804ms 5 5 100.00
V2S prim_fsm_check rstmgr_sec_cm 23.060s 16.804ms 5 5 100.00
V2S sec_cm_bus_integrity rstmgr_tl_intg_err 3.260s 1.301ms 20 20 100.00
V2S sec_cm_scan_intersig_mubi rstmgr_sec_cm_scan_intersig_mubi 1.230s 187.067us 50 50 100.00
V2S sec_cm_leaf_rst_bkgn_chk rstmgr_leaf_rst_cnsty 8.560s 2.358ms 50 50 100.00
V2S sec_cm_leaf_rst_shadow rstmgr_leaf_rst_shadow_attack 1.180s 244.701us 50 50 100.00
V2S sec_cm_leaf_fsm_sparse rstmgr_sec_cm 23.060s 16.804ms 5 5 100.00
V2S sec_cm_sw_rst_config_regwen rstmgr_csr_rw 0.860s 88.480us 20 20 100.00
V2S sec_cm_dump_ctrl_config_regwen rstmgr_csr_rw 0.860s 88.480us 20 20 100.00
V2S TOTAL 175 175 100.00
V3 stress_all_with_rand_reset rstmgr_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 620 620 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 8 8 8 100.00
V2S 5 5 5 100.00
V3 1 0 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.53 99.41 99.31 99.88 -- 99.83 100.00 98.77

Past Results