Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.62	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	1	9	90.00
Crosses	16	3	13	81.25

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	1	7	87.50	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	3	13	81.25	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12740

1

T4

37

T5

37

T6

37

auto[1]

13765

1

T1

4

T3

4

T4

19

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	1	7	87.50

User Defined Bins for reset_info_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
reset_info_cp[8]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8650	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	9275	1			T1	2		T2	1		T3	2
reset_info_cp[2]	3000	1			T1	1		T3	1		T4	2
reset_info_cp[4]	5750	1			T1	1		T3	1		T4	18
reset_info_cp[16]	100	1			T7	2		T11	2		T12	2
reset_info_cp[32]	100	1			T7	1		T11	1		T12	1
reset_info_cp[64]	150	1			T7	2		T11	2		T12	2
reset_info_cp[128]	100	1			T4	1		T5	1		T6	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	3	13	81.25	3

Automatically Generated Cross Bins for capture_cross

Element holes

reset_info_cp	enable_cp	COUNT	AT LEAST	NUMBER	STATUS
[reset_info_cp[8]]	*	--	--	2

Uncovered bins

reset_info_cp	enable_cp	COUNT	AT LEAST	NUMBER	STATUS
[reset_info_cp[128]]	[auto[0]]	0	1	1

Covered bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	4640	1			T4	13		T5	13		T6	13
reset_info_cp[1]	auto[1]	4015	1			T1	1		T3	1		T4	6
reset_info_cp[2]	auto[0]	700	1			T4	1		T5	1		T6	1
reset_info_cp[2]	auto[1]	2300	1			T1	1		T3	1		T4	1
reset_info_cp[4]	auto[0]	2550	1			T4	10		T5	10		T6	10
reset_info_cp[4]	auto[1]	3200	1			T1	1		T3	1		T4	8
reset_info_cp[16]	auto[0]	50	1			T7	1		T11	1		T12	1
reset_info_cp[16]	auto[1]	50	1			T7	1		T11	1		T12	1
reset_info_cp[32]	auto[0]	50	1			T13	1		T37	1		T92	1
reset_info_cp[32]	auto[1]	50	1			T7	1		T11	1		T12	1
reset_info_cp[64]	auto[0]	50	1			T7	1		T11	1		T12	1
reset_info_cp[64]	auto[1]	100	1			T7	1		T11	1		T12	1
reset_info_cp[128]	auto[1]	100	1			T4	1		T5	1		T6	1