Assertions
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Assertions by Category
ASSERTPROPERTIESSEQUENCES
Total733010
Category 0733010


Assertions by Severity
ASSERTPROPERTIESSEQUENCES
Total733010
Severity 0733010


Summary for Assertions
NUMBERPERCENT
Total Number733100.00
Uncovered50.68
Success72899.32
Failure00.00
Incomplete00.00
Without Attempts00.00


Summary for Cover Sequences
NUMBERPERCENT
Total Number10100.00
Uncovered00.00
All Matches10100.00
First Matches10100.00


Detail Report for Assertions

Assertions Uncovered:
ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETESRC
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorAonEnTracksRstPorAonActive_A 002626665000
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorEnTracksRstPorInactive_A 0086984190000
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorIoDiv4EnTracksRstPorIoDiv4Active_A 0020876770000
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorIoEnTracksRstPorIoInactive_A 0083502355000
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorUsbEnTracksRstPorUsbActive_A 0041754345000

Assertions Success:
ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETESRC
tb.dut.AlertsKnownO_A 00188040951298695500
tb.dut.FpvSecCmRegWeOnehotCheck_A 00188040955000
tb.dut.ParameterMatch_A 0050550500
tb.dut.PwrKnownO_A 00188040951298695500
tb.dut.ResetsKnownO_A 00188040951298695500
tb.dut.RstEnKnownO_A 00188040951298695500
tb.dut.TlAReadyKnownO_A 00188040951298695500
tb.dut.TlDValidKnownO_A 00188040951298695500
tb.dut.gen_d0_i2c0_assert.FpvSecCmD0I2c0FsmCheck_A 00188040955000
tb.dut.gen_d0_i2c1_assert.FpvSecCmD0I2c1FsmCheck_A 00188040955000
tb.dut.gen_d0_i2c2_assert.FpvSecCmD0I2c2FsmCheck_A 00188040955000
tb.dut.gen_d0_lc_assert.FpvSecCmD0LcFsmCheck_A 00188040955000
tb.dut.gen_d0_lc_io_assert.FpvSecCmD0LcIoFsmCheck_A 00188040955000
tb.dut.gen_d0_lc_io_div2_assert.FpvSecCmD0LcIoDiv2FsmCheck_A 00188040955000
tb.dut.gen_d0_lc_shadowed_assert.FpvSecCmD0LcShadowedFsmCheck_A 00188040955000
tb.dut.gen_d0_lc_usb_assert.FpvSecCmD0LcUsbFsmCheck_A 00188040955000
tb.dut.gen_d0_spi_device_assert.FpvSecCmD0SpiDeviceFsmCheck_A 00188040955000
tb.dut.gen_d0_spi_host0_assert.FpvSecCmD0SpiHost0FsmCheck_A 00188040955000
tb.dut.gen_d0_spi_host1_assert.FpvSecCmD0SpiHost1FsmCheck_A 00188040955000
tb.dut.gen_d0_sys_assert.FpvSecCmD0SysFsmCheck_A 00188040955000
tb.dut.gen_d0_usb_aon_assert.FpvSecCmD0UsbAonFsmCheck_A 00188040955000
tb.dut.gen_d0_usb_assert.FpvSecCmD0UsbFsmCheck_A 00188040955000
tb.dut.gen_daon_lc_aon_assert.FpvSecCmDAonLcAonFsmCheck_A 00188040955000
tb.dut.gen_daon_lc_assert.FpvSecCmDAonLcFsmCheck_A 00188040955000
tb.dut.gen_daon_lc_io_assert.FpvSecCmDAonLcIoFsmCheck_A 00188040955000
tb.dut.gen_daon_lc_io_div2_assert.FpvSecCmDAonLcIoDiv2FsmCheck_A 00188040955000
tb.dut.gen_daon_lc_shadowed_assert.FpvSecCmDAonLcShadowedFsmCheck_A 00188040955000
tb.dut.gen_daon_lc_usb_assert.FpvSecCmDAonLcUsbFsmCheck_A 00188040955000
tb.dut.gen_daon_por_assert.FpvSecCmDAonPorFsmCheck_A 00188040955000
tb.dut.gen_daon_por_io_assert.FpvSecCmDAonPorIoFsmCheck_A 00188040955000
tb.dut.gen_daon_por_io_div2_assert.FpvSecCmDAonPorIoDiv2FsmCheck_A 00188040955000
tb.dut.gen_daon_por_io_div4_assert.FpvSecCmDAonPorIoDiv4FsmCheck_A 00188040955000
tb.dut.gen_daon_por_usb_assert.FpvSecCmDAonPorUsbFsmCheck_A 00188040955000
tb.dut.gen_daon_sys_io_div4_assert.FpvSecCmDAonSysIoDiv4FsmCheck_A 00188040955000
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_prim_mubi4_sender.OutputsKnown_A 002626665183857000
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_clean_mux.gen_generic.u_impl_generic.selKnown0 00117551125000
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_clean_mux.gen_generic.u_impl_generic.selKnown1 003955345000
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_out_mux.gen_generic.u_impl_generic.selKnown0 00109551045000
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_out_mux.gen_generic.u_impl_generic.selKnown1 003955345000
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_root_mux.gen_generic.u_impl_generic.selKnown0 008305780000
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_root_mux.gen_generic.u_impl_generic.selKnown1 003955345000
tb.dut.gen_rst_por_aon[0].u_por_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.gen_rst_por_aon[0].u_por_scanmode_sync.OutputsKnown_A 00188040951298695500
tb.dut.gen_rst_por_aon[0].u_por_scanmode_sync.gen_no_flops.OutputDelay_A 00188040951298695500
tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux.gen_generic.u_impl_generic.selKnown0 00109551045000
tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux.gen_generic.u_impl_generic.selKnown1 003955345000
tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_prim_mubi4_sender.OutputsKnown_A 002626665181501000
tb.dut.gen_rst_por_aon[1].u_por_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.gen_rst_por_aon[1].u_por_scanmode_sync.OutputsKnown_A 00188040951298695500
tb.dut.gen_rst_por_aon[1].u_por_scanmode_sync.gen_no_flops.OutputDelay_A 00188040951298695500
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[0].LcHandshakeOff_A 00188040951690000
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[0].LcHandshakeOn_A 001880409515665000
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[0].SysHandshakeOff_A 00188040951304039000
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[0].SysHandshakeOn_A 001880409525035000
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[1].LcHandshakeOff_A 00188040951690000
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[1].LcHandshakeOn_A 001880409515665000
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[1].SysHandshakeOff_A 00188040951304039000
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[1].SysHandshakeOn_A 001880409525035000
tb.dut.rstmgr_attrs_sva_if.AlertInfoAttr_A 0050550500
tb.dut.rstmgr_attrs_sva_if.CpuInfoAttr_A 0050550500
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorAboveFall_A 00869841901095500
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorAboveRise_A 00869841901095500
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorIoAboveFall_A 00835023551095500
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorIoAboveRise_A 00835023551095500
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorIoDiv2AboveFall_A 00417527701095500
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorIoDiv2AboveRise_A 00417527701095500
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorIoDiv4AboveFall_A 00208767701095500
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorIoDiv4AboveRise_A 00208767701095500
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorUcbAboveFall_A 00417543451095500
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorUcbAboveRise_A 00417543451095500
tb.dut.rstmgr_cascading_sva_if.CascadeLcToLcAboveFall_A 00869841902785500
tb.dut.rstmgr_cascading_sva_if.CascadeLcToLcAboveRise_A 00869841902785500
tb.dut.rstmgr_cascading_sva_if.CascadeLcToLcAonAboveFall_A 0026266652785500
tb.dut.rstmgr_cascading_sva_if.CascadeLcToLcAonAboveRise_A 0026266652785500
tb.dut.rstmgr_cascading_sva_if.CascadeLcToLcShadowedAboveFall_A 00869841902785500
tb.dut.rstmgr_cascading_sva_if.CascadeLcToLcShadowedAboveRise_A 00869841902785500
tb.dut.rstmgr_cascading_sva_if.CascadePorToAonAboveFall_A 002626665835500
tb.dut.rstmgr_cascading_sva_if.CascadeSysToSysAboveFall_A 00869841902785500
tb.dut.rstmgr_cascading_sva_if.CascadeSysToSysAboveRise_A 00869841902785500
tb.dut.rstmgr_cascading_sva_if.ScanRstToAonRise_A 00262666530000
tb.dut.rstmgr_cascading_sva_if.StablePorToAonRise_A 0026266651095500
tb.dut.rstmgr_cascading_sva_if.g_power_domains[0].CascadeLcToSysAboveFall_A 00188040952785500
tb.dut.rstmgr_cascading_sva_if.g_power_domains[0].CascadeLcToSysAboveRise_A 00188040952785500
tb.dut.rstmgr_cascading_sva_if.g_power_domains[0].CascadeLocalRstToLcAboveFall_A 00188040952785500
tb.dut.rstmgr_cascading_sva_if.g_power_domains[0].CascadeLocalRstToLcAboveRise_A 00188040952785500
tb.dut.rstmgr_cascading_sva_if.g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A 00208767702785500
tb.dut.rstmgr_cascading_sva_if.g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A 00208767702785500
tb.dut.rstmgr_cascading_sva_if.g_power_domains[1].CascadeLcToSysAboveFall_A 00188040952785500
tb.dut.rstmgr_cascading_sva_if.g_power_domains[1].CascadeLcToSysAboveRise_A 00188040952785500
tb.dut.rstmgr_cascading_sva_if.g_power_domains[1].CascadeLocalRstToLcAboveFall_A 00188040952785500
tb.dut.rstmgr_cascading_sva_if.g_power_domains[1].CascadeLocalRstToLcAboveRise_A 00188040952785500
tb.dut.rstmgr_csr_assert.TlulOOBAddrErr_A 0019487580612000
tb.dut.rstmgr_csr_assert.alert_regwen_rd_A 00194875801525500
tb.dut.rstmgr_csr_assert.cpu_regwen_rd_A 00194875801405500
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_0_rd_A 00194875802952000
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_1_rd_A 00194875803161000
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_2_rd_A 00194875803008500
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_3_rd_A 00194875802986500
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_4_rd_A 00194875803206000
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_5_rd_A 00194875802681000
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_6_rd_A 00194875802673500
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_7_rd_A 00194875802837500
tb.dut.rstmgr_csr_assert.sw_rst_regwen_0_rd_A 00194875801374500
tb.dut.rstmgr_csr_assert.sw_rst_regwen_1_rd_A 00194875801453500
tb.dut.rstmgr_csr_assert.sw_rst_regwen_2_rd_A 00194875801188000
tb.dut.rstmgr_csr_assert.sw_rst_regwen_3_rd_A 00194875801524000
tb.dut.rstmgr_csr_assert.sw_rst_regwen_4_rd_A 00194875801737500
tb.dut.rstmgr_csr_assert.sw_rst_regwen_5_rd_A 00194875801254000
tb.dut.rstmgr_csr_assert.sw_rst_regwen_6_rd_A 00194875801378500
tb.dut.rstmgr_csr_assert.sw_rst_regwen_7_rd_A 00194875801317000
tb.dut.rstmgr_rst_en_track_sva_if.D0RstI2c0EnTracksRstI2c0Active_A 00208767701870000
tb.dut.rstmgr_rst_en_track_sva_if.D0RstI2c0EnTracksRstI2c0Inactive_A 00208767702945500
tb.dut.rstmgr_rst_en_track_sva_if.D0RstI2c1EnTracksRstI2c1Active_A 00208767701865000
tb.dut.rstmgr_rst_en_track_sva_if.D0RstI2c1EnTracksRstI2c1Inactive_A 00208767702940500
tb.dut.rstmgr_rst_en_track_sva_if.D0RstI2c2EnTracksRstI2c2Active_A 00208767701905000
tb.dut.rstmgr_rst_en_track_sva_if.D0RstI2c2EnTracksRstI2c2Inactive_A 00208767702975500
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcIoDiv2EnTracksRstLcIoDiv2Active_A 00417527701695000
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcIoDiv2EnTracksRstLcIoDiv2Inactive_A 00417527702785500
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcIoDiv4ShadowedEnTracksRstLcIoDiv4ShadowedActive_A 00208767701700000
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcIoDiv4ShadowedEnTracksRstLcIoDiv4ShadowedInactive_A 00208767702790500
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcIoEnTracksRstLcIoActive_A 00835023551695000
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcIoEnTracksRstLcIoInactive_A 00835023552785500
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcShadowedEnTracksRstLcShadowedActive_A 00869841901695000
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcShadowedEnTracksRstLcShadowedInactive_A 00869841902785500
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcUsbEnTracksRstLcUsbActive_A 00417543451695000
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcUsbEnTracksRstLcUsbInactive_A 00417543452785500
tb.dut.rstmgr_rst_en_track_sva_if.D0RstPorAonEnTracksRstPorAonActive_A 0026266655000
tb.dut.rstmgr_rst_en_track_sva_if.D0RstPorAonEnTracksRstPorAonInactive_A 0026266651090500
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSpiDeviceEnTracksRstSpiDeviceActive_A 00208767701845000
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSpiDeviceEnTracksRstSpiDeviceInactive_A 00208767702920500
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSpiHost0EnTracksRstSpiHost0Active_A 00835023551850000
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSpiHost0EnTracksRstSpiHost0Inactive_A 00835023552930500
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSpiHost1EnTracksRstSpiHost1Active_A 00417527701860000
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSpiHost1EnTracksRstSpiHost1Inactive_A 00417527702945500
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSysEnTracksRstSysActive_A 00869841901695000
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSysEnTracksRstSysInactive_A 00869841902785500
tb.dut.rstmgr_rst_en_track_sva_if.D0RstUsbAonEnTracksRstUsbAonActive_A 0026266651870000
tb.dut.rstmgr_rst_en_track_sva_if.D0RstUsbAonEnTracksRstUsbAonInactive_A 0026266652920500
tb.dut.rstmgr_rst_en_track_sva_if.D0RstUsbEnTracksRstUsbActive_A 00417543451840000
tb.dut.rstmgr_rst_en_track_sva_if.D0RstUsbEnTracksRstUsbInactive_A 00417543452920500
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcAonEnTracksRstLcAonActive_A 0026266651695000
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcAonEnTracksRstLcAonInactive_A 0026266652780500
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcIoDiv2EnTracksRstLcIoDiv2Active_A 00417527701690000
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcIoDiv2EnTracksRstLcIoDiv2Inactive_A 00417527702785500
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcIoDiv4ShadowedEnTracksRstLcIoDiv4ShadowedActive_A 00208767701695000
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcIoDiv4ShadowedEnTracksRstLcIoDiv4ShadowedInactive_A 00208767702790500
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcIoEnTracksRstLcIoActive_A 00835023551695000
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcIoEnTracksRstLcIoInactive_A 00835023552785500
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcShadowedEnTracksRstLcShadowedActive_A 00869841901700000
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcShadowedEnTracksRstLcShadowedInactive_A 00869841902790500
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcUsbEnTracksRstLcUsbActive_A 00417543451690000
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcUsbEnTracksRstLcUsbInactive_A 00417543452785500
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorAonEnTracksRstPorAonInactive_A 0026266651095500
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorEnTracksRstPorActive_A 00869841905000
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorIoDiv2EnTracksRstPorIoDiv2Active_A 00417527705000
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorIoDiv2EnTracksRstPorIoDiv2Inactive_A 0041752770177500
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorIoDiv4EnTracksRstPorIoDiv4Inactive_A 00208767701095500
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorIoEnTracksRstPorIoActive_A 00835023555000
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorUsbEnTracksRstPorUsbInactive_A 0041754345177500
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstSysIoDiv4EnTracksRstSysIoDiv4Active_A 00208767701695000
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstSysIoDiv4EnTracksRstSysIoDiv4Inactive_A 00208767702785500
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[0].RstEnOff_A 00208767701825000
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[0].RstEnOn_A 0020876770155000
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[0].RstNOff_A 00208767701825000
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[0].RstNOn_A 0020876770155000
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[1].RstEnOff_A 00835023551665000
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[1].RstEnOn_A 0083502355155000
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[1].RstNOff_A 00835023551665000
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[1].RstNOn_A 0083502355155000
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[2].RstEnOff_A 00417527701680000
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[2].RstEnOn_A 0041752770165000
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[2].RstNOff_A 00417527701680000
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[2].RstNOn_A 0041752770165000
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[3].RstEnOff_A 00417543451655000
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[3].RstEnOn_A 0041754345140000
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[3].RstNOff_A 00417543451655000
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[3].RstNOn_A 0041754345140000
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tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[4].RstEnOn_A 002626665180000
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[4].RstNOff_A 0026266652885500
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[4].RstNOn_A 002626665180000
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tb.dut.tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_device.aDataKnown_M 001948820063280500
tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A 0019487580298000
tb.dut.tlul_assert_device.gen_device.contigMask_M 0019488200114134000
tb.dut.tlul_assert_device.gen_device.dDataKnown_A 0019488200218323500
tb.dut.tlul_assert_device.gen_device.legalAOpcodeErr_A 0019487580404000
tb.dut.tlul_assert_device.gen_device.legalAParam_M 0019488200149091000
tb.dut.tlul_assert_device.gen_device.legalDParam_A 0019488200410010000
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M 0019488200149091000
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A 0019488200410010000
tb.dut.tlul_assert_device.gen_device.respOpcode_A 0019488200410010000
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A 0019488200410010000
tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A 0019487580200000
tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A 0019487580148000
tb.dut.tlul_assert_device.p_dbw.TlDbw_A 0062062000
tb.dut.u_alert_info.CntStoreSlot_A 0050550500
tb.dut.u_alert_info.CntWidth_A 0050550500
tb.dut.u_cpu_info.CntStoreSlot_A 0050550500
tb.dut.u_cpu_info.CntWidth_A 0050550500
tb.dut.u_ctrl_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_ctrl_scanmode_sync.OutputsKnown_A 00208767701453810000
tb.dut.u_ctrl_scanmode_sync.gen_no_flops.OutputDelay_A 00208767701453810000
tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00279052740000
tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 003955345000
tb.dut.u_d0_i2c0.u_prim_mubi4_sender.OutputsKnown_A 00208767701264916000
tb.dut.u_d0_i2c0.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00294552895000
tb.dut.u_d0_i2c0.u_rst_mux.gen_generic.u_impl_generic.selKnown1 003955345000
tb.dut.u_d0_i2c0.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_d0_i2c0.u_scanmode_sync.OutputsKnown_A 00188040951298695500
tb.dut.u_d0_i2c0.u_scanmode_sync.gen_no_flops.OutputDelay_A 00188040951298695500
tb.dut.u_d0_i2c1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00279052740000
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tb.dut.u_d0_i2c1.u_prim_mubi4_sender.OutputsKnown_A 00208767701271206000
tb.dut.u_d0_i2c1.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00294052890000
tb.dut.u_d0_i2c1.u_rst_mux.gen_generic.u_impl_generic.selKnown1 003955345000
tb.dut.u_d0_i2c1.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_d0_i2c1.u_scanmode_sync.OutputsKnown_A 00188040951298695500
tb.dut.u_d0_i2c1.u_scanmode_sync.gen_no_flops.OutputDelay_A 00188040951298695500
tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00279052740000
tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 003955345000
tb.dut.u_d0_i2c2.u_prim_mubi4_sender.OutputsKnown_A 00208767701260871000
tb.dut.u_d0_i2c2.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00297052920000
tb.dut.u_d0_i2c2.u_rst_mux.gen_generic.u_impl_generic.selKnown1 003955345000
tb.dut.u_d0_i2c2.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_d0_i2c2.u_scanmode_sync.OutputsKnown_A 00188040951298695500
tb.dut.u_d0_i2c2.u_scanmode_sync.gen_no_flops.OutputDelay_A 00188040951298695500
tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00279052740000
tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 003955345000
tb.dut.u_d0_lc.u_prim_mubi4_sender.OutputsKnown_A 00869841905447021500
tb.dut.u_d0_lc.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00278552735000
tb.dut.u_d0_lc.u_rst_mux.gen_generic.u_impl_generic.selKnown1 003955345000
tb.dut.u_d0_lc.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_d0_lc.u_scanmode_sync.OutputsKnown_A 00188040951298695500
tb.dut.u_d0_lc.u_scanmode_sync.gen_no_flops.OutputDelay_A 00188040951298695500
tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00279052740000
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tb.dut.u_d0_lc_io.u_prim_mubi4_sender.OutputsKnown_A 00835023555229093500
tb.dut.u_d0_lc_io.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00278552735000
tb.dut.u_d0_lc_io.u_rst_mux.gen_generic.u_impl_generic.selKnown1 003955345000
tb.dut.u_d0_lc_io.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_d0_lc_io.u_scanmode_sync.OutputsKnown_A 00188040951298695500
tb.dut.u_d0_lc_io.u_scanmode_sync.gen_no_flops.OutputDelay_A 00188040951298695500
tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00279052740000
tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 003955345000
tb.dut.u_d0_lc_io_div2.u_prim_mubi4_sender.OutputsKnown_A 00417527702613334000
tb.dut.u_d0_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00278552735000
tb.dut.u_d0_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic.selKnown1 003955345000
tb.dut.u_d0_lc_io_div2.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_d0_lc_io_div2.u_scanmode_sync.OutputsKnown_A 00188040951298695500
tb.dut.u_d0_lc_io_div2.u_scanmode_sync.gen_no_flops.OutputDelay_A 00188040951298695500
tb.dut.u_d0_lc_io_div4.u_prim_mubi4_sender.OutputsKnown_A 00208767701302866000
tb.dut.u_d0_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00278552735000
tb.dut.u_d0_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown1 003955345000
tb.dut.u_d0_lc_io_div4.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_d0_lc_io_div4.u_scanmode_sync.OutputsKnown_A 00188040951298695500
tb.dut.u_d0_lc_io_div4.u_scanmode_sync.gen_no_flops.OutputDelay_A 00188040951298695500
tb.dut.u_d0_lc_io_div4_shadowed.u_prim_mubi4_sender.OutputsKnown_A 00208767701302866000
tb.dut.u_d0_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00278552735000
tb.dut.u_d0_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown1 003955345000
tb.dut.u_d0_lc_io_div4_shadowed.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_d0_lc_io_div4_shadowed.u_scanmode_sync.OutputsKnown_A 00188040951298695500
tb.dut.u_d0_lc_io_div4_shadowed.u_scanmode_sync.gen_no_flops.OutputDelay_A 00188040951298695500
tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00279052740000
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tb.dut.u_d0_lc_shadowed.u_prim_mubi4_sender.OutputsKnown_A 00869841905447316500
tb.dut.u_d0_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00278552735000
tb.dut.u_d0_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown1 003955345000
tb.dut.u_d0_lc_shadowed.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_d0_lc_shadowed.u_scanmode_sync.OutputsKnown_A 00188040951298695500
tb.dut.u_d0_lc_shadowed.u_scanmode_sync.gen_no_flops.OutputDelay_A 00188040951298695500
tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00279052740000
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tb.dut.u_d0_lc_usb.u_prim_mubi4_sender.OutputsKnown_A 00417543452613349000
tb.dut.u_d0_lc_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00278552735000
tb.dut.u_d0_lc_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown1 003955345000
tb.dut.u_d0_lc_usb.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
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tb.dut.u_d0_lc_usb.u_scanmode_sync.gen_no_flops.OutputDelay_A 00188040951298695500
tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00279052740000
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tb.dut.u_d0_spi_device.u_prim_mubi4_sender.OutputsKnown_A 00208767701266531000
tb.dut.u_d0_spi_device.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00292052870000
tb.dut.u_d0_spi_device.u_rst_mux.gen_generic.u_impl_generic.selKnown1 003955345000
tb.dut.u_d0_spi_device.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_d0_spi_device.u_scanmode_sync.OutputsKnown_A 00188040951298695500
tb.dut.u_d0_spi_device.u_scanmode_sync.gen_no_flops.OutputDelay_A 00188040951298695500
tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00279052740000
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tb.dut.u_d0_spi_host0.u_prim_mubi4_sender.OutputsKnown_A 00835023555080183500
tb.dut.u_d0_spi_host0.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00292552875000
tb.dut.u_d0_spi_host0.u_rst_mux.gen_generic.u_impl_generic.selKnown1 003955345000
tb.dut.u_d0_spi_host0.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
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tb.dut.u_d0_spi_host0.u_scanmode_sync.gen_no_flops.OutputDelay_A 00188040951298695500
tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00279052740000
tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 003955345000
tb.dut.u_d0_spi_host1.u_prim_mubi4_sender.OutputsKnown_A 00417527702540674000
tb.dut.u_d0_spi_host1.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00294052890000
tb.dut.u_d0_spi_host1.u_rst_mux.gen_generic.u_impl_generic.selKnown1 003955345000
tb.dut.u_d0_spi_host1.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
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tb.dut.u_d0_spi_host1.u_scanmode_sync.gen_no_flops.OutputDelay_A 00188040951298695500
tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00279052740000
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tb.dut.u_d0_sys.u_prim_mubi4_sender.OutputsKnown_A 00869841905408211500
tb.dut.u_d0_sys.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00278552735000
tb.dut.u_d0_sys.u_rst_mux.gen_generic.u_impl_generic.selKnown1 003955345000
tb.dut.u_d0_sys.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
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tb.dut.u_d0_sys.u_scanmode_sync.gen_no_flops.OutputDelay_A 00188040951298695500
tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00279052740000
tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 003955345000
tb.dut.u_d0_usb.u_prim_mubi4_sender.OutputsKnown_A 00417543452553179000
tb.dut.u_d0_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00291552865000
tb.dut.u_d0_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown1 003955345000
tb.dut.u_d0_usb.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_d0_usb.u_scanmode_sync.OutputsKnown_A 00188040951298695500
tb.dut.u_d0_usb.u_scanmode_sync.gen_no_flops.OutputDelay_A 00188040951298695500
tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00277552725000
tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 003955345000
tb.dut.u_d0_usb_aon.u_prim_mubi4_sender.OutputsKnown_A 002626665157085000
tb.dut.u_d0_usb_aon.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00295052900000
tb.dut.u_d0_usb_aon.u_rst_mux.gen_generic.u_impl_generic.selKnown1 003955345000
tb.dut.u_d0_usb_aon.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_d0_usb_aon.u_scanmode_sync.OutputsKnown_A 00188040951298695500
tb.dut.u_d0_usb_aon.u_scanmode_sync.gen_no_flops.OutputDelay_A 00188040951298695500
tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00279052740000
tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 003955345000
tb.dut.u_daon_lc.u_prim_mubi4_sender.OutputsKnown_A 00869841905539682500
tb.dut.u_daon_lc.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00278552735000
tb.dut.u_daon_lc.u_rst_mux.gen_generic.u_impl_generic.selKnown1 003955345000
tb.dut.u_daon_lc.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_daon_lc.u_scanmode_sync.OutputsKnown_A 00188040951298695500
tb.dut.u_daon_lc.u_scanmode_sync.gen_no_flops.OutputDelay_A 00188040951298695500
tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00277552725000
tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 003955345000
tb.dut.u_daon_lc_aon.u_prim_mubi4_sender.OutputsKnown_A 002626665164561000
tb.dut.u_daon_lc_aon.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00278552735000
tb.dut.u_daon_lc_aon.u_rst_mux.gen_generic.u_impl_generic.selKnown1 003955345000
tb.dut.u_daon_lc_aon.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_daon_lc_aon.u_scanmode_sync.OutputsKnown_A 00188040951298695500
tb.dut.u_daon_lc_aon.u_scanmode_sync.gen_no_flops.OutputDelay_A 00188040951298695500
tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00279052740000
tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 003955345000
tb.dut.u_daon_lc_io.u_prim_mubi4_sender.OutputsKnown_A 00835023555317785000
tb.dut.u_daon_lc_io.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00278552735000
tb.dut.u_daon_lc_io.u_rst_mux.gen_generic.u_impl_generic.selKnown1 003955345000
tb.dut.u_daon_lc_io.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_daon_lc_io.u_scanmode_sync.OutputsKnown_A 00188040951298695500
tb.dut.u_daon_lc_io.u_scanmode_sync.gen_no_flops.OutputDelay_A 00188040951298695500
tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00279052740000
tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 003955345000
tb.dut.u_daon_lc_io_div2.u_prim_mubi4_sender.OutputsKnown_A 00417527702657790000
tb.dut.u_daon_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00278552735000
tb.dut.u_daon_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic.selKnown1 003955345000
tb.dut.u_daon_lc_io_div2.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_daon_lc_io_div2.u_scanmode_sync.OutputsKnown_A 00188040951298695500
tb.dut.u_daon_lc_io_div2.u_scanmode_sync.gen_no_flops.OutputDelay_A 00188040951298695500
tb.dut.u_daon_lc_io_div4.u_prim_mubi4_sender.OutputsKnown_A 00208767701325094000
tb.dut.u_daon_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00278552735000
tb.dut.u_daon_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown1 003955345000
tb.dut.u_daon_lc_io_div4.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_daon_lc_io_div4.u_scanmode_sync.OutputsKnown_A 00188040951298695500
tb.dut.u_daon_lc_io_div4.u_scanmode_sync.gen_no_flops.OutputDelay_A 00188040951298695500
tb.dut.u_daon_lc_io_div4_shadowed.u_prim_mubi4_sender.OutputsKnown_A 00208767701325094000
tb.dut.u_daon_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00278552735000
tb.dut.u_daon_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown1 003955345000
tb.dut.u_daon_lc_io_div4_shadowed.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_daon_lc_io_div4_shadowed.u_scanmode_sync.OutputsKnown_A 00188040951298695500
tb.dut.u_daon_lc_io_div4_shadowed.u_scanmode_sync.gen_no_flops.OutputDelay_A 00188040951298695500
tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00279052740000
tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 003955345000
tb.dut.u_daon_lc_shadowed.u_prim_mubi4_sender.OutputsKnown_A 00869841905539457500
tb.dut.u_daon_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00278552735000
tb.dut.u_daon_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown1 003955345000
tb.dut.u_daon_lc_shadowed.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_daon_lc_shadowed.u_scanmode_sync.OutputsKnown_A 00188040951298695500
tb.dut.u_daon_lc_shadowed.u_scanmode_sync.gen_no_flops.OutputDelay_A 00188040951298695500
tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00279052740000
tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 003955345000
tb.dut.u_daon_lc_usb.u_prim_mubi4_sender.OutputsKnown_A 00417543452657805000
tb.dut.u_daon_lc_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00278552735000
tb.dut.u_daon_lc_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown1 003955345000
tb.dut.u_daon_lc_usb.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_daon_lc_usb.u_scanmode_sync.OutputsKnown_A 00188040951298695500
tb.dut.u_daon_lc_usb.u_scanmode_sync.gen_no_flops.OutputDelay_A 00188040951298695500
tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00279052740000
tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 003955345000
tb.dut.u_daon_por.u_prim_mubi4_sender.OutputsKnown_A 00869841906061026000
tb.dut.u_daon_por.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00109551045000
tb.dut.u_daon_por.u_rst_mux.gen_generic.u_impl_generic.selKnown1 003955345000
tb.dut.u_daon_por.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_daon_por.u_scanmode_sync.OutputsKnown_A 00188040951298695500
tb.dut.u_daon_por.u_scanmode_sync.gen_no_flops.OutputDelay_A 00188040951298695500
tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00279052740000
tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 003955345000
tb.dut.u_daon_por_io.u_prim_mubi4_sender.OutputsKnown_A 00835023555818463000
tb.dut.u_daon_por_io.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00109551045000
tb.dut.u_daon_por_io.u_rst_mux.gen_generic.u_impl_generic.selKnown1 003955345000
tb.dut.u_daon_por_io.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_daon_por_io.u_scanmode_sync.OutputsKnown_A 00188040951298695500
tb.dut.u_daon_por_io.u_scanmode_sync.gen_no_flops.OutputDelay_A 00188040951298695500
tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00279052740000
tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 003955345000
tb.dut.u_daon_por_io_div2.u_prim_mubi4_sender.OutputsKnown_A 00417527702908817500
tb.dut.u_daon_por_io_div2.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00109551045000
tb.dut.u_daon_por_io_div2.u_rst_mux.gen_generic.u_impl_generic.selKnown1 003955345000
tb.dut.u_daon_por_io_div2.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_daon_por_io_div2.u_scanmode_sync.OutputsKnown_A 00188040951298695500
tb.dut.u_daon_por_io_div2.u_scanmode_sync.gen_no_flops.OutputDelay_A 00188040951298695500
tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00279052740000
tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 003955345000
tb.dut.u_daon_por_io_div4.u_prim_mubi4_sender.OutputsKnown_A 00208767701453810000
tb.dut.u_daon_por_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00109551045000
tb.dut.u_daon_por_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown1 003955345000
tb.dut.u_daon_por_io_div4.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_daon_por_io_div4.u_scanmode_sync.OutputsKnown_A 00188040951298695500
tb.dut.u_daon_por_io_div4.u_scanmode_sync.gen_no_flops.OutputDelay_A 00188040951298695500
tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00279052740000
tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 003955345000
tb.dut.u_daon_por_usb.u_prim_mubi4_sender.OutputsKnown_A 00417543452909027500
tb.dut.u_daon_por_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00109551045000
tb.dut.u_daon_por_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown1 003955345000
tb.dut.u_daon_por_usb.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_daon_por_usb.u_scanmode_sync.OutputsKnown_A 00188040951298695500
tb.dut.u_daon_por_usb.u_scanmode_sync.gen_no_flops.OutputDelay_A 00188040951298695500
tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00279052740000
tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 003955345000
tb.dut.u_daon_sys_io_div4.u_prim_mubi4_sender.OutputsKnown_A 00208767701315679000
tb.dut.u_daon_sys_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00278552735000
tb.dut.u_daon_sys_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown1 003955345000
tb.dut.u_daon_sys_io_div4.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_daon_sys_io_div4.u_scanmode_sync.OutputsKnown_A 00188040951298695500
tb.dut.u_daon_sys_io_div4.u_scanmode_sync.gen_no_flops.OutputDelay_A 00188040951298695500
tb.dut.u_lc_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic.selKnown0 00278552735000
tb.dut.u_lc_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic.selKnown1 003955345000
tb.dut.u_lc_src.u_rst_aon_mux.gen_generic.u_impl_generic.selKnown0 00278552735000
tb.dut.u_lc_src.u_rst_aon_mux.gen_generic.u_impl_generic.selKnown1 003955345000
tb.dut.u_reg.en2addrHit 0019487580132054000
tb.dut.u_reg.reAfterRv 0019487580132039000
tb.dut.u_reg.rePulse 001948758071938000
tb.dut.u_reg.u_chk.PayLoadWidthCheck 0062062000
tb.dut.u_reg.u_reg_if.AllowedLatency_A 0062062000
tb.dut.u_reg.u_reg_if.MatchedWidthAssert 0062062000
tb.dut.u_reg.u_reg_if.u_err.dataWidthOnly32_A 0062062000
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A 0062062000
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck 0062062000
tb.dut.u_reg.u_rsp_intg_gen.DataWidthCheck_A 0062062000
tb.dut.u_reg.u_rsp_intg_gen.PayLoadWidthCheck 0062062000
tb.dut.u_reg.wePulse 001948758060101000
tb.dut.u_sys_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic.selKnown0 00278552735000
tb.dut.u_sys_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic.selKnown1 003955345000
tb.dut.u_sys_src.u_rst_aon_mux.gen_generic.u_impl_generic.selKnown0 00278552735000
tb.dut.u_sys_src.u_rst_aon_mux.gen_generic.u_impl_generic.selKnown1 003955345000


Detail Report for Cover Sequences

Cover Sequences All Matches:
COVER SEQUENCESCATEGORYSEVERITYATTEMPTSALL MATCHESFIRST MATCHESINCOMPLETESRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C 001948820016655166550
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C 0019488200370037000
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C 0019488200370037000
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C 0019488200290029000
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C 00194882002502500
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C 0019488200235023500
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C 00194882009009000
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C 00194882004804800
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C 001948820015610156100
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C 0019488200833860833860455

Cover Sequences First Matches:
COVER SEQUENCESCATEGORYSEVERITYATTEMPTSALL MATCHESFIRST MATCHESINCOMPLETESRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C 001948820016655166550
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C 0019488200370037000
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C 0019488200370037000
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C 0019488200290029000
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C 00194882002502500
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C 0019488200235023500
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C 00194882009009000
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C 00194882004804800
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C 001948820015610156100
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C 0019488200833860833860455

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