Group : rstmgr_env_pkg::rstmgr_env_cov::reset_stretcher_cg
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Group : rstmgr_env_pkg::rstmgr_env_cov::reset_stretcher_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv



Summary for Group rstmgr_env_pkg::rstmgr_env_cov::reset_stretcher_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00


Variables for Group rstmgr_env_pkg::rstmgr_env_cov::reset_stretcher_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
count_cp 4 0 4 100.00 100 1 1 0
length_cp 8 0 8 100.00 100 1 1 0


Summary for Variable count_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for count_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
others 11240 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
cb[0] 1260 1 T1 1 T2 3 T3 1
cb[1] 1140 1 T2 4 T4 4 T5 4
cb[2] 1140 1 T2 4 T4 4 T5 4
cb[3] 1140 1 T2 4 T4 4 T5 4



Summary for Variable length_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for length_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
others 12860 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
lb[0] 475 1 T2 1 T7 3 T11 3
lb[1] 170 1 T7 2 T11 2 T12 2
lb[2] 300 1 T2 4 T7 1 T11 1
lb[3] 450 1 T2 3 T7 5 T11 5
lb[4] 510 1 T2 5 T4 2 T5 2
lb[5] 340 1 T2 2 T4 1 T5 1
lb[6] 605 1 T2 4 T7 3 T11 3
lb[7] 210 1 T7 2 T11 2 T12 2

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