Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
11690 |
1 |
|
|
T4 |
29 |
|
T5 |
29 |
|
T6 |
29 |
auto[1] |
14815 |
1 |
|
|
T1 |
4 |
|
T3 |
4 |
|
T4 |
27 |
Summary for Variable reset_info_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
1 |
7 |
87.50 |
User Defined Bins for reset_info_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
reset_info_cp[8] |
0 |
1 |
1 |
|
Excluded/Illegal bins
NAME | COUNT | STATUS |
others |
8650 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
reset_info_cp[1] |
9275 |
1 |
|
|
T1 |
2 |
|
T2 |
1 |
|
T3 |
2 |
reset_info_cp[2] |
3000 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
2 |
reset_info_cp[4] |
5750 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
18 |
reset_info_cp[16] |
100 |
1 |
|
|
T7 |
2 |
|
T11 |
2 |
|
T12 |
2 |
reset_info_cp[32] |
100 |
1 |
|
|
T7 |
1 |
|
T11 |
1 |
|
T12 |
1 |
reset_info_cp[64] |
150 |
1 |
|
|
T7 |
2 |
|
T11 |
2 |
|
T12 |
2 |
reset_info_cp[128] |
100 |
1 |
|
|
T4 |
1 |
|
T5 |
1 |
|
T6 |
1 |
Summary for Cross capture_cross
Samples crossed: reset_info_cp enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
16 |
4 |
12 |
75.00 |
4 |
Automatically Generated Cross Bins for capture_cross
Element holes
reset_info_cp | enable_cp | COUNT | AT LEAST | NUMBER | STATUS |
[reset_info_cp[8]] |
* |
-- |
-- |
2 |
|
Uncovered bins
reset_info_cp | enable_cp | COUNT | AT LEAST | NUMBER | STATUS |
[reset_info_cp[32]] |
[auto[1]] |
0 |
1 |
1 |
|
[reset_info_cp[128]] |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
reset_info_cp | enable_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
reset_info_cp[1] |
auto[0] |
4340 |
1 |
|
|
T4 |
11 |
|
T5 |
11 |
|
T6 |
11 |
reset_info_cp[1] |
auto[1] |
4315 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
8 |
reset_info_cp[2] |
auto[0] |
950 |
1 |
|
|
T4 |
1 |
|
T5 |
1 |
|
T6 |
1 |
reset_info_cp[2] |
auto[1] |
2050 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
reset_info_cp[4] |
auto[0] |
2250 |
1 |
|
|
T4 |
9 |
|
T5 |
9 |
|
T6 |
9 |
reset_info_cp[4] |
auto[1] |
3500 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
9 |
reset_info_cp[16] |
auto[0] |
50 |
1 |
|
|
T7 |
1 |
|
T11 |
1 |
|
T12 |
1 |
reset_info_cp[16] |
auto[1] |
50 |
1 |
|
|
T7 |
1 |
|
T11 |
1 |
|
T12 |
1 |
reset_info_cp[32] |
auto[0] |
100 |
1 |
|
|
T7 |
1 |
|
T11 |
1 |
|
T12 |
1 |
reset_info_cp[64] |
auto[0] |
50 |
1 |
|
|
T7 |
1 |
|
T11 |
1 |
|
T12 |
1 |
reset_info_cp[64] |
auto[1] |
100 |
1 |
|
|
T7 |
1 |
|
T11 |
1 |
|
T12 |
1 |
reset_info_cp[128] |
auto[0] |
100 |
1 |
|
|
T4 |
1 |
|
T5 |
1 |
|
T6 |
1 |