Group : rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg
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Group : rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
80.77 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv



Summary for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 1 9 90.00
Crosses 16 4 12 75.00


Variables for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
enable_cp 2 0 2 100.00 100 1 1 2
reset_info_cp 8 1 7 87.50 100 1 1 0


Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
capture_cross 16 4 12 75.00 100 1 1 0


Summary for Variable enable_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for enable_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 11690 1 T4 29 T5 29 T6 29
auto[1] 14815 1 T1 4 T3 4 T4 27



Summary for Variable reset_info_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 1 7 87.50


User Defined Bins for reset_info_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
reset_info_cp[8] 0 1 1


Excluded/Illegal bins
NAMECOUNTSTATUS
others 8650 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
reset_info_cp[1] 9275 1 T1 2 T2 1 T3 2
reset_info_cp[2] 3000 1 T1 1 T3 1 T4 2
reset_info_cp[4] 5750 1 T1 1 T3 1 T4 18
reset_info_cp[16] 100 1 T7 2 T11 2 T12 2
reset_info_cp[32] 100 1 T7 1 T11 1 T12 1
reset_info_cp[64] 150 1 T7 2 T11 2 T12 2
reset_info_cp[128] 100 1 T4 1 T5 1 T6 1



Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 4 12 75.00 4


Automatically Generated Cross Bins for capture_cross

Element holes
reset_info_cpenable_cpCOUNTAT LEASTNUMBERSTATUS
[reset_info_cp[8]] * -- -- 2


Uncovered bins
reset_info_cpenable_cpCOUNTAT LEASTNUMBERSTATUS
[reset_info_cp[32]] [auto[1]] 0 1 1
[reset_info_cp[128]] [auto[1]] 0 1 1


Covered bins
reset_info_cpenable_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
reset_info_cp[1] auto[0] 4340 1 T4 11 T5 11 T6 11
reset_info_cp[1] auto[1] 4315 1 T1 1 T3 1 T4 8
reset_info_cp[2] auto[0] 950 1 T4 1 T5 1 T6 1
reset_info_cp[2] auto[1] 2050 1 T1 1 T3 1 T4 1
reset_info_cp[4] auto[0] 2250 1 T4 9 T5 9 T6 9
reset_info_cp[4] auto[1] 3500 1 T1 1 T3 1 T4 9
reset_info_cp[16] auto[0] 50 1 T7 1 T11 1 T12 1
reset_info_cp[16] auto[1] 50 1 T7 1 T11 1 T12 1
reset_info_cp[32] auto[0] 100 1 T7 1 T11 1 T12 1
reset_info_cp[64] auto[0] 50 1 T7 1 T11 1 T12 1
reset_info_cp[64] auto[1] 100 1 T7 1 T11 1 T12 1
reset_info_cp[128] auto[0] 100 1 T4 1 T5 1 T6 1

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