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LINE 63
EXPRESSION (reg_we && ((!addrmiss)))
---1-- ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T51,T52,T55 |
1 | 1 | Covered | T1,T3,T4 |
LINE 75
EXPRESSION (intg_err || reg_we_err)
----1--- -----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T56,T57,T58 |
1 | 0 | Covered | T46,T53,T54 |
LINE 82
EXPRESSION (err_q | intg_err | reg_we_err)
--1-- ----2--- -----3----
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Covered | T56,T57,T58 |
0 | 1 | 0 | Covered | T46,T53,T54 |
1 | 0 | 0 | Covered | T56,T46,T53 |
LINE 124
EXPRESSION ((devmode_i & addrmiss) | wr_err | intg_err)
-----------1---------- ---2-- ----3---
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Covered | T46,T53,T54 |
0 | 1 | 0 | Covered | T51,T52,T55 |
1 | 0 | 0 | Covered | T51,T52,T55 |
LINE 124
SUB-EXPRESSION (devmode_i & addrmiss)
----1---- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T51,T52,T55 |
LINE 433
EXPRESSION (alert_info_ctrl_we & alert_regwen_qs)
---------1-------- -------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T46,T53,T59 |
1 | 1 | Covered | T1,T3,T4 |
LINE 554
EXPRESSION (cpu_info_ctrl_we & cpu_regwen_qs)
--------1------- ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T46,T53,T54 |
1 | 1 | Covered | T1,T3,T4 |
LINE 880
EXPRESSION (sw_rst_ctrl_n_0_we & sw_rst_regwen_0_qs)
---------1-------- ---------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T8,T9,T10 |
1 | 1 | Covered | T1,T3,T7 |
LINE 912
EXPRESSION (sw_rst_ctrl_n_1_we & sw_rst_regwen_1_qs)
---------1-------- ---------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T8 |
1 | 1 | Covered | T7,T8,T9 |
LINE 944
EXPRESSION (sw_rst_ctrl_n_2_we & sw_rst_regwen_2_qs)
---------1-------- ---------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T8 |
1 | 1 | Covered | T7,T8,T9 |
LINE 976
EXPRESSION (sw_rst_ctrl_n_3_we & sw_rst_regwen_3_qs)
---------1-------- ---------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T8 |
1 | 1 | Covered | T7,T8,T9 |
LINE 1008
EXPRESSION (sw_rst_ctrl_n_4_we & sw_rst_regwen_4_qs)
---------1-------- ---------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T8,T9,T10 |
1 | 1 | Covered | T1,T3,T7 |
LINE 1040
EXPRESSION (sw_rst_ctrl_n_5_we & sw_rst_regwen_5_qs)
---------1-------- ---------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T8 |
1 | 1 | Covered | T7,T8,T9 |
LINE 1072
EXPRESSION (sw_rst_ctrl_n_6_we & sw_rst_regwen_6_qs)
---------1-------- ---------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T8 |
1 | 1 | Covered | T7,T8,T9 |
LINE 1104
EXPRESSION (sw_rst_ctrl_n_7_we & sw_rst_regwen_7_qs)
---------1-------- ---------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T8 |
1 | 1 | Covered | T7,T8,T9 |
LINE 1219
EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_ALERT_TEST_OFFSET)
---------------------------1--------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
LINE 1220
EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_RESET_REQ_OFFSET)
--------------------------1--------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
LINE 1221
EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_RESET_INFO_OFFSET)
---------------------------1--------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 1222
EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_ALERT_REGWEN_OFFSET)
----------------------------1---------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
LINE 1223
EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_ALERT_INFO_CTRL_OFFSET)
-----------------------------1-----------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
LINE 1224
EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_ALERT_INFO_ATTR_OFFSET)
-----------------------------1-----------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 1225
EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_ALERT_INFO_OFFSET)
---------------------------1--------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
LINE 1226
EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_CPU_REGWEN_OFFSET)
---------------------------1--------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
LINE 1227
EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_CPU_INFO_CTRL_OFFSET)
----------------------------1----------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
LINE 1228
EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_CPU_INFO_ATTR_OFFSET)
----------------------------1----------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
LINE 1229
EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_CPU_INFO_OFFSET)
--------------------------1-------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
LINE 1230
EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_SW_RST_REGWEN_0_OFFSET)
-----------------------------1-----------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
LINE 1231
EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_SW_RST_REGWEN_1_OFFSET)
-----------------------------1-----------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
LINE 1232
EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_SW_RST_REGWEN_2_OFFSET)
-----------------------------1-----------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
LINE 1233
EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_SW_RST_REGWEN_3_OFFSET)
-----------------------------1-----------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 1234
EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_SW_RST_REGWEN_4_OFFSET)
-----------------------------1-----------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
LINE 1235
EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_SW_RST_REGWEN_5_OFFSET)
-----------------------------1-----------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
LINE 1236
EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_SW_RST_REGWEN_6_OFFSET)
-----------------------------1-----------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
LINE 1237
EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_SW_RST_REGWEN_7_OFFSET)
-----------------------------1-----------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
LINE 1238
EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_SW_RST_CTRL_N_0_OFFSET)
-----------------------------1-----------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
LINE 1239
EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_SW_RST_CTRL_N_1_OFFSET)
-----------------------------1-----------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
LINE 1240
EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_SW_RST_CTRL_N_2_OFFSET)
-----------------------------1-----------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
LINE 1241
EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_SW_RST_CTRL_N_3_OFFSET)
-----------------------------1-----------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
LINE 1242
EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_SW_RST_CTRL_N_4_OFFSET)
-----------------------------1-----------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
LINE 1243
EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_SW_RST_CTRL_N_5_OFFSET)
-----------------------------1-----------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
LINE 1244
EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_SW_RST_CTRL_N_6_OFFSET)
-----------------------------1-----------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
LINE 1245
EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_SW_RST_CTRL_N_7_OFFSET)
-----------------------------1-----------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
LINE 1246
EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_ERR_CODE_OFFSET)
--------------------------1-------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
LINE 1249
EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
---------1--------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 1249
SUB-EXPRESSION (reg_re || reg_we)
---1-- ---2--
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
LINE 1253
EXPRESSION
Number Term
1 reg_we &
2 ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1 & (~reg_be))))) | (addr_hit[13] & ((|(4'b1 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | (addr_hit[15] & ((|(4'b1 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1 & (~reg_be))))) | (addr_hit[17] & ((|(4'b1 & (~reg_be))))) | (addr_hit[18] & ((|(4'b1 & (~reg_be))))) | (addr_hit[19] & ((|(4'b1 & (~reg_be))))) | (addr_hit[20] & ((|(4'b1 & (~reg_be))))) | (addr_hit[21] & ((|(4'b1 & (~reg_be))))) | (addr_hit[22] & ((|(4'b1 & (~reg_be))))) | (addr_hit[23] & ((|(4'b1 & (~reg_be))))) | (addr_hit[24] & ((|(4'b1 & (~reg_be))))) | (addr_hit[25] & ((|(4'b1 & (~reg_be))))) | (addr_hit[26] & ((|(4'b1 & (~reg_be))))) | (addr_hit[27] & ((|(4'b1 & (~reg_be)))))))
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T46,T51,T52 |
LINE 1253
SUB-EXPRESSION
Number Term
1 (addr_hit[0] & ((|(4'b1 & (~reg_be))))) |
2 (addr_hit[1] & ((|(4'b1 & (~reg_be))))) |
3 (addr_hit[2] & ((|(4'b1 & (~reg_be))))) |
4 (addr_hit[3] & ((|(4'b1 & (~reg_be))))) |
5 (addr_hit[4] & ((|(4'b1 & (~reg_be))))) |
6 (addr_hit[5] & ((|(4'b1 & (~reg_be))))) |
7 (addr_hit[6] & ((|(4'b1111 & (~reg_be))))) |
8 (addr_hit[7] & ((|(4'b1 & (~reg_be))))) |
9 (addr_hit[8] & ((|(4'b1 & (~reg_be))))) |
10 (addr_hit[9] & ((|(4'b1 & (~reg_be))))) |
11 (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) |
12 (addr_hit[11] & ((|(4'b1 & (~reg_be))))) |
13 (addr_hit[12] & ((|(4'b1 & (~reg_be))))) |
14 (addr_hit[13] & ((|(4'b1 & (~reg_be))))) |
15 (addr_hit[14] & ((|(4'b1 & (~reg_be))))) |
16 (addr_hit[15] & ((|(4'b1 & (~reg_be))))) |
17 (addr_hit[16] & ((|(4'b1 & (~reg_be))))) |
18 (addr_hit[17] & ((|(4'b1 & (~reg_be))))) |
19 (addr_hit[18] & ((|(4'b1 & (~reg_be))))) |
20 (addr_hit[19] & ((|(4'b1 & (~reg_be))))) |
21 (addr_hit[20] & ((|(4'b1 & (~reg_be))))) |
22 (addr_hit[21] & ((|(4'b1 & (~reg_be))))) |
23 (addr_hit[22] & ((|(4'b1 & (~reg_be))))) |
24 (addr_hit[23] & ((|(4'b1 & (~reg_be))))) |
25 (addr_hit[24] & ((|(4'b1 & (~reg_be))))) |
26 (addr_hit[25] & ((|(4'b1 & (~reg_be))))) |
27 (addr_hit[26] & ((|(4'b1 & (~reg_be))))) |
28 (addr_hit[27] & ((|(4'b1 & (~reg_be))))))
Sensitive Expression == 1 | Status | Tests |
ALL ZEROS | Covered | T1,T2,T3 |
28 (addr_hit[27] & ((|(4'... | Covered | T1,T3,T4 |
27 (addr_hit[26] & ((|(4'... | Covered | T1,T3,T4 |
26 (addr_hit[25] & ((|(4'... | Covered | T1,T3,T4 |
25 (addr_hit[24] & ((|(4'... | Covered | T1,T3,T4 |
24 (addr_hit[23] & ((|(4'... | Covered | T1,T3,T4 |
23 (addr_hit[22] & ((|(4'... | Covered | T1,T3,T4 |
22 (addr_hit[21] & ((|(4'... | Covered | T1,T3,T4 |
21 (addr_hit[20] & ((|(4'... | Covered | T1,T3,T4 |
20 (addr_hit[19] & ((|(4'... | Covered | T1,T3,T4 |
19 (addr_hit[18] & ((|(4'... | Covered | T1,T3,T4 |
18 (addr_hit[17] & ((|(4'... | Covered | T1,T3,T4 |
17 (addr_hit[16] & ((|(4'... | Covered | T1,T3,T4 |
16 (addr_hit[15] & ((|(4'... | Covered | T1,T3,T4 |
15 (addr_hit[14] & ((|(4'... | Covered | T1,T2,T3 |
14 (addr_hit[13] & ((|(4'... | Covered | T1,T3,T4 |
13 (addr_hit[12] & ((|(4'... | Covered | T1,T3,T4 |
12 (addr_hit[11] & ((|(4'... | Covered | T1,T3,T4 |
11 (addr_hit[10] & ((|(4'... | Covered | T1,T3,T4 |
10 (addr_hit[9] & ((|(4'b... | Covered | T1,T3,T4 |
9 (addr_hit[8] & ((|(4'b... | Covered | T1,T3,T4 |
8 (addr_hit[7] & ((|(4'b... | Covered | T1,T3,T4 |
7 (addr_hit[6] & ((|(4'b... | Covered | T1,T3,T4 |
6 (addr_hit[5] & ((|(4'b... | Covered | T1,T2,T3 |
5 (addr_hit[4] & ((|(4'b... | Covered | T1,T3,T4 |
4 (addr_hit[3] & ((|(4'b... | Covered | T1,T3,T4 |
3 (addr_hit[2] & ((|(4'b... | Covered | T1,T3,T4 |
2 (addr_hit[1] & ((|(4'b... | Covered | T1,T3,T4 |
1 (addr_hit[0] & ((|(4'b... | Covered | T1,T3,T4 |
LINE 1253
SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 1253
SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 1253
SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T3,T4 |
LINE 1253
SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 1253
SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 1253
SUB-EXPRESSION (addr_hit[5] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T2,T3 |
LINE 1253
SUB-EXPRESSION (addr_hit[6] & ((|(4'b1111 & (~reg_be)))))
-----1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 1253
SUB-EXPRESSION (addr_hit[7] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 1253
SUB-EXPRESSION (addr_hit[8] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 1253
SUB-EXPRESSION (addr_hit[9] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 1253
SUB-EXPRESSION (addr_hit[10] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 1253
SUB-EXPRESSION (addr_hit[11] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 1253
SUB-EXPRESSION (addr_hit[12] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 1253
SUB-EXPRESSION (addr_hit[13] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 1253
SUB-EXPRESSION (addr_hit[14] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T2,T3 |
LINE 1253
SUB-EXPRESSION (addr_hit[15] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 1253
SUB-EXPRESSION (addr_hit[16] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 1253
SUB-EXPRESSION (addr_hit[17] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 1253
SUB-EXPRESSION (addr_hit[18] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 1253
SUB-EXPRESSION (addr_hit[19] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 1253
SUB-EXPRESSION (addr_hit[20] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 1253
SUB-EXPRESSION (addr_hit[21] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 1253
SUB-EXPRESSION (addr_hit[22] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 1253
SUB-EXPRESSION (addr_hit[23] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 1253
SUB-EXPRESSION (addr_hit[24] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 1253
SUB-EXPRESSION (addr_hit[25] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 1253
SUB-EXPRESSION (addr_hit[26] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 1253
SUB-EXPRESSION (addr_hit[27] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 1285
EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T4 |
1 | 0 | 1 | Covered | T1,T3,T4 |
1 | 1 | 0 | Covered | T51,T52,T55 |
1 | 1 | 1 | Covered | T60,T61,T36 |
LINE 1290
EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T4 |
1 | 0 | 1 | Covered | T1,T3,T4 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T3,T4 |
LINE 1293
EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T4 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T3,T4 |
LINE 1302
EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T4 |
1 | 0 | 1 | Covered | T1,T3,T4 |
1 | 1 | 0 | Covered | T51,T52,T55 |
1 | 1 | 1 | Covered | T45,T46,T47 |
LINE 1305
EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T4 |
1 | 0 | 1 | Covered | T1,T3,T4 |
1 | 1 | 0 | Covered | T46,T53,T54 |
1 | 1 | 1 | Covered | T1,T3,T4 |
LINE 1310
EXPRESSION (addr_hit[5] & reg_re & ((!reg_error)))
-----1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T4,T5,T6 |
LINE 1311
EXPRESSION (addr_hit[6] & reg_re & ((!reg_error)))
-----1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T3,T4 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T3,T4 |
LINE 1312
EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T4 |
1 | 0 | 1 | Covered | T1,T3,T4 |
1 | 1 | 0 | Covered | T51,T52,T55 |
1 | 1 | 1 | Covered | T45,T46,T47 |
LINE 1315
EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T4 |
1 | 0 | 1 | Covered | T1,T3,T4 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T3,T4 |
LINE 1320
EXPRESSION (addr_hit[9] & reg_re & ((!reg_error)))
-----1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T3,T4 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T4,T5,T6 |
LINE 1321
EXPRESSION (addr_hit[10] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T3,T4 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T3,T4 |
LINE 1322
EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T4 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T51,T52,T55 |
1 | 1 | 1 | Covered | T1,T3,T8 |
LINE 1325
EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T4 |
1 | 0 | 1 | Covered | T1,T3,T4 |
1 | 1 | 0 | Covered | T51,T52,T55 |
1 | 1 | 1 | Covered | T1,T3,T8 |
LINE 1328
EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T4 |
1 | 0 | 1 | Covered | T1,T3,T4 |
1 | 1 | 0 | Covered | T51,T52,T55 |
1 | 1 | 1 | Covered | T1,T3,T8 |
LINE 1331
EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T4 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T51,T52,T55 |
1 | 1 | 1 | Covered | T1,T3,T8 |
LINE 1334
EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T4 |
1 | 0 | 1 | Covered | T1,T3,T4 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T3,T8 |
LINE 1337
EXPRESSION (addr_hit[16] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T4 |
1 | 0 | 1 | Covered | T1,T3,T4 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T3,T8 |
LINE 1340
EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T4 |
1 | 0 | 1 | Covered | T1,T3,T4 |
1 | 1 | 0 | Covered | T51,T52,T55 |
1 | 1 | 1 | Covered | T1,T3,T8 |
LINE 1343
EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T4 |
1 | 0 | 1 | Covered | T1,T3,T4 |
1 | 1 | 0 | Covered | T46,T53,T54 |
1 | 1 | 1 | Covered | T1,T3,T8 |
LINE 1346
EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T4 |
1 | 0 | 1 | Covered | T1,T3,T4 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T3,T7 |
LINE 1349
EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T4 |
1 | 0 | 1 | Covered | T1,T3,T4 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T3,T7 |
LINE 1352
EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T4 |
1 | 0 | 1 | Covered | T1,T3,T4 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T3,T7 |
LINE 1355
EXPRESSION (addr_hit[22] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T4 |
1 | 0 | 1 | Covered | T1,T3,T4 |
1 | 1 | 0 | Covered | T51,T52,T55 |
1 | 1 | 1 | Covered | T1,T3,T7 |