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LINE 1358
EXPRESSION (addr_hit[23] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T4 |
1 | 0 | 1 | Covered | T1,T3,T4 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T3,T7 |
LINE 1361
EXPRESSION (addr_hit[24] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T4 |
1 | 0 | 1 | Covered | T1,T3,T4 |
1 | 1 | 0 | Covered | T51,T52,T55 |
1 | 1 | 1 | Covered | T1,T3,T7 |
LINE 1364
EXPRESSION (addr_hit[25] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T4 |
1 | 0 | 1 | Covered | T1,T3,T4 |
1 | 1 | 0 | Covered | T51,T52,T55 |
1 | 1 | 1 | Covered | T1,T3,T7 |
LINE 1367
EXPRESSION (addr_hit[26] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T4 |
1 | 0 | 1 | Covered | T1,T3,T4 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T3,T7 |