Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.57 99.40 98.27 99.05 99.83 99.33 95.57


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T503 /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.27575053133231337900838750421970033258359017314638339144808911284637742195356 Nov 22 12:39:38 PM PST 23 Nov 22 12:39:44 PM PST 23 243816210 ps
T504 /workspace/coverage/default/49.rstmgr_alert_test.61682229023679848626536594062703534377572496394817518349367650642028358575950 Nov 22 12:42:06 PM PST 23 Nov 22 12:42:13 PM PST 23 78981557 ps
T505 /workspace/coverage/default/34.rstmgr_stress_all.64029205169003076885789603727549180788529338884258108484989914593499494585282 Nov 22 12:41:14 PM PST 23 Nov 22 12:41:54 PM PST 23 11131278308 ps
T506 /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.47182594495070911754780634135194734299911196191159019885953181140058613932903 Nov 22 12:42:07 PM PST 23 Nov 22 12:42:14 PM PST 23 170065619 ps
T507 /workspace/coverage/default/37.rstmgr_reset.81585225383500026016338134762936641876093394972143467876054128897211864984747 Nov 22 12:41:03 PM PST 23 Nov 22 12:41:12 PM PST 23 1729953098 ps
T508 /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.22022653604328012692512081654521484528439629783759908401704776680780161234100 Nov 22 12:39:36 PM PST 23 Nov 22 12:39:41 PM PST 23 241232855 ps
T509 /workspace/coverage/default/35.rstmgr_reset.115566185768346729010906778139113895626947189623727984245524290684493469192050 Nov 22 12:41:08 PM PST 23 Nov 22 12:41:16 PM PST 23 1729953098 ps
T510 /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.98314564983482783214466507138943191233909528518897757281551484483437261754426 Nov 22 12:40:09 PM PST 23 Nov 22 12:40:19 PM PST 23 2162831562 ps
T511 /workspace/coverage/default/0.rstmgr_smoke.90941651806909405572970650649829079103748788330811015310021611942290150477274 Nov 22 12:39:23 PM PST 23 Nov 22 12:39:27 PM PST 23 223941050 ps
T62 /workspace/coverage/default/2.rstmgr_sec_cm.68157993645765134446927516432069459853118477905747970190762985785588220480982 Nov 22 12:39:58 PM PST 23 Nov 22 12:40:14 PM PST 23 8294713949 ps
T512 /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.42058714942664099160078079068600542226052413820021949667927214005186442991702 Nov 22 12:40:22 PM PST 23 Nov 22 12:40:26 PM PST 23 241232855 ps
T513 /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.41344577552995566843418676586120581574622307923532876810318982148597119843131 Nov 22 12:40:31 PM PST 23 Nov 22 12:40:34 PM PST 23 241232855 ps
T514 /workspace/coverage/default/23.rstmgr_alert_test.76153789270288455861547859205603363372045303798974637986675011888651110993022 Nov 22 12:40:49 PM PST 23 Nov 22 12:40:51 PM PST 23 78981557 ps
T515 /workspace/coverage/default/16.rstmgr_por_stretcher.108130777670127334131785527155776366972081540771077072414994675635136597490618 Nov 22 12:40:15 PM PST 23 Nov 22 12:40:17 PM PST 23 230357768 ps
T516 /workspace/coverage/default/13.rstmgr_reset.46040646885239147419414152686248024124930040555117793612661864419786979561533 Nov 22 12:40:06 PM PST 23 Nov 22 12:40:16 PM PST 23 1729953098 ps
T517 /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.57620764409680652043064962416364852627910363792028140135284844491839733091542 Nov 22 12:41:09 PM PST 23 Nov 22 12:41:12 PM PST 23 170065619 ps
T518 /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.43682170922563153288282198807304325994320635309343679125110758071825008905625 Nov 22 12:40:43 PM PST 23 Nov 22 12:40:45 PM PST 23 170065619 ps
T519 /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.65829763397375566229709285228948700345238035510755364451877759678550380238266 Nov 22 12:40:11 PM PST 23 Nov 22 12:40:14 PM PST 23 170065619 ps
T520 /workspace/coverage/default/10.rstmgr_smoke.60813826314906144414237858141782045039049570296821875547564800100903746716481 Nov 22 12:40:41 PM PST 23 Nov 22 12:40:44 PM PST 23 223941050 ps
T521 /workspace/coverage/default/24.rstmgr_smoke.88508324891147182488244549073049082173574998499587261636617184562302375490278 Nov 22 12:40:39 PM PST 23 Nov 22 12:40:42 PM PST 23 223941050 ps
T522 /workspace/coverage/default/13.rstmgr_sw_rst.24144050798516443162830552836497565354542352136295515325721755006677957213606 Nov 22 12:40:06 PM PST 23 Nov 22 12:40:11 PM PST 23 473109710 ps
T63 /workspace/coverage/default/4.rstmgr_sec_cm.12411825094990374471947075767300317026272652464836775013268530913064842887503 Nov 22 12:39:40 PM PST 23 Nov 22 12:39:58 PM PST 23 8294713949 ps
T523 /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.16432342876176309708828716937036788491934143701024247456244718885988781499714 Nov 22 12:39:53 PM PST 23 Nov 22 12:39:55 PM PST 23 241232855 ps
T524 /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.32547178142540135819126038861464585119813733541580044643937794344248706091511 Nov 22 12:41:47 PM PST 23 Nov 22 12:41:52 PM PST 23 243816210 ps
T525 /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.78204861811671390068269931898188821280683171511659184643264507562169081178868 Nov 22 12:41:42 PM PST 23 Nov 22 12:41:52 PM PST 23 2162831562 ps
T526 /workspace/coverage/default/3.rstmgr_smoke.57263755112865198461444245817154156533310511476407761154771879721290030725265 Nov 22 12:39:43 PM PST 23 Nov 22 12:39:47 PM PST 23 223941050 ps
T527 /workspace/coverage/default/7.rstmgr_stress_all.99084506658117552244553929220868808552213878521005345228483103016328260473295 Nov 22 12:40:03 PM PST 23 Nov 22 12:40:45 PM PST 23 11131278308 ps
T528 /workspace/coverage/default/9.rstmgr_por_stretcher.74394098680447078809345736442011737814848894156015293508870305494081558782520 Nov 22 12:39:53 PM PST 23 Nov 22 12:39:54 PM PST 23 230357768 ps
T529 /workspace/coverage/default/41.rstmgr_reset.99106848420661496686285646867260364211706385609398502388153883861275024003262 Nov 22 12:41:28 PM PST 23 Nov 22 12:41:36 PM PST 23 1729953098 ps
T530 /workspace/coverage/default/6.rstmgr_stress_all.58287815535377212049891051994768242627113279931000728747706084461001704992185 Nov 22 12:40:00 PM PST 23 Nov 22 12:40:40 PM PST 23 11131278308 ps
T531 /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.61125200757808880340604631992022512773028215945812804009477562464229191102202 Nov 22 12:40:15 PM PST 23 Nov 22 12:40:18 PM PST 23 243816210 ps
T532 /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.35544980167715664089834732258200369355579044929014157080737563774895480737350 Nov 22 12:41:14 PM PST 23 Nov 22 12:41:24 PM PST 23 2162831562 ps
T533 /workspace/coverage/default/4.rstmgr_por_stretcher.73498733703034248034849305216927009276606760590403792461907096388858880149681 Nov 22 12:39:44 PM PST 23 Nov 22 12:39:47 PM PST 23 230357768 ps
T534 /workspace/coverage/default/31.rstmgr_por_stretcher.93028094806862193351904342016062492148137348347581659598985445186626510615118 Nov 22 12:40:37 PM PST 23 Nov 22 12:40:40 PM PST 23 230357768 ps
T535 /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.93489563721404463044118984044492107077897868139837561157764739365248068709808 Nov 22 12:40:05 PM PST 23 Nov 22 12:40:09 PM PST 23 170065619 ps
T536 /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.80448661126419129082833106217393233177385767371767164583284477839636058537369 Nov 22 12:40:43 PM PST 23 Nov 22 12:40:53 PM PST 23 2162831562 ps
T537 /workspace/coverage/default/16.rstmgr_stress_all.91268992362233926256204857024424744740579858493723880201181686882774156776789 Nov 22 12:40:06 PM PST 23 Nov 22 12:40:49 PM PST 23 11131278308 ps
T538 /workspace/coverage/default/11.rstmgr_alert_test.19101435050568885771622972100030598284257349960575222773323721528358357980663 Nov 22 12:40:05 PM PST 23 Nov 22 12:40:08 PM PST 23 78981557 ps
T539 /workspace/coverage/default/24.rstmgr_sw_rst.42980112695914774232829228137779424200957251202026648905856940335355622336148 Nov 22 12:40:51 PM PST 23 Nov 22 12:40:54 PM PST 23 473109710 ps
T540 /workspace/coverage/default/0.rstmgr_sw_rst.83369204394184583595191141186340330212417656043654701656873293599644219537571 Nov 22 12:39:34 PM PST 23 Nov 22 12:39:40 PM PST 23 473109710 ps
T541 /workspace/coverage/default/41.rstmgr_stress_all.50236273700682146086391177763758576732717009229829991973057301364034906046292 Nov 22 12:41:10 PM PST 23 Nov 22 12:41:51 PM PST 23 11131278308 ps
T542 /workspace/coverage/default/17.rstmgr_reset.9295403534397880539798098289920298075436097690313558333437919965669932009873 Nov 22 12:40:07 PM PST 23 Nov 22 12:40:16 PM PST 23 1729953098 ps
T543 /workspace/coverage/default/16.rstmgr_sw_rst.53943345125086549152862161346761470497146829410163771729735387666549907875227 Nov 22 12:40:18 PM PST 23 Nov 22 12:40:22 PM PST 23 473109710 ps
T544 /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.77858708381321416972283375114987533796995684799836722998628528471881865349349 Nov 22 12:41:36 PM PST 23 Nov 22 12:41:46 PM PST 23 2162831562 ps
T545 /workspace/coverage/default/38.rstmgr_sw_rst.113429312203445459453718162905299614053136293539244803550492599116383279325632 Nov 22 12:41:06 PM PST 23 Nov 22 12:41:10 PM PST 23 473109710 ps
T546 /workspace/coverage/default/28.rstmgr_stress_all.38756278448905562450367240673509090974860901641321450117994824385029459753485 Nov 22 12:40:53 PM PST 23 Nov 22 12:41:34 PM PST 23 11131278308 ps
T547 /workspace/coverage/default/47.rstmgr_smoke.98032793522134060007511783262641100298575062255434310277662692128305346106974 Nov 22 12:41:59 PM PST 23 Nov 22 12:42:11 PM PST 23 223941050 ps
T548 /workspace/coverage/default/3.rstmgr_stress_all.105597397806396629058390182376982963068453133345301934282458048951394142324922 Nov 22 12:39:33 PM PST 23 Nov 22 12:40:17 PM PST 23 11131278308 ps
T549 /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.103321603082983923021556414576029909975207085032434895168069873373030253209150 Nov 22 12:40:06 PM PST 23 Nov 22 12:40:10 PM PST 23 243816210 ps
T550 /workspace/coverage/default/29.rstmgr_smoke.12267617132273165949302224171782423063521728657447740787832301878218397194103 Nov 22 12:41:09 PM PST 23 Nov 22 12:41:16 PM PST 23 223941050 ps
T551 /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.70791257037134277209112385733716578783336065001665272725719696034306321092409 Nov 22 12:41:03 PM PST 23 Nov 22 12:41:05 PM PST 23 241232855 ps
T552 /workspace/coverage/default/25.rstmgr_alert_test.24632284193041776404582550686348325965668019238094230989247340754471484387837 Nov 22 12:40:46 PM PST 23 Nov 22 12:40:48 PM PST 23 78981557 ps
T553 /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.79835906901554650230968343329998424031572173240464610487330451952430824682067 Nov 22 12:39:27 PM PST 23 Nov 22 12:39:30 PM PST 23 241232855 ps
T554 /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.76853844727492542845229893170437756807891853182062722650360355201658870279979 Nov 22 12:40:15 PM PST 23 Nov 22 12:40:19 PM PST 23 170065619 ps
T555 /workspace/coverage/default/35.rstmgr_por_stretcher.3361097152515408945350232662951854623293328111337560804794397579445817389060 Nov 22 12:41:31 PM PST 23 Nov 22 12:41:33 PM PST 23 230357768 ps
T556 /workspace/coverage/default/18.rstmgr_por_stretcher.85488621950268854010260387232746004382032762150659204425669254079729730220804 Nov 22 12:40:05 PM PST 23 Nov 22 12:40:08 PM PST 23 230357768 ps
T557 /workspace/coverage/default/9.rstmgr_alert_test.39039312889241545520829121809536524901322953557289681480563853438125075435306 Nov 22 12:40:07 PM PST 23 Nov 22 12:40:10 PM PST 23 78981557 ps
T558 /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.33125378726083691758632772768005312828048092051705831388211047440437028876898 Nov 22 12:40:38 PM PST 23 Nov 22 12:40:49 PM PST 23 2162831562 ps
T559 /workspace/coverage/default/4.rstmgr_alert_test.98522112875405673412629983945752399651029843009824710272431849168505590937591 Nov 22 12:39:36 PM PST 23 Nov 22 12:39:41 PM PST 23 78981557 ps
T560 /workspace/coverage/default/2.rstmgr_sw_rst.56497344716928677538874358147153312928851155377002274659118821468590789884881 Nov 22 12:39:31 PM PST 23 Nov 22 12:39:37 PM PST 23 473109710 ps
T561 /workspace/coverage/default/46.rstmgr_sw_rst.14356922605017817347360147334476947762312500251461607661266441700943929802300 Nov 22 12:41:58 PM PST 23 Nov 22 12:42:07 PM PST 23 473109710 ps
T562 /workspace/coverage/default/41.rstmgr_por_stretcher.60940740116139759373627417494929911952257360379654077518167109058007235532520 Nov 22 12:41:20 PM PST 23 Nov 22 12:41:21 PM PST 23 230357768 ps
T563 /workspace/coverage/default/0.rstmgr_alert_test.107237281295299171181003946587900828762494070464913013199431320848528967035169 Nov 22 12:39:25 PM PST 23 Nov 22 12:39:28 PM PST 23 78981557 ps
T564 /workspace/coverage/default/29.rstmgr_por_stretcher.93930437522466370739879372328494838825456471128512663895995289076539358002778 Nov 22 12:41:11 PM PST 23 Nov 22 12:41:13 PM PST 23 230357768 ps
T565 /workspace/coverage/default/18.rstmgr_smoke.9190125217223380498315275627721168902208075657664237963357859883522883600100 Nov 22 12:40:22 PM PST 23 Nov 22 12:40:25 PM PST 23 223941050 ps
T566 /workspace/coverage/default/31.rstmgr_stress_all.74749959902139645543213234721168110184837092674901073440949513436438182611417 Nov 22 12:40:55 PM PST 23 Nov 22 12:41:34 PM PST 23 11131278308 ps
T567 /workspace/coverage/default/14.rstmgr_stress_all.21485454469556190411145753477573282242923191629973949273508810500766763143327 Nov 22 12:40:09 PM PST 23 Nov 22 12:40:49 PM PST 23 11131278308 ps
T568 /workspace/coverage/default/29.rstmgr_reset.42484490604394466793359501041621771477328757426666004241567625633946758063347 Nov 22 12:41:17 PM PST 23 Nov 22 12:41:24 PM PST 23 1729953098 ps
T569 /workspace/coverage/default/37.rstmgr_smoke.11436188033135043862256466187432990136491951981809284448130054359710292722760 Nov 22 12:41:22 PM PST 23 Nov 22 12:41:24 PM PST 23 223941050 ps
T570 /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.104775233670514506617968805908774411965668579908050480569877197909036580711009 Nov 22 12:41:14 PM PST 23 Nov 22 12:41:17 PM PST 23 241232855 ps
T571 /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.64080040230818744302770054480464484188983148811833931029202555123448739927275 Nov 22 12:41:41 PM PST 23 Nov 22 12:41:43 PM PST 23 243816210 ps
T572 /workspace/coverage/default/5.rstmgr_reset.20352044829222842297927601307032827532473960246502653371923493024048065413122 Nov 22 12:39:54 PM PST 23 Nov 22 12:40:02 PM PST 23 1729953098 ps
T573 /workspace/coverage/default/21.rstmgr_sw_rst.67341165323931286562427853448923145480723910891885888978990488020399754229280 Nov 22 12:40:29 PM PST 23 Nov 22 12:40:33 PM PST 23 473109710 ps
T574 /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.89600470120822439976580189247106757216436447299935536119446279058576327361468 Nov 22 12:39:40 PM PST 23 Nov 22 12:39:46 PM PST 23 241232855 ps
T575 /workspace/coverage/default/4.rstmgr_smoke.39446063492271589839073590256565614394836406950766364864611531587148906773137 Nov 22 12:39:36 PM PST 23 Nov 22 12:39:41 PM PST 23 223941050 ps
T576 /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.40673269139345025480123067600672417775671976490368292238100552904274568365495 Nov 22 12:40:43 PM PST 23 Nov 22 12:40:53 PM PST 23 2162831562 ps
T577 /workspace/coverage/default/38.rstmgr_smoke.38983233257463034730108221926414546814987800651201273619925046364707948520166 Nov 22 12:41:14 PM PST 23 Nov 22 12:41:17 PM PST 23 223941050 ps
T578 /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.28636417076213867442644696351185586256225972215767582387562276581495362989495 Nov 22 12:41:13 PM PST 23 Nov 22 12:41:22 PM PST 23 2162831562 ps
T579 /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.52731214313555141495293882151035986216972028252479067935169485791181090072505 Nov 22 12:40:07 PM PST 23 Nov 22 12:40:17 PM PST 23 2162831562 ps
T580 /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.3443454773113657677139009784574877313358940281004905224962027757740522706385 Nov 22 12:41:17 PM PST 23 Nov 22 12:41:19 PM PST 23 243816210 ps
T581 /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.58204113394909755842252215881471945415004739925381406081088969988620660201671 Nov 22 12:39:35 PM PST 23 Nov 22 12:39:40 PM PST 23 243816210 ps
T582 /workspace/coverage/default/12.rstmgr_sw_rst.41201856752212566392299153953253145454904268864733182575468594891361792379077 Nov 22 12:40:06 PM PST 23 Nov 22 12:40:12 PM PST 23 473109710 ps
T583 /workspace/coverage/default/12.rstmgr_stress_all.31526210335838355075638857741828872311265943318752737158455285911314975388324 Nov 22 12:40:07 PM PST 23 Nov 22 12:40:49 PM PST 23 11131278308 ps
T584 /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.94947362824171027526960580441766321447752179966855286873636699469505725887348 Nov 22 12:41:09 PM PST 23 Nov 22 12:41:12 PM PST 23 241232855 ps
T585 /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.85204422088905103703814564416082123003600093443996262404835970662641775523836 Nov 22 12:42:12 PM PST 23 Nov 22 12:42:25 PM PST 23 2162831562 ps
T586 /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.22893294617962543449204168826573843547465769051648566884905648230052987641121 Nov 22 12:40:42 PM PST 23 Nov 22 12:40:45 PM PST 23 243816210 ps
T587 /workspace/coverage/default/3.rstmgr_alert_test.40276516119863313896735929363203405785165504823798623279674406228772629999460 Nov 22 12:39:36 PM PST 23 Nov 22 12:39:40 PM PST 23 78981557 ps
T588 /workspace/coverage/default/12.rstmgr_smoke.23955898362661194185604849446079144236215606821509352460267963038318398959106 Nov 22 12:40:13 PM PST 23 Nov 22 12:40:16 PM PST 23 223941050 ps
T589 /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.110269809527700105144823077734100241871141995449281048611493167129936045033053 Nov 22 12:40:21 PM PST 23 Nov 22 12:40:25 PM PST 23 241232855 ps
T590 /workspace/coverage/default/48.rstmgr_por_stretcher.92814443710600754444367524208783058217038463336811496386811925852287783285662 Nov 22 12:42:12 PM PST 23 Nov 22 12:42:19 PM PST 23 230357768 ps
T591 /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.71126830077120204621052607278730121214565960338076123369142241774460941463160 Nov 22 12:40:38 PM PST 23 Nov 22 12:40:49 PM PST 23 2162831562 ps
T592 /workspace/coverage/default/17.rstmgr_stress_all.3865399569141911164112896793577573823889063445747915176832242890562807838853 Nov 22 12:40:22 PM PST 23 Nov 22 12:41:04 PM PST 23 11131278308 ps
T593 /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.70247274991425995957203285747459646318660898916760020342997658130990440369809 Nov 22 12:41:15 PM PST 23 Nov 22 12:41:17 PM PST 23 243816210 ps
T594 /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.82953538374604109015845870299699381030431902596773818414727789108083318146065 Nov 22 12:40:05 PM PST 23 Nov 22 12:40:08 PM PST 23 170065619 ps
T595 /workspace/coverage/default/44.rstmgr_alert_test.44257029915041764337697847535613571558444106752903877907320305509494611809959 Nov 22 12:41:58 PM PST 23 Nov 22 12:42:05 PM PST 23 78981557 ps
T596 /workspace/coverage/default/40.rstmgr_por_stretcher.21871394027259947809370540990525136859436971320838413390207983814819811297556 Nov 22 12:41:07 PM PST 23 Nov 22 12:41:09 PM PST 23 230357768 ps
T597 /workspace/coverage/default/49.rstmgr_smoke.98254953779903394880439730532838859205386561521235298057995143220705197121566 Nov 22 12:42:02 PM PST 23 Nov 22 12:42:13 PM PST 23 223941050 ps
T598 /workspace/coverage/default/22.rstmgr_smoke.93766013507659212265344107336678542200053017572406939199897302771012937456340 Nov 22 12:40:29 PM PST 23 Nov 22 12:40:32 PM PST 23 223941050 ps
T599 /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.44807872812888039099265354018670529671192614341877545403285985406616635633677 Nov 22 12:40:39 PM PST 23 Nov 22 12:40:49 PM PST 23 2162831562 ps
T600 /workspace/coverage/default/5.rstmgr_sw_rst.4528992659971202670899493642542613776273517060849942244058307775395038299262 Nov 22 12:39:54 PM PST 23 Nov 22 12:39:58 PM PST 23 473109710 ps
T601 /workspace/coverage/default/47.rstmgr_por_stretcher.13016728060929597281638858757031526422857963551796090717009728885996371009563 Nov 22 12:41:49 PM PST 23 Nov 22 12:41:59 PM PST 23 230357768 ps
T602 /workspace/coverage/default/5.rstmgr_por_stretcher.58702234216160003631666145047020050394356764006444465512957512276867837490796 Nov 22 12:39:38 PM PST 23 Nov 22 12:39:43 PM PST 23 230357768 ps
T603 /workspace/coverage/default/43.rstmgr_reset.105321249251564621057910413919952826478447204823274804346211035063200052415463 Nov 22 12:42:08 PM PST 23 Nov 22 12:42:19 PM PST 23 1729953098 ps
T604 /workspace/coverage/default/4.rstmgr_sw_rst.82348162674081874634692443256362963915405456126439286016646977256110873030722 Nov 22 12:39:37 PM PST 23 Nov 22 12:39:44 PM PST 23 473109710 ps
T605 /workspace/coverage/default/4.rstmgr_reset.30665788156133653169920103679217618231757495220113602627709913860353720988429 Nov 22 12:39:36 PM PST 23 Nov 22 12:39:46 PM PST 23 1729953098 ps
T606 /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.58304859596662160995959180617619887929746395003804570078059918834681612027586 Nov 22 12:39:30 PM PST 23 Nov 22 12:39:34 PM PST 23 243816210 ps
T607 /workspace/coverage/default/18.rstmgr_reset.79823069227029870119275889474560359736498292653004160130625724882547931589704 Nov 22 12:40:22 PM PST 23 Nov 22 12:40:31 PM PST 23 1729953098 ps
T608 /workspace/coverage/default/20.rstmgr_smoke.64031547861518328409236654909590609612582745277130638731987408327158993736645 Nov 22 12:40:32 PM PST 23 Nov 22 12:40:34 PM PST 23 223941050 ps
T609 /workspace/coverage/default/39.rstmgr_stress_all.21490792974157623502046891165481611859742959650261434885509902756516631045586 Nov 22 12:41:04 PM PST 23 Nov 22 12:41:45 PM PST 23 11131278308 ps
T610 /workspace/coverage/default/18.rstmgr_stress_all.3651690750252814995984178255145733484024139129452214188437595057556335429735 Nov 22 12:40:23 PM PST 23 Nov 22 12:41:05 PM PST 23 11131278308 ps
T611 /workspace/coverage/default/9.rstmgr_reset.88707115984653799964080671028662087978559573948091907514186137840867924770906 Nov 22 12:40:00 PM PST 23 Nov 22 12:40:09 PM PST 23 1729953098 ps
T612 /workspace/coverage/default/6.rstmgr_reset.3116414666500700235215717212134773607544632999620334354596894032540905369992 Nov 22 12:39:55 PM PST 23 Nov 22 12:40:03 PM PST 23 1729953098 ps
T613 /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.19541576297525694870722996054055369454175223254268754020765811945724029080855 Nov 22 12:40:42 PM PST 23 Nov 22 12:40:44 PM PST 23 243816210 ps
T614 /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.91819857790627606935552638001613554728698088881092115477236800081397887976360 Nov 22 12:40:04 PM PST 23 Nov 22 12:40:08 PM PST 23 170065619 ps
T615 /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.48541516647498076503761331668069256807322188390672899585076147227366435226171 Nov 22 12:40:05 PM PST 23 Nov 22 12:40:09 PM PST 23 241232855 ps
T616 /workspace/coverage/default/26.rstmgr_stress_all.75562010163707014853674991629617670130148084891573175499770448919081921940396 Nov 22 12:41:03 PM PST 23 Nov 22 12:41:43 PM PST 23 11131278308 ps
T617 /workspace/coverage/default/39.rstmgr_smoke.3232597133375164589275888338973162795093384746087120985957248932920205053256 Nov 22 12:41:10 PM PST 23 Nov 22 12:41:13 PM PST 23 223941050 ps
T618 /workspace/coverage/default/19.rstmgr_stress_all.53017033232119944393061446659978057514658208898358721747040046541956187669345 Nov 22 12:40:23 PM PST 23 Nov 22 12:41:05 PM PST 23 11131278308 ps
T619 /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.9670307702790156569351373347533721988787821230606250576291440526083303370147 Nov 22 12:41:14 PM PST 23 Nov 22 12:41:16 PM PST 23 243816210 ps
T620 /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.61022032970522489698818427680282495083459812918003605003277394418919085700476 Nov 22 12:40:07 PM PST 23 Nov 22 12:40:11 PM PST 23 241232855 ps

Test location /workspace/coverage/default/0.rstmgr_stress_all.39053291225283990641039319736017630807416647302552412765829402117207284443964
Short name T7
Test name
Test status
Simulation time 11131278308 ps
CPU time 39.85 seconds
Started Nov 22 12:39:34 PM PST 23
Finished Nov 22 12:40:16 PM PST 23
Peak memory 199960 kb
Host smart-c50b5ace-ebae-4aea-a227-737531a13415
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39053291225283990641039319736017630807416647302552412765829402117207284443964 -assert nopos
tproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.39053291225283990641039319736017630807416647302552412765829402117207284443964
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.44047145543631622685975066263239599359203432496207428422868003766745985667447
Short name T10
Test name
Test status
Simulation time 473109710 ps
CPU time 2.67 seconds
Started Nov 22 12:41:04 PM PST 23
Finished Nov 22 12:41:10 PM PST 23
Peak memory 199856 kb
Host smart-57d3d781-888c-443d-a495-8939f28ece58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44047145543631622685975066263239599359203432496207428422868003766745985667447 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 29.rstmgr_sw_rst.44047145543631622685975066263239599359203432496207428422868003766745985667447
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.105022316460395405096095916316210252128565294510962548470804546292808345418088
Short name T46
Test name
Test status
Simulation time 486526484 ps
CPU time 1.98 seconds
Started Nov 22 12:29:19 PM PST 23
Finished Nov 22 12:29:23 PM PST 23
Peak memory 199784 kb
Host smart-be2feb94-0537-4ffc-8f8d-91e5f2b75d66
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105022316460395405096095916316210252128565294510962548470804546292808345418088 -assert
nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err.105022316460395405096095916316210252128565294510962548470804546292808345418088
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.15337875237998195257391567996438993373290773613638227813416450099082906319327
Short name T57
Test name
Test status
Simulation time 8294713949 ps
CPU time 13.82 seconds
Started Nov 22 12:39:41 PM PST 23
Finished Nov 22 12:39:58 PM PST 23
Peak memory 216588 kb
Host smart-eb257e33-982c-4077-8d06-4c7f665ba031
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15337875237998195257391567996438993373290773613638227813416450099082906319327 -assert nopostpro
c +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.15337875237998195257391567996438993373290773613638227813416450099082906319327
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.57361880850199236156814934359717518334550439137946091122498477969837803073881
Short name T27
Test name
Test status
Simulation time 2162831562 ps
CPU time 7.67 seconds
Started Nov 22 12:40:06 PM PST 23
Finished Nov 22 12:40:21 PM PST 23
Peak memory 216988 kb
Host smart-6d182016-b0be-4153-8a4c-772230b41814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57361880850199236156814934359717518334550439137946091122498477969837803073881 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 12.rstmgr_leaf_rst_cnsty.57361880850199236156814934359717518334550439137946091122498477969837803073881
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.33562989120708715284591867270306588519575436922017091126285620164860000321114
Short name T55
Test name
Test status
Simulation time 333191924 ps
CPU time 2.19 seconds
Started Nov 22 12:29:13 PM PST 23
Finished Nov 22 12:29:17 PM PST 23
Peak memory 208024 kb
Host smart-e51b9c8f-a54f-4c9c-b85a-6a10603f452e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33562989120708715284591867270306588519575436922017091126285620164860000321114 -assert nopostproc +U
VM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.33562989120708715284591867270306588519575436922017091126285620164860000321114
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.103266475951017832000113444243591600927145211940422401403848511003651092540614
Short name T109
Test name
Test status
Simulation time 78981557 ps
CPU time 0.76 seconds
Started Nov 22 12:40:14 PM PST 23
Finished Nov 22 12:40:17 PM PST 23
Peak memory 199540 kb
Host smart-53d585b7-0a60-4ff9-a4b9-f3e899872fe1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103266475951017832000113444243591600927145211940422401403848511003651092540614 -assert nopostp
roc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.103266475951017832000113444243591600927145211940422401403848511003651092540614
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.41127904267378301030044739644503178861869960014665614431892120036405456382414
Short name T97
Test name
Test status
Simulation time 170065619 ps
CPU time 1.19 seconds
Started Nov 22 12:39:31 PM PST 23
Finished Nov 22 12:39:35 PM PST 23
Peak memory 199772 kb
Host smart-64f6d553-f509-465d-98a8-e46e43db0ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41127904267378301030044739644503178861869960014665614431892120036405456382414 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.41127904267378301030044739644503178861869960014665614431892120036405456382414
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.57205108994035620391726256983414943798199166492424371831636154413821830734285
Short name T116
Test name
Test status
Simulation time 241232855 ps
CPU time 1.41 seconds
Started Nov 22 12:40:10 PM PST 23
Finished Nov 22 12:40:13 PM PST 23
Peak memory 199744 kb
Host smart-077651bf-445a-464a-98b1-b6bb1cb3622d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57205108994035620391726256983414943798199166492424371831636154413821830734285 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 15.rstmgr_sw_rst_reset_race.57205108994035620391726256983414943798199166492424371831636154413821830734285
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.102909739248884521385499912032955596252446355941898560355500650190366348177059
Short name T84
Test name
Test status
Simulation time 148107110 ps
CPU time 1.13 seconds
Started Nov 22 12:29:09 PM PST 23
Finished Nov 22 12:29:12 PM PST 23
Peak memory 199820 kb
Host smart-5b282ecd-5e84-4feb-a76d-c5c3f55a8952
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102909739248884521385499912032955596252446355941898560355500650190366348177059
-assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_same_csr_outstanding.10290973924888452138549991203295559625244635594189856035550
0650190366348177059
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.32827302720241634933085411424449708759922028218562369118536397764646707532885
Short name T19
Test name
Test status
Simulation time 230357768 ps
CPU time 0.91 seconds
Started Nov 22 12:40:01 PM PST 23
Finished Nov 22 12:40:04 PM PST 23
Peak memory 199704 kb
Host smart-b9904e94-fc4d-4b74-9d7a-ec46d96286d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32827302720241634933085411424449708759922028218562369118536397764646707532885 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.rstmgr_por_stretcher.32827302720241634933085411424449708759922028218562369118536397764646707532885
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.36325100028597644202131765263695955436156788684643080473901787680699021524003
Short name T199
Test name
Test status
Simulation time 222441038 ps
CPU time 1.5 seconds
Started Nov 22 12:29:23 PM PST 23
Finished Nov 22 12:29:26 PM PST 23
Peak memory 199732 kb
Host smart-070991af-1219-4a09-bc10-6394785b25e1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36325100028597644202131765263695955436156788684643080473901787680699021524003 -assert nopo
stproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.36325100028597644202131765263695955436156788684643080473901787680699021524003
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.114054551745470818154555031627787759684555359026540408741463380266718648752940
Short name T187
Test name
Test status
Simulation time 1017822401 ps
CPU time 4.85 seconds
Started Nov 22 12:29:18 PM PST 23
Finished Nov 22 12:29:25 PM PST 23
Peak memory 199700 kb
Host smart-dddd2c29-5262-468a-84fb-59d07e0ede75
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114054551745470818154555031627787759684555359026540408741463380266718648752940 -assert nop
ostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.114054551745470818154555031627787759684555359026540408741463380266718648752940
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.8284264470508003724127946032303139338276238598046960157384906986283354612277
Short name T185
Test name
Test status
Simulation time 108023456 ps
CPU time 0.82 seconds
Started Nov 22 12:29:10 PM PST 23
Finished Nov 22 12:29:13 PM PST 23
Peak memory 199620 kb
Host smart-6a47faaf-00bd-4bed-be6f-8cf839bf4b57
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8284264470508003724127946032303139338276238598046960157384906986283354612277 -assert nopos
tproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.8284264470508003724127946032303139338276238598046960157384906986283354612277
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.22211329352308345552637534391755627704058452357695309054525485342850192851990
Short name T222
Test name
Test status
Simulation time 108315125 ps
CPU time 0.95 seconds
Started Nov 22 12:29:25 PM PST 23
Finished Nov 22 12:29:29 PM PST 23
Peak memory 199644 kb
Host smart-b9a66037-89dc-446d-9b87-237adcc223b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221132935230834555263753439175562770405845
2357695309054525485342850192851990 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.2221132935230834555
2637534391755627704058452357695309054525485342850192851990
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.42991616629869278351951603541391142461348628601955425295152320651751059782058
Short name T152
Test name
Test status
Simulation time 61856420 ps
CPU time 0.73 seconds
Started Nov 22 12:29:12 PM PST 23
Finished Nov 22 12:29:14 PM PST 23
Peak memory 199644 kb
Host smart-37794246-4b7b-4495-a618-c499f09b748d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42991616629869278351951603541391142461348628601955425295152320651751059782058 -assert nopostproc
+UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.42991616629869278351951603541391142461348628601955425295152320651751059782058
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.26203738961887593118989952458742837148628044454007648607406568221251654808432
Short name T202
Test name
Test status
Simulation time 148107110 ps
CPU time 1.12 seconds
Started Nov 22 12:29:07 PM PST 23
Finished Nov 22 12:29:09 PM PST 23
Peak memory 199660 kb
Host smart-8a4b4be9-64cf-4c65-bc91-9b2bb92eb6c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26203738961887593118989952458742837148628044454007648607406568221251654808432
-assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_same_csr_outstanding.262037389618875931189899524587428371486280444540076486074065
68221251654808432
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.62895464808855049818922010037191812186453420252580014000536965556457067171982
Short name T209
Test name
Test status
Simulation time 486526484 ps
CPU time 1.94 seconds
Started Nov 22 12:29:16 PM PST 23
Finished Nov 22 12:29:19 PM PST 23
Peak memory 199792 kb
Host smart-127d0f12-ddea-41f7-9704-f9acd17c5be7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62895464808855049818922010037191812186453420252580014000536965556457067171982 -assert n
opostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err.62895464808855049818922010037191812186453420252580014000536965556457067171982
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.90367999883196541584710123239450252720474822177630485303071190897091697883679
Short name T216
Test name
Test status
Simulation time 222441038 ps
CPU time 1.57 seconds
Started Nov 22 12:29:12 PM PST 23
Finished Nov 22 12:29:15 PM PST 23
Peak memory 199732 kb
Host smart-a0b3cc81-9316-4081-933a-efedd3766c3c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90367999883196541584710123239450252720474822177630485303071190897091697883679 -assert nopo
stproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.90367999883196541584710123239450252720474822177630485303071190897091697883679
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.34326816687280015353984953541692651244088572826510389493419413134460378735171
Short name T148
Test name
Test status
Simulation time 1017822401 ps
CPU time 4.98 seconds
Started Nov 22 12:29:24 PM PST 23
Finished Nov 22 12:29:31 PM PST 23
Peak memory 199388 kb
Host smart-138a0e42-243c-4135-8ea3-2c65ef27c00e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34326816687280015353984953541692651244088572826510389493419413134460378735171 -assert nopo
stproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.34326816687280015353984953541692651244088572826510389493419413134460378735171
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.98053527335960231732715387921651168228493298459219952271833559285676989149035
Short name T211
Test name
Test status
Simulation time 108023456 ps
CPU time 0.83 seconds
Started Nov 22 12:29:24 PM PST 23
Finished Nov 22 12:29:27 PM PST 23
Peak memory 199588 kb
Host smart-aad0a422-e60a-4961-9545-e013dbc29667
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98053527335960231732715387921651168228493298459219952271833559285676989149035 -assert nopo
stproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.98053527335960231732715387921651168228493298459219952271833559285676989149035
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.99662570204809379920493473807094812044726598940636932118605517645155247129009
Short name T198
Test name
Test status
Simulation time 108315125 ps
CPU time 0.92 seconds
Started Nov 22 12:29:12 PM PST 23
Finished Nov 22 12:29:14 PM PST 23
Peak memory 199684 kb
Host smart-b8d752ee-7bd4-4126-9f55-b0765ce6c8a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9966257020480937992049347380709481204472659
8940636932118605517645155247129009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.9966257020480937992
0493473807094812044726598940636932118605517645155247129009
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.58623108182483671913703797103691842009378018966636393342024284640327068663449
Short name T212
Test name
Test status
Simulation time 61856420 ps
CPU time 0.72 seconds
Started Nov 22 12:29:22 PM PST 23
Finished Nov 22 12:29:25 PM PST 23
Peak memory 199644 kb
Host smart-c6506ff2-5a4f-45b8-9717-9a6d992fa69b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58623108182483671913703797103691842009378018966636393342024284640327068663449 -assert nopostproc
+UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.58623108182483671913703797103691842009378018966636393342024284640327068663449
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.51711206651067674660850144556999782465212568356070888570974401770021964537599
Short name T165
Test name
Test status
Simulation time 333191924 ps
CPU time 2.3 seconds
Started Nov 22 12:29:10 PM PST 23
Finished Nov 22 12:29:14 PM PST 23
Peak memory 207988 kb
Host smart-1a7600d5-e2bb-4cc0-86d4-6e3012afd2ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51711206651067674660850144556999782465212568356070888570974401770021964537599 -assert nopostproc +U
VM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.51711206651067674660850144556999782465212568356070888570974401770021964537599
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.85067145103258808865397190622255359048983196544530576209643267535082890844090
Short name T158
Test name
Test status
Simulation time 486526484 ps
CPU time 1.92 seconds
Started Nov 22 12:29:24 PM PST 23
Finished Nov 22 12:29:28 PM PST 23
Peak memory 199764 kb
Host smart-79757ccf-d150-485e-9888-348e0c60adcd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85067145103258808865397190622255359048983196544530576209643267535082890844090 -assert n
opostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err.85067145103258808865397190622255359048983196544530576209643267535082890844090
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.1839492100136428529001969451796010798202863043431689713074672673097007330088
Short name T177
Test name
Test status
Simulation time 108315125 ps
CPU time 0.93 seconds
Started Nov 22 12:29:46 PM PST 23
Finished Nov 22 12:29:48 PM PST 23
Peak memory 199712 kb
Host smart-a455a515-f6ff-4dc1-b296-73d6f1d14eb4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839492100136428529001969451796010798202863
043431689713074672673097007330088 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.1839492100136428529
001969451796010798202863043431689713074672673097007330088
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.99488391468638980745744909702735148965989323608300639928437568029263485967315
Short name T174
Test name
Test status
Simulation time 61856420 ps
CPU time 0.74 seconds
Started Nov 22 12:29:46 PM PST 23
Finished Nov 22 12:29:47 PM PST 23
Peak memory 199620 kb
Host smart-8d48a3ba-592b-40e8-ae17-bca96d125bd8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99488391468638980745744909702735148965989323608300639928437568029263485967315 -assert nopostproc
+UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.99488391468638980745744909702735148965989323608300639928437568029263485967315
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.56728572416948636443132145264882042547284148676706146386448883559987241909505
Short name T86
Test name
Test status
Simulation time 148107110 ps
CPU time 1.14 seconds
Started Nov 22 12:29:58 PM PST 23
Finished Nov 22 12:30:01 PM PST 23
Peak memory 199616 kb
Host smart-c131aff7-a319-427c-999b-b1f5f20e5c0c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56728572416948636443132145264882042547284148676706146386448883559987241909505
-assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_same_csr_outstanding.56728572416948636443132145264882042547284148676706146386448
883559987241909505
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.109488883908057213665813683121584718517235639908453236558143693353661379863998
Short name T150
Test name
Test status
Simulation time 333191924 ps
CPU time 2.25 seconds
Started Nov 22 12:29:46 PM PST 23
Finished Nov 22 12:29:49 PM PST 23
Peak memory 207960 kb
Host smart-e6756871-dfa0-4f47-b6a0-5162a1350ca6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109488883908057213665813683121584718517235639908453236558143693353661379863998 -assert nopostproc +
UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.109488883908057213665813683121584718517235639908453236558143693353661379863998
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.20425418453420903589603129679174189910772181789113897398772134730538153838142
Short name T183
Test name
Test status
Simulation time 486526484 ps
CPU time 1.94 seconds
Started Nov 22 12:29:46 PM PST 23
Finished Nov 22 12:29:49 PM PST 23
Peak memory 199780 kb
Host smart-cf672aa2-e488-4f36-b19d-0360343af1c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20425418453420903589603129679174189910772181789113897398772134730538153838142 -assert n
opostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_err.20425418453420903589603129679174189910772181789113897398772134730538153838142
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.88007563130943964949038639886458381396397533095766633060602626409327245080561
Short name T179
Test name
Test status
Simulation time 108315125 ps
CPU time 0.97 seconds
Started Nov 22 12:29:38 PM PST 23
Finished Nov 22 12:29:40 PM PST 23
Peak memory 199688 kb
Host smart-91bef3bc-1075-4f3e-9a21-0c4cba9d0ee8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8800756313094396494903863988645838139639753
3095766633060602626409327245080561 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.880075631309439649
49038639886458381396397533095766633060602626409327245080561
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.113136749457746422261020228623247966014680564744341952080543166442805211773711
Short name T161
Test name
Test status
Simulation time 61856420 ps
CPU time 0.76 seconds
Started Nov 22 12:29:55 PM PST 23
Finished Nov 22 12:30:00 PM PST 23
Peak memory 199692 kb
Host smart-a5fa80f5-4532-4b75-a585-70b5d9c7fd54
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113136749457746422261020228623247966014680564744341952080543166442805211773711 -assert nopostpro
c +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.113136749457746422261020228623247966014680564744341952080543166442805211773711
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.87360415491096886352807609439918529776692603506586092085351962021075655805982
Short name T78
Test name
Test status
Simulation time 148107110 ps
CPU time 1.48 seconds
Started Nov 22 12:29:31 PM PST 23
Finished Nov 22 12:29:34 PM PST 23
Peak memory 199664 kb
Host smart-3e8d08d5-d61b-4e10-a1d7-050d40e0f97d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87360415491096886352807609439918529776692603506586092085351962021075655805982
-assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_same_csr_outstanding.87360415491096886352807609439918529776692603506586092085351
962021075655805982
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.68440869379688576478618978764362264349905662543907958059181610062508554293907
Short name T194
Test name
Test status
Simulation time 333191924 ps
CPU time 2.41 seconds
Started Nov 22 12:29:39 PM PST 23
Finished Nov 22 12:29:43 PM PST 23
Peak memory 207964 kb
Host smart-1edfff5a-bead-45f3-9647-435e2420c1f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68440869379688576478618978764362264349905662543907958059181610062508554293907 -assert nopostproc +U
VM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.68440869379688576478618978764362264349905662543907958059181610062508554293907
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.23490924217655703987923151404067704072554649806003975037480144966811405540678
Short name T75
Test name
Test status
Simulation time 486526484 ps
CPU time 1.9 seconds
Started Nov 22 12:29:58 PM PST 23
Finished Nov 22 12:30:02 PM PST 23
Peak memory 199680 kb
Host smart-6a464e0d-0136-4ec4-8202-02eed0f4a5bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23490924217655703987923151404067704072554649806003975037480144966811405540678 -assert n
opostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_err.23490924217655703987923151404067704072554649806003975037480144966811405540678
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.9669236992919576599589111902107971460363830653358673782409935294630293295568
Short name T220
Test name
Test status
Simulation time 108315125 ps
CPU time 0.95 seconds
Started Nov 22 12:29:37 PM PST 23
Finished Nov 22 12:29:39 PM PST 23
Peak memory 199688 kb
Host smart-5dc727d1-947a-4dd8-9408-92ab2bb5c1de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9669236992919576599589111902107971460363830
653358673782409935294630293295568 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.9669236992919576599
589111902107971460363830653358673782409935294630293295568
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.41265949211431509785879084003097927961768459191888450668070382539941686580629
Short name T145
Test name
Test status
Simulation time 61856420 ps
CPU time 0.78 seconds
Started Nov 22 12:29:28 PM PST 23
Finished Nov 22 12:29:32 PM PST 23
Peak memory 199636 kb
Host smart-d2eeb57f-f47a-48a3-ab9d-740fc3860755
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41265949211431509785879084003097927961768459191888450668070382539941686580629 -assert nopostproc
+UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.41265949211431509785879084003097927961768459191888450668070382539941686580629
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.36818056565859645086389083431409478017759754606100934752632771165327562302497
Short name T189
Test name
Test status
Simulation time 148107110 ps
CPU time 1.12 seconds
Started Nov 22 12:29:37 PM PST 23
Finished Nov 22 12:29:39 PM PST 23
Peak memory 199696 kb
Host smart-51376e5c-a958-4753-8c37-7c7c321084d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36818056565859645086389083431409478017759754606100934752632771165327562302497
-assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_same_csr_outstanding.36818056565859645086389083431409478017759754606100934752632
771165327562302497
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.94758167132274206411646479027843947612709591942487411208309548545598115735833
Short name T159
Test name
Test status
Simulation time 333191924 ps
CPU time 2.3 seconds
Started Nov 22 12:29:39 PM PST 23
Finished Nov 22 12:29:43 PM PST 23
Peak memory 207932 kb
Host smart-b3ccb1bb-7997-49e1-acf7-dbea103d234a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94758167132274206411646479027843947612709591942487411208309548545598115735833 -assert nopostproc +U
VM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.94758167132274206411646479027843947612709591942487411208309548545598115735833
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.113722174097338405572269444298421313498423944685671295448310850568120931642858
Short name T193
Test name
Test status
Simulation time 486526484 ps
CPU time 2.03 seconds
Started Nov 22 12:29:37 PM PST 23
Finished Nov 22 12:29:41 PM PST 23
Peak memory 199800 kb
Host smart-d2929238-0172-4367-8e51-d061319ddbc1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113722174097338405572269444298421313498423944685671295448310850568120931642858 -assert
nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_err.113722174097338405572269444298421313498423944685671295448310850568120931642858
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.11262317590160627681083775907662351322177601903942804077941033383732362486531
Short name T170
Test name
Test status
Simulation time 108315125 ps
CPU time 0.94 seconds
Started Nov 22 12:30:12 PM PST 23
Finished Nov 22 12:30:14 PM PST 23
Peak memory 199808 kb
Host smart-91a6d57f-c9cf-48ed-948c-d45158432ecd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126231759016062768108377590766235132217760
1903942804077941033383732362486531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.112623175901606276
81083775907662351322177601903942804077941033383732362486531
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.110946989215448903617050271810436550474738590374891317808787278207919487047290
Short name T146
Test name
Test status
Simulation time 61856420 ps
CPU time 0.72 seconds
Started Nov 22 12:29:36 PM PST 23
Finished Nov 22 12:29:38 PM PST 23
Peak memory 199624 kb
Host smart-cada3d62-958c-41e7-8b0d-337845c90e34
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110946989215448903617050271810436550474738590374891317808787278207919487047290 -assert nopostpro
c +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.110946989215448903617050271810436550474738590374891317808787278207919487047290
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.103292978933452929080908363546882697793410835103157001518724622933373363154831
Short name T87
Test name
Test status
Simulation time 148107110 ps
CPU time 1.08 seconds
Started Nov 22 12:30:15 PM PST 23
Finished Nov 22 12:30:17 PM PST 23
Peak memory 199652 kb
Host smart-ee75335c-afae-4779-8f60-baec63f134a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103292978933452929080908363546882697793410835103157001518724622933373363154831
-assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_same_csr_outstanding.1032929789334529290809083635468826977934108351031570015187
24622933373363154831
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.109694522273958140579203975542729625764754209377228699618129269080395022779790
Short name T51
Test name
Test status
Simulation time 333191924 ps
CPU time 2.28 seconds
Started Nov 22 12:29:34 PM PST 23
Finished Nov 22 12:29:38 PM PST 23
Peak memory 207948 kb
Host smart-528384cb-95d7-4066-aed1-4a7ec6c7d77d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109694522273958140579203975542729625764754209377228699618129269080395022779790 -assert nopostproc +
UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.109694522273958140579203975542729625764754209377228699618129269080395022779790
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.53894902129656839299063646598419060589567838928221001284932160386772999815919
Short name T54
Test name
Test status
Simulation time 486526484 ps
CPU time 1.91 seconds
Started Nov 22 12:29:39 PM PST 23
Finished Nov 22 12:29:43 PM PST 23
Peak memory 199748 kb
Host smart-5b484abb-aae1-4b46-9417-97ec925a91af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53894902129656839299063646598419060589567838928221001284932160386772999815919 -assert n
opostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_err.53894902129656839299063646598419060589567838928221001284932160386772999815919
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.64191831341719296408955644774060239001657954957503462856540192537748512260862
Short name T171
Test name
Test status
Simulation time 108315125 ps
CPU time 0.9 seconds
Started Nov 22 12:30:06 PM PST 23
Finished Nov 22 12:30:08 PM PST 23
Peak memory 199684 kb
Host smart-be201d25-6c17-4d34-b5bc-bf6f81fd8593
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6419183134171929640895564477406023900165795
4957503462856540192537748512260862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.641918313417192964
08955644774060239001657954957503462856540192537748512260862
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.71426214827530662174064842860171915256652968941998363933911098933996516685716
Short name T164
Test name
Test status
Simulation time 61856420 ps
CPU time 0.74 seconds
Started Nov 22 12:30:08 PM PST 23
Finished Nov 22 12:30:10 PM PST 23
Peak memory 199684 kb
Host smart-e399daaf-5963-4923-a0d9-d1f8332987a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71426214827530662174064842860171915256652968941998363933911098933996516685716 -assert nopostproc
+UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.71426214827530662174064842860171915256652968941998363933911098933996516685716
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.2650031709879058580267122711978570894642948307977649786592308005393856834674
Short name T191
Test name
Test status
Simulation time 148107110 ps
CPU time 1.09 seconds
Started Nov 22 12:30:17 PM PST 23
Finished Nov 22 12:30:19 PM PST 23
Peak memory 199648 kb
Host smart-684018e1-609d-432e-8765-5943208201ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650031709879058580267122711978570894642948307977649786592308005393856834674 -
assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_same_csr_outstanding.265003170987905858026712271197857089464294830797764978659230
8005393856834674
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.12582897090744417353429367631254140516611187113498461554474703379548688475702
Short name T225
Test name
Test status
Simulation time 333191924 ps
CPU time 2.2 seconds
Started Nov 22 12:30:21 PM PST 23
Finished Nov 22 12:30:26 PM PST 23
Peak memory 208048 kb
Host smart-86599ffd-ebf8-4eb3-9533-56288b8d6379
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12582897090744417353429367631254140516611187113498461554474703379548688475702 -assert nopostproc +U
VM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.12582897090744417353429367631254140516611187113498461554474703379548688475702
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.27920782594778645505246889418203921736547944507430000522688510967373877692712
Short name T192
Test name
Test status
Simulation time 486526484 ps
CPU time 1.86 seconds
Started Nov 22 12:30:19 PM PST 23
Finished Nov 22 12:30:22 PM PST 23
Peak memory 199796 kb
Host smart-0949cc2d-b603-4749-8988-81cbd45bb732
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27920782594778645505246889418203921736547944507430000522688510967373877692712 -assert n
opostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_err.27920782594778645505246889418203921736547944507430000522688510967373877692712
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.14201349299615787612511299442308173584354227043902989561493847099530537884313
Short name T91
Test name
Test status
Simulation time 108315125 ps
CPU time 0.96 seconds
Started Nov 22 12:30:12 PM PST 23
Finished Nov 22 12:30:14 PM PST 23
Peak memory 199704 kb
Host smart-aa2318c0-e3a3-4212-9c2f-f961e39c55ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420134929961578761251129944230817358435422
7043902989561493847099530537884313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.142013492996157876
12511299442308173584354227043902989561493847099530537884313
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.59051283019785994780262232804395673434458412574765993342886248744973858011741
Short name T169
Test name
Test status
Simulation time 61856420 ps
CPU time 0.74 seconds
Started Nov 22 12:30:20 PM PST 23
Finished Nov 22 12:30:24 PM PST 23
Peak memory 199604 kb
Host smart-a3c93300-58fb-4493-a407-38e412a9a038
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59051283019785994780262232804395673434458412574765993342886248744973858011741 -assert nopostproc
+UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.59051283019785994780262232804395673434458412574765993342886248744973858011741
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.68996575480115213503811686720469988866757822281876131596863655373702711572870
Short name T197
Test name
Test status
Simulation time 148107110 ps
CPU time 1.13 seconds
Started Nov 22 12:30:12 PM PST 23
Finished Nov 22 12:30:14 PM PST 23
Peak memory 199716 kb
Host smart-60068506-a25c-43e6-8a31-db561c458896
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68996575480115213503811686720469988866757822281876131596863655373702711572870
-assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_same_csr_outstanding.68996575480115213503811686720469988866757822281876131596863
655373702711572870
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.87553452443100120641516251304404267594960427621584600769834723523853996133961
Short name T200
Test name
Test status
Simulation time 333191924 ps
CPU time 2.3 seconds
Started Nov 22 12:30:12 PM PST 23
Finished Nov 22 12:30:16 PM PST 23
Peak memory 207984 kb
Host smart-78eb7f4c-b9fa-4fbf-839c-76f29e051cc4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87553452443100120641516251304404267594960427621584600769834723523853996133961 -assert nopostproc +U
VM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.87553452443100120641516251304404267594960427621584600769834723523853996133961
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.104419025441914116402137561731626995915197627328602716219989931090238468405755
Short name T167
Test name
Test status
Simulation time 486526484 ps
CPU time 1.92 seconds
Started Nov 22 12:30:12 PM PST 23
Finished Nov 22 12:30:15 PM PST 23
Peak memory 199792 kb
Host smart-6d026f6c-abf7-4d99-b5e2-228e0d5f8a02
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104419025441914116402137561731626995915197627328602716219989931090238468405755 -assert
nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_err.104419025441914116402137561731626995915197627328602716219989931090238468405755
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.69761349434298762882129514656364149658206941287230326294063194236841705318377
Short name T45
Test name
Test status
Simulation time 108315125 ps
CPU time 0.94 seconds
Started Nov 22 12:30:11 PM PST 23
Finished Nov 22 12:30:13 PM PST 23
Peak memory 199700 kb
Host smart-7cd5a6aa-0886-4c2e-af2f-7d075a61a505
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6976134943429876288212951465636414965820694
1287230326294063194236841705318377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.697613494342987628
82129514656364149658206941287230326294063194236841705318377
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.68418221090356149106139315405255121415042548169114369039149232752134932654205
Short name T204
Test name
Test status
Simulation time 61856420 ps
CPU time 0.77 seconds
Started Nov 22 12:30:09 PM PST 23
Finished Nov 22 12:30:11 PM PST 23
Peak memory 199640 kb
Host smart-9a039ce8-34e6-47f2-8f9b-e81e29f6aa79
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68418221090356149106139315405255121415042548169114369039149232752134932654205 -assert nopostproc
+UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.68418221090356149106139315405255121415042548169114369039149232752134932654205
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.82872228343187533458702160849220110667933433567950758044971426305614631579920
Short name T201
Test name
Test status
Simulation time 148107110 ps
CPU time 1.11 seconds
Started Nov 22 12:30:10 PM PST 23
Finished Nov 22 12:30:12 PM PST 23
Peak memory 199696 kb
Host smart-8d065a4e-f214-4c22-a145-481d21f80c4c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82872228343187533458702160849220110667933433567950758044971426305614631579920
-assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_same_csr_outstanding.82872228343187533458702160849220110667933433567950758044971
426305614631579920
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.36912645466049857116126186186069833105053689330105082175477907934703405113430
Short name T228
Test name
Test status
Simulation time 333191924 ps
CPU time 2.23 seconds
Started Nov 22 12:30:09 PM PST 23
Finished Nov 22 12:30:12 PM PST 23
Peak memory 207976 kb
Host smart-b85c6d38-b100-46e3-8f41-0bb7c8c08e88
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36912645466049857116126186186069833105053689330105082175477907934703405113430 -assert nopostproc +U
VM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.36912645466049857116126186186069833105053689330105082175477907934703405113430
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.25770987030816959754648463082677993147068173319341718172375590568057948660551
Short name T74
Test name
Test status
Simulation time 486526484 ps
CPU time 1.93 seconds
Started Nov 22 12:30:20 PM PST 23
Finished Nov 22 12:30:25 PM PST 23
Peak memory 199708 kb
Host smart-9f7fb06c-65c3-46f3-89f2-f50c48d2bc53
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25770987030816959754648463082677993147068173319341718172375590568057948660551 -assert n
opostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_err.25770987030816959754648463082677993147068173319341718172375590568057948660551
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.51813012684259244615243269049895857651148555273518457681161536450884312457368
Short name T173
Test name
Test status
Simulation time 108315125 ps
CPU time 0.97 seconds
Started Nov 22 12:30:11 PM PST 23
Finished Nov 22 12:30:14 PM PST 23
Peak memory 199724 kb
Host smart-67041bcd-3361-4593-b3eb-43e04001e11d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5181301268425924461524326904989585765114855
5273518457681161536450884312457368 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.518130126842592446
15243269049895857651148555273518457681161536450884312457368
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.16356598030683121796056580920268223932631073886739184444444075131307905797948
Short name T227
Test name
Test status
Simulation time 61856420 ps
CPU time 0.72 seconds
Started Nov 22 12:30:16 PM PST 23
Finished Nov 22 12:30:17 PM PST 23
Peak memory 198988 kb
Host smart-e7d39d1e-a56c-4730-9f2c-e709ab561b13
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16356598030683121796056580920268223932631073886739184444444075131307905797948 -assert nopostproc
+UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.16356598030683121796056580920268223932631073886739184444444075131307905797948
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.45764425364708552091125624053487305568671144119000523186775112028786890038521
Short name T88
Test name
Test status
Simulation time 148107110 ps
CPU time 1.15 seconds
Started Nov 22 12:30:11 PM PST 23
Finished Nov 22 12:30:13 PM PST 23
Peak memory 199816 kb
Host smart-84173799-3cc8-44a8-9479-132d8eb2edaa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45764425364708552091125624053487305568671144119000523186775112028786890038521
-assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_same_csr_outstanding.45764425364708552091125624053487305568671144119000523186775
112028786890038521
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.38802481759492221551881558638852263850331045957979746228241365785274556088920
Short name T172
Test name
Test status
Simulation time 333191924 ps
CPU time 2.4 seconds
Started Nov 22 12:30:10 PM PST 23
Finished Nov 22 12:30:13 PM PST 23
Peak memory 207976 kb
Host smart-b2ec0bd0-0e00-4dc4-83c2-b597cd63bd77
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38802481759492221551881558638852263850331045957979746228241365785274556088920 -assert nopostproc +U
VM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.38802481759492221551881558638852263850331045957979746228241365785274556088920
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.1225982885303924302147751692292654286066244142183718886929497138554606524137
Short name T186
Test name
Test status
Simulation time 486526484 ps
CPU time 1.96 seconds
Started Nov 22 12:30:11 PM PST 23
Finished Nov 22 12:30:13 PM PST 23
Peak memory 199800 kb
Host smart-7396d39e-882f-4472-89b5-0bc5dd973871
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225982885303924302147751692292654286066244142183718886929497138554606524137 -assert no
postproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_err.1225982885303924302147751692292654286066244142183718886929497138554606524137
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.54416143047779438858825148724840997959405510076763059538447195083947617069626
Short name T157
Test name
Test status
Simulation time 108315125 ps
CPU time 0.95 seconds
Started Nov 22 12:30:16 PM PST 23
Finished Nov 22 12:30:17 PM PST 23
Peak memory 199688 kb
Host smart-b372b3eb-2794-4c7d-ab15-42cce94401de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5441614304777943885882514872484099795940551
0076763059538447195083947617069626 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.544161430477794388
58825148724840997959405510076763059538447195083947617069626
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.105967480489673059812874169597840825663415923722680794714565954638483004835588
Short name T219
Test name
Test status
Simulation time 61856420 ps
CPU time 0.75 seconds
Started Nov 22 12:30:07 PM PST 23
Finished Nov 22 12:30:09 PM PST 23
Peak memory 199628 kb
Host smart-467793a2-1878-4e73-983e-604869b89d48
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105967480489673059812874169597840825663415923722680794714565954638483004835588 -assert nopostpro
c +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.105967480489673059812874169597840825663415923722680794714565954638483004835588
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.75684842640177932466467228843051542204498687548488261093980116521699466021350
Short name T223
Test name
Test status
Simulation time 148107110 ps
CPU time 1.11 seconds
Started Nov 22 12:30:11 PM PST 23
Finished Nov 22 12:30:13 PM PST 23
Peak memory 199668 kb
Host smart-0ea758a2-fe55-464d-8dd0-32545b535378
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75684842640177932466467228843051542204498687548488261093980116521699466021350
-assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_same_csr_outstanding.75684842640177932466467228843051542204498687548488261093980
116521699466021350
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.96257542102500476318244003791719564751651290039631392158156020034647938193774
Short name T176
Test name
Test status
Simulation time 333191924 ps
CPU time 2.29 seconds
Started Nov 22 12:30:11 PM PST 23
Finished Nov 22 12:30:14 PM PST 23
Peak memory 207952 kb
Host smart-a7a40ed2-3e6f-4bd9-a772-0a9e4f106782
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96257542102500476318244003791719564751651290039631392158156020034647938193774 -assert nopostproc +U
VM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.96257542102500476318244003791719564751651290039631392158156020034647938193774
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.91233606814769977635924260503518255999146354926194519597603617816735288913911
Short name T155
Test name
Test status
Simulation time 486526484 ps
CPU time 1.94 seconds
Started Nov 22 12:30:16 PM PST 23
Finished Nov 22 12:30:18 PM PST 23
Peak memory 199212 kb
Host smart-82dd0e62-a8c7-469e-8355-c2c0ccd5c1c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91233606814769977635924260503518255999146354926194519597603617816735288913911 -assert n
opostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_err.91233606814769977635924260503518255999146354926194519597603617816735288913911
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.30785423644317424323073116611668955134637509244187310872618606408371002557291
Short name T90
Test name
Test status
Simulation time 108315125 ps
CPU time 1.02 seconds
Started Nov 22 12:30:12 PM PST 23
Finished Nov 22 12:30:14 PM PST 23
Peak memory 199808 kb
Host smart-25708171-198a-4cec-a979-abc1765160a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078542364431742432307311661166895513463750
9244187310872618606408371002557291 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.307854236443174243
23073116611668955134637509244187310872618606408371002557291
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.115290423819085320462914406535003071628643804040187037413850392460055403656348
Short name T195
Test name
Test status
Simulation time 61856420 ps
CPU time 0.73 seconds
Started Nov 22 12:30:32 PM PST 23
Finished Nov 22 12:30:35 PM PST 23
Peak memory 199600 kb
Host smart-06580b56-dd4b-4b59-84a5-67be79522173
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115290423819085320462914406535003071628643804040187037413850392460055403656348 -assert nopostpro
c +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.115290423819085320462914406535003071628643804040187037413850392460055403656348
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.108853655949812629258794694706327663458831016187419510918507325707780008439051
Short name T80
Test name
Test status
Simulation time 148107110 ps
CPU time 1.1 seconds
Started Nov 22 12:30:32 PM PST 23
Finished Nov 22 12:30:36 PM PST 23
Peak memory 199656 kb
Host smart-a3311f65-6900-490c-a4c7-0af786e4d364
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108853655949812629258794694706327663458831016187419510918507325707780008439051
-assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_same_csr_outstanding.1088536559498126292587946947063276634588310161874195109185
07325707780008439051
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.45986060377121038299854210217286134754143783019508043735387955434464387717199
Short name T52
Test name
Test status
Simulation time 333191924 ps
CPU time 2.28 seconds
Started Nov 22 12:30:19 PM PST 23
Finished Nov 22 12:30:22 PM PST 23
Peak memory 207188 kb
Host smart-0e6e8681-bfab-4434-9b29-1a7962b2b2ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45986060377121038299854210217286134754143783019508043735387955434464387717199 -assert nopostproc +U
VM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.45986060377121038299854210217286134754143783019508043735387955434464387717199
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.50725931737361595204548016807410259265623397713432799772748977228774738494305
Short name T224
Test name
Test status
Simulation time 486526484 ps
CPU time 1.91 seconds
Started Nov 22 12:30:16 PM PST 23
Finished Nov 22 12:30:19 PM PST 23
Peak memory 199776 kb
Host smart-d9f8e3d2-08bc-485c-b772-0be123796443
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50725931737361595204548016807410259265623397713432799772748977228774738494305 -assert n
opostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_err.50725931737361595204548016807410259265623397713432799772748977228774738494305
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.75965020989992775835326440672817238809990326520460796653528935910013771564269
Short name T166
Test name
Test status
Simulation time 222441038 ps
CPU time 1.54 seconds
Started Nov 22 12:29:23 PM PST 23
Finished Nov 22 12:29:27 PM PST 23
Peak memory 199732 kb
Host smart-9cfeb244-9f89-4d3b-975e-46ddf4bccf4f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75965020989992775835326440672817238809990326520460796653528935910013771564269 -assert nopo
stproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.75965020989992775835326440672817238809990326520460796653528935910013771564269
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.56115559108801138233528456263295383842446529956557725006196164699487886159319
Short name T206
Test name
Test status
Simulation time 1017822401 ps
CPU time 4.76 seconds
Started Nov 22 12:29:23 PM PST 23
Finished Nov 22 12:29:30 PM PST 23
Peak memory 199728 kb
Host smart-6bc70d68-6241-43d7-936e-6ef28b0ba3dd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56115559108801138233528456263295383842446529956557725006196164699487886159319 -assert nopo
stproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.56115559108801138233528456263295383842446529956557725006196164699487886159319
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.68877864184273173391505061732873869014046589029066831916123388031725231959555
Short name T214
Test name
Test status
Simulation time 108023456 ps
CPU time 0.85 seconds
Started Nov 22 12:29:27 PM PST 23
Finished Nov 22 12:29:30 PM PST 23
Peak memory 199636 kb
Host smart-750737f1-275d-4ee9-9769-ddc0c7233b2d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68877864184273173391505061732873869014046589029066831916123388031725231959555 -assert nopo
stproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.68877864184273173391505061732873869014046589029066831916123388031725231959555
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.100935027451497636724608232072952483612682884098705922876344129979128835013445
Short name T181
Test name
Test status
Simulation time 108315125 ps
CPU time 1 seconds
Started Nov 22 12:29:27 PM PST 23
Finished Nov 22 12:29:30 PM PST 23
Peak memory 199684 kb
Host smart-3b0437f1-741f-4edd-87b7-ced3c655faaa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009350274514976367246082320729524836126828
84098705922876344129979128835013445 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.100935027451497636
724608232072952483612682884098705922876344129979128835013445
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.42160902608870906229611118684263444227055788658898943896709048082333205436514
Short name T163
Test name
Test status
Simulation time 61856420 ps
CPU time 0.74 seconds
Started Nov 22 12:29:16 PM PST 23
Finished Nov 22 12:29:18 PM PST 23
Peak memory 199632 kb
Host smart-5e287ec5-8987-4790-bf0f-4fdb2f3bae33
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42160902608870906229611118684263444227055788658898943896709048082333205436514 -assert nopostproc
+UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.42160902608870906229611118684263444227055788658898943896709048082333205436514
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.37427899183804564912292921235570511242324928285106361324891049508822717294106
Short name T196
Test name
Test status
Simulation time 148107110 ps
CPU time 1.08 seconds
Started Nov 22 12:29:23 PM PST 23
Finished Nov 22 12:29:26 PM PST 23
Peak memory 199440 kb
Host smart-b0c3e55c-a172-462f-8629-9d66ad78c8b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37427899183804564912292921235570511242324928285106361324891049508822717294106
-assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_same_csr_outstanding.374278991838045649122929212355705112423249282851063613248910
49508822717294106
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.100882745753195803808411831053211447066880692092770320155502973028259621895154
Short name T226
Test name
Test status
Simulation time 333191924 ps
CPU time 2.27 seconds
Started Nov 22 12:29:26 PM PST 23
Finished Nov 22 12:29:31 PM PST 23
Peak memory 207976 kb
Host smart-062596cc-24f2-4cd6-aaec-8bf06c818860
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100882745753195803808411831053211447066880692092770320155502973028259621895154 -assert nopostproc +
UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.100882745753195803808411831053211447066880692092770320155502973028259621895154
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.4379938728105516558380466077715136368727959329660820828687833751412276543603
Short name T190
Test name
Test status
Simulation time 222441038 ps
CPU time 1.62 seconds
Started Nov 22 12:29:25 PM PST 23
Finished Nov 22 12:29:28 PM PST 23
Peak memory 199840 kb
Host smart-2dd0a144-6a3a-422f-ac6b-83f72c43abb4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4379938728105516558380466077715136368727959329660820828687833751412276543603 -assert nopos
tproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.4379938728105516558380466077715136368727959329660820828687833751412276543603
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.13964383040915281339177287188773553324516303138318478051999709798435118078744
Short name T208
Test name
Test status
Simulation time 1017822401 ps
CPU time 4.97 seconds
Started Nov 22 12:29:34 PM PST 23
Finished Nov 22 12:29:40 PM PST 23
Peak memory 199712 kb
Host smart-52905979-4a4c-48de-b682-a980afaab44f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13964383040915281339177287188773553324516303138318478051999709798435118078744 -assert nopo
stproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.13964383040915281339177287188773553324516303138318478051999709798435118078744
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.70022023464530382634278003138055473492817886383394567857688796220753085999265
Short name T48
Test name
Test status
Simulation time 108023456 ps
CPU time 0.81 seconds
Started Nov 22 12:29:26 PM PST 23
Finished Nov 22 12:29:30 PM PST 23
Peak memory 199620 kb
Host smart-820a694a-15e6-4ef7-9c25-9b142dd8b0b3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70022023464530382634278003138055473492817886383394567857688796220753085999265 -assert nopo
stproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.70022023464530382634278003138055473492817886383394567857688796220753085999265
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.47954676446883586066021033346829378131466563298277728492426504049005748876111
Short name T210
Test name
Test status
Simulation time 108315125 ps
CPU time 0.93 seconds
Started Nov 22 12:29:25 PM PST 23
Finished Nov 22 12:29:28 PM PST 23
Peak memory 199652 kb
Host smart-a8d5eb51-9f35-43b9-b533-32771f3ab340
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4795467644688358606602103334682937813146656
3298277728492426504049005748876111 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.4795467644688358606
6021033346829378131466563298277728492426504049005748876111
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.2919759464368143027446591420151054958102515532997095961202648913316895783915
Short name T149
Test name
Test status
Simulation time 61856420 ps
CPU time 0.73 seconds
Started Nov 22 12:29:18 PM PST 23
Finished Nov 22 12:29:21 PM PST 23
Peak memory 199644 kb
Host smart-7f6ef95c-9da8-41c3-8241-07df28079b6c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919759464368143027446591420151054958102515532997095961202648913316895783915 -assert nopostproc
+UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.2919759464368143027446591420151054958102515532997095961202648913316895783915
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.100108825801583519772272463231693934397465366604967400091519558109711558837711
Short name T76
Test name
Test status
Simulation time 148107110 ps
CPU time 1.09 seconds
Started Nov 22 12:29:25 PM PST 23
Finished Nov 22 12:29:28 PM PST 23
Peak memory 199820 kb
Host smart-e077c9ed-1f26-4aa0-910b-e3e973936535
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100108825801583519772272463231693934397465366604967400091519558109711558837711
-assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_same_csr_outstanding.10010882580158351977227246323169393439746536660496740009151
9558109711558837711
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.4350669312175243230968269115796898393878568908839562093397790165161987761186
Short name T184
Test name
Test status
Simulation time 333191924 ps
CPU time 2.25 seconds
Started Nov 22 12:29:23 PM PST 23
Finished Nov 22 12:29:28 PM PST 23
Peak memory 207988 kb
Host smart-bd62763a-0b43-49ed-b5c4-d0267c0443e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4350669312175243230968269115796898393878568908839562093397790165161987761186 -assert nopostproc +UV
M_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.4350669312175243230968269115796898393878568908839562093397790165161987761186
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.28732038368428419064963961863625600803474174306787128474490228489400639311994
Short name T162
Test name
Test status
Simulation time 486526484 ps
CPU time 1.93 seconds
Started Nov 22 12:29:23 PM PST 23
Finished Nov 22 12:29:27 PM PST 23
Peak memory 199788 kb
Host smart-34a71452-8b5d-4c58-b357-3293043871df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28732038368428419064963961863625600803474174306787128474490228489400639311994 -assert n
opostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err.28732038368428419064963961863625600803474174306787128474490228489400639311994
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.14666913099288140090967649742177166684640661634835530611826629441191853940050
Short name T147
Test name
Test status
Simulation time 222441038 ps
CPU time 1.65 seconds
Started Nov 22 12:29:25 PM PST 23
Finished Nov 22 12:29:29 PM PST 23
Peak memory 199700 kb
Host smart-ca276050-e6e6-41e0-af4d-4f0d4458071e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14666913099288140090967649742177166684640661634835530611826629441191853940050 -assert nopo
stproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.14666913099288140090967649742177166684640661634835530611826629441191853940050
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.108573553284617983612789861581167467992434093767490353964907300582645358737690
Short name T81
Test name
Test status
Simulation time 1017822401 ps
CPU time 5.06 seconds
Started Nov 22 12:29:34 PM PST 23
Finished Nov 22 12:29:41 PM PST 23
Peak memory 199700 kb
Host smart-f44685cf-92f0-4693-9fad-5ab75747de15
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108573553284617983612789861581167467992434093767490353964907300582645358737690 -assert nop
ostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.108573553284617983612789861581167467992434093767490353964907300582645358737690
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.89745787342709027127867834280481349845962362594594142711906491307201569883866
Short name T47
Test name
Test status
Simulation time 108023456 ps
CPU time 0.82 seconds
Started Nov 22 12:29:25 PM PST 23
Finished Nov 22 12:29:28 PM PST 23
Peak memory 199600 kb
Host smart-cbcd380d-f99d-4471-83ac-9374e02be78f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89745787342709027127867834280481349845962362594594142711906491307201569883866 -assert nopo
stproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.89745787342709027127867834280481349845962362594594142711906491307201569883866
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.56065023014084524233368721155822541980690617663742870587868788280149968287587
Short name T50
Test name
Test status
Simulation time 108315125 ps
CPU time 0.92 seconds
Started Nov 22 12:29:25 PM PST 23
Finished Nov 22 12:29:28 PM PST 23
Peak memory 199684 kb
Host smart-6937543c-68eb-408c-a7d7-4169bb58848a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5606502301408452423336872115582254198069061
7663742870587868788280149968287587 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.5606502301408452423
3368721155822541980690617663742870587868788280149968287587
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.92260784111453864379435399829306948676411501937239744641256785491649850975151
Short name T154
Test name
Test status
Simulation time 61856420 ps
CPU time 0.73 seconds
Started Nov 22 12:29:25 PM PST 23
Finished Nov 22 12:29:28 PM PST 23
Peak memory 199616 kb
Host smart-9125b032-e0aa-4225-947c-9cae237a27a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92260784111453864379435399829306948676411501937239744641256785491649850975151 -assert nopostproc
+UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.92260784111453864379435399829306948676411501937239744641256785491649850975151
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.96892490097284255480855816510781878955845443803506209051951210001123160744868
Short name T217
Test name
Test status
Simulation time 148107110 ps
CPU time 1.11 seconds
Started Nov 22 12:29:25 PM PST 23
Finished Nov 22 12:29:28 PM PST 23
Peak memory 199816 kb
Host smart-1270cab9-1353-421a-a343-935caf20a1bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96892490097284255480855816510781878955845443803506209051951210001123160744868
-assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_same_csr_outstanding.968924900972842554808558165107818789558454438035062090519512
10001123160744868
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.82527448732581528290781922037242265605148330128898174772973148359357286049270
Short name T72
Test name
Test status
Simulation time 333191924 ps
CPU time 2.24 seconds
Started Nov 22 12:29:23 PM PST 23
Finished Nov 22 12:29:27 PM PST 23
Peak memory 207944 kb
Host smart-9bafd2c5-d95f-44d2-a547-3553d5655b84
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82527448732581528290781922037242265605148330128898174772973148359357286049270 -assert nopostproc +U
VM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.82527448732581528290781922037242265605148330128898174772973148359357286049270
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.30619414299038907999569830168031563258052359602639651436748395974305732049143
Short name T53
Test name
Test status
Simulation time 486526484 ps
CPU time 1.86 seconds
Started Nov 22 12:29:32 PM PST 23
Finished Nov 22 12:29:35 PM PST 23
Peak memory 199760 kb
Host smart-e8eb4f0c-69d0-47dd-838d-7b4a7cb570a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30619414299038907999569830168031563258052359602639651436748395974305732049143 -assert n
opostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err.30619414299038907999569830168031563258052359602639651436748395974305732049143
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.85418412840065559388666203144845835071747422527565603378422674893255361318024
Short name T82
Test name
Test status
Simulation time 108315125 ps
CPU time 0.93 seconds
Started Nov 22 12:29:20 PM PST 23
Finished Nov 22 12:29:23 PM PST 23
Peak memory 199700 kb
Host smart-710f238d-7dff-431d-9abb-8d20ef51300f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8541841284006555938866620314484583507174742
2527565603378422674893255361318024 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.8541841284006555938
8666203144845835071747422527565603378422674893255361318024
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.42525163897611087528341960824529018783094555438969108646546292483670595974513
Short name T153
Test name
Test status
Simulation time 61856420 ps
CPU time 0.7 seconds
Started Nov 22 12:29:34 PM PST 23
Finished Nov 22 12:29:36 PM PST 23
Peak memory 199636 kb
Host smart-9d8ab52c-b7e9-4f06-8580-2e722eca471c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42525163897611087528341960824529018783094555438969108646546292483670595974513 -assert nopostproc
+UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.42525163897611087528341960824529018783094555438969108646546292483670595974513
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.85755354838495565789502812574149483210725426825012746744944873240437970338356
Short name T207
Test name
Test status
Simulation time 148107110 ps
CPU time 1.13 seconds
Started Nov 22 12:29:33 PM PST 23
Finished Nov 22 12:29:35 PM PST 23
Peak memory 199652 kb
Host smart-b6fbefaf-9339-4bca-8ff3-13405ead1c9f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85755354838495565789502812574149483210725426825012746744944873240437970338356
-assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_same_csr_outstanding.857553548384955657895028125741494832107254268250127467449448
73240437970338356
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.98621869331661106145609962041597593640151077940647925422963705308728211228804
Short name T175
Test name
Test status
Simulation time 333191924 ps
CPU time 2.38 seconds
Started Nov 22 12:29:25 PM PST 23
Finished Nov 22 12:29:30 PM PST 23
Peak memory 207948 kb
Host smart-124453d6-16c2-4e4a-893e-6d101d59a017
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98621869331661106145609962041597593640151077940647925422963705308728211228804 -assert nopostproc +U
VM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.98621869331661106145609962041597593640151077940647925422963705308728211228804
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.88862862475388047603662723141960795395279382134821387753910808558182362658600
Short name T188
Test name
Test status
Simulation time 486526484 ps
CPU time 1.84 seconds
Started Nov 22 12:29:33 PM PST 23
Finished Nov 22 12:29:36 PM PST 23
Peak memory 199756 kb
Host smart-09119a7c-3348-419b-9a9d-89b1d7327d76
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88862862475388047603662723141960795395279382134821387753910808558182362658600 -assert n
opostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err.88862862475388047603662723141960795395279382134821387753910808558182362658600
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.22431512504046315683211822199306714951423819146665266543685631333960246303276
Short name T218
Test name
Test status
Simulation time 108315125 ps
CPU time 0.96 seconds
Started Nov 22 12:29:30 PM PST 23
Finished Nov 22 12:29:32 PM PST 23
Peak memory 199648 kb
Host smart-80d9b122-6018-4f6f-a43f-401b7cffe908
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243151250404631568321182219930671495142381
9146665266543685631333960246303276 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.2243151250404631568
3211822199306714951423819146665266543685631333960246303276
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.3157878882601714230108455936548665620994169960432452491132219246970133258432
Short name T83
Test name
Test status
Simulation time 61856420 ps
CPU time 0.71 seconds
Started Nov 22 12:29:26 PM PST 23
Finished Nov 22 12:29:30 PM PST 23
Peak memory 199648 kb
Host smart-d6651123-79ca-4ed3-9427-279fe179777a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157878882601714230108455936548665620994169960432452491132219246970133258432 -assert nopostproc
+UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.3157878882601714230108455936548665620994169960432452491132219246970133258432
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.103764504533178126104331461368594805419813744648811441804462234229821453487778
Short name T59
Test name
Test status
Simulation time 148107110 ps
CPU time 1.15 seconds
Started Nov 22 12:29:29 PM PST 23
Finished Nov 22 12:29:32 PM PST 23
Peak memory 199732 kb
Host smart-b8723bbd-0262-405b-a548-4d541781b57d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103764504533178126104331461368594805419813744648811441804462234229821453487778
-assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_same_csr_outstanding.10376450453317812610433146136859480541981374464881144180446
2234229821453487778
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.84919093930568954405720552620725640356041458964999723556901853483705378789390
Short name T160
Test name
Test status
Simulation time 333191924 ps
CPU time 2.26 seconds
Started Nov 22 12:29:25 PM PST 23
Finished Nov 22 12:29:30 PM PST 23
Peak memory 207980 kb
Host smart-c8ecefb0-f6db-4c5b-887f-0fb42472fb45
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84919093930568954405720552620725640356041458964999723556901853483705378789390 -assert nopostproc +U
VM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.84919093930568954405720552620725640356041458964999723556901853483705378789390
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.28510113152369924442260685980023908977902825597173437234670720809364689763978
Short name T156
Test name
Test status
Simulation time 486526484 ps
CPU time 1.88 seconds
Started Nov 22 12:29:29 PM PST 23
Finished Nov 22 12:29:33 PM PST 23
Peak memory 199764 kb
Host smart-5ad88528-d1cd-4499-b402-4059b33cd8da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28510113152369924442260685980023908977902825597173437234670720809364689763978 -assert n
opostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err.28510113152369924442260685980023908977902825597173437234670720809364689763978
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.4692572942240132634581041840044130546092012169152395285559985729239808917594
Short name T213
Test name
Test status
Simulation time 108315125 ps
CPU time 0.97 seconds
Started Nov 22 12:29:34 PM PST 23
Finished Nov 22 12:29:37 PM PST 23
Peak memory 199700 kb
Host smart-bd324a62-c147-4b09-bcc0-04d484052baa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4692572942240132634581041840044130546092012
169152395285559985729239808917594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.46925729422401326345
81041840044130546092012169152395285559985729239808917594
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.45677988017327127989482338355293092646333525142779014598020069886836470805314
Short name T205
Test name
Test status
Simulation time 61856420 ps
CPU time 0.72 seconds
Started Nov 22 12:29:37 PM PST 23
Finished Nov 22 12:29:39 PM PST 23
Peak memory 199632 kb
Host smart-c078c8c1-463f-498e-9de1-0bab31762644
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45677988017327127989482338355293092646333525142779014598020069886836470805314 -assert nopostproc
+UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.45677988017327127989482338355293092646333525142779014598020069886836470805314
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.15413997815195263920938673209808768665208656176332440210284117589701146962021
Short name T85
Test name
Test status
Simulation time 148107110 ps
CPU time 1.12 seconds
Started Nov 22 12:29:40 PM PST 23
Finished Nov 22 12:29:42 PM PST 23
Peak memory 199680 kb
Host smart-28dd9d9c-4ceb-44d2-9afc-ea753b0dcb3e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15413997815195263920938673209808768665208656176332440210284117589701146962021
-assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_same_csr_outstanding.154139978151952639209386732098087686652086561763324402102841
17589701146962021
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.74764494823137569024109275079949159115692782344491883426374286193219364311253
Short name T178
Test name
Test status
Simulation time 333191924 ps
CPU time 2.22 seconds
Started Nov 22 12:29:33 PM PST 23
Finished Nov 22 12:29:36 PM PST 23
Peak memory 207980 kb
Host smart-dfd6e676-f2f4-48fc-b98b-3e27acfe8ea4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74764494823137569024109275079949159115692782344491883426374286193219364311253 -assert nopostproc +U
VM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.74764494823137569024109275079949159115692782344491883426374286193219364311253
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.68815215643957411605536972719169207558969325954357815355940220199776619623408
Short name T168
Test name
Test status
Simulation time 486526484 ps
CPU time 1.89 seconds
Started Nov 22 12:29:23 PM PST 23
Finished Nov 22 12:29:27 PM PST 23
Peak memory 199792 kb
Host smart-3ed22380-f714-43d0-9900-dd03c49eb136
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68815215643957411605536972719169207558969325954357815355940220199776619623408 -assert n
opostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err.68815215643957411605536972719169207558969325954357815355940220199776619623408
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.83232092910509724781890818591776475450681567030425699323302070362566766352892
Short name T49
Test name
Test status
Simulation time 108315125 ps
CPU time 0.92 seconds
Started Nov 22 12:29:41 PM PST 23
Finished Nov 22 12:29:43 PM PST 23
Peak memory 199688 kb
Host smart-f05d30fc-d644-432e-9265-dc5b3edcc8a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8323209291050972478189081859177647545068156
7030425699323302070362566766352892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.8323209291050972478
1890818591776475450681567030425699323302070362566766352892
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.44142293505864190206741016905296229998698585218594563940256715936663076111876
Short name T182
Test name
Test status
Simulation time 61856420 ps
CPU time 0.76 seconds
Started Nov 22 12:29:38 PM PST 23
Finished Nov 22 12:29:40 PM PST 23
Peak memory 199664 kb
Host smart-33993a22-0b9e-407a-ba47-80e7ce5cefb6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44142293505864190206741016905296229998698585218594563940256715936663076111876 -assert nopostproc
+UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.44142293505864190206741016905296229998698585218594563940256715936663076111876
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.100371044804016097418992605902175977092100977877926447555165291362273729379001
Short name T215
Test name
Test status
Simulation time 148107110 ps
CPU time 1.09 seconds
Started Nov 22 12:29:37 PM PST 23
Finished Nov 22 12:29:39 PM PST 23
Peak memory 199688 kb
Host smart-7b8b587d-7fe2-4f15-af9e-20d0f054d05b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100371044804016097418992605902175977092100977877926447555165291362273729379001
-assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_same_csr_outstanding.10037104480401609741899260590217597709210097787792644755516
5291362273729379001
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.40120586353845991618645683284362668342337455527601683925921201596584169102679
Short name T151
Test name
Test status
Simulation time 333191924 ps
CPU time 2.18 seconds
Started Nov 22 12:29:34 PM PST 23
Finished Nov 22 12:29:37 PM PST 23
Peak memory 207980 kb
Host smart-e490ed1d-30d7-4ec7-a62a-dc9dc53f5f78
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40120586353845991618645683284362668342337455527601683925921201596584169102679 -assert nopostproc +U
VM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.40120586353845991618645683284362668342337455527601683925921201596584169102679
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.60689963542814253188572264572274822837764786961203741795717644716067963468316
Short name T221
Test name
Test status
Simulation time 486526484 ps
CPU time 1.92 seconds
Started Nov 22 12:29:37 PM PST 23
Finished Nov 22 12:29:40 PM PST 23
Peak memory 199788 kb
Host smart-cc9cd363-a0f2-4965-b941-f2bf9f941bbe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60689963542814253188572264572274822837764786961203741795717644716067963468316 -assert n
opostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err.60689963542814253188572264572274822837764786961203741795717644716067963468316
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.73994569876234147961206512932483738719189665037352096100399302882226497806610
Short name T180
Test name
Test status
Simulation time 108315125 ps
CPU time 0.91 seconds
Started Nov 22 12:29:39 PM PST 23
Finished Nov 22 12:29:42 PM PST 23
Peak memory 199668 kb
Host smart-9ba4be41-76d8-4a9b-8e16-7432cc4a4fb8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7399456987623414796120651293248373871918966
5037352096100399302882226497806610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.7399456987623414796
1206512932483738719189665037352096100399302882226497806610
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.48290240474715125065251162387596858635671245998717082374055287799575549364127
Short name T79
Test name
Test status
Simulation time 61856420 ps
CPU time 0.72 seconds
Started Nov 22 12:29:42 PM PST 23
Finished Nov 22 12:29:43 PM PST 23
Peak memory 199580 kb
Host smart-2cb0573e-6522-4d83-a9ce-fe499c2eb441
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48290240474715125065251162387596858635671245998717082374055287799575549364127 -assert nopostproc
+UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.48290240474715125065251162387596858635671245998717082374055287799575549364127
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.83526717052678710426849285772872962180622659586682973500998946365046890516433
Short name T89
Test name
Test status
Simulation time 148107110 ps
CPU time 1.08 seconds
Started Nov 22 12:29:46 PM PST 23
Finished Nov 22 12:29:47 PM PST 23
Peak memory 199712 kb
Host smart-f59789b5-348a-41d8-b58a-1c4c453240a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83526717052678710426849285772872962180622659586682973500998946365046890516433
-assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_same_csr_outstanding.835267170526787104268492857728729621806226595866829735009989
46365046890516433
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.59990090151117657567774460369157299164173374441074624465682106141350308460626
Short name T73
Test name
Test status
Simulation time 333191924 ps
CPU time 2.26 seconds
Started Nov 22 12:29:35 PM PST 23
Finished Nov 22 12:29:39 PM PST 23
Peak memory 207984 kb
Host smart-1a07d6cf-f1de-48f7-b234-d700da7c392e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59990090151117657567774460369157299164173374441074624465682106141350308460626 -assert nopostproc +U
VM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.59990090151117657567774460369157299164173374441074624465682106141350308460626
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.78906551552526378725803258894579976457156479065125188373943781419890127260606
Short name T203
Test name
Test status
Simulation time 486526484 ps
CPU time 1.89 seconds
Started Nov 22 12:29:37 PM PST 23
Finished Nov 22 12:29:41 PM PST 23
Peak memory 199784 kb
Host smart-c2976b18-092b-4de2-9e86-b362bbaedd54
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78906551552526378725803258894579976457156479065125188373943781419890127260606 -assert n
opostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err.78906551552526378725803258894579976457156479065125188373943781419890127260606
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.107237281295299171181003946587900828762494070464913013199431320848528967035169
Short name T563
Test name
Test status
Simulation time 78981557 ps
CPU time 0.81 seconds
Started Nov 22 12:39:25 PM PST 23
Finished Nov 22 12:39:28 PM PST 23
Peak memory 199720 kb
Host smart-d89375e0-28f7-4cb0-a0fa-983736192f07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107237281295299171181003946587900828762494070464913013199431320848528967035169 -assert nopostp
roc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.107237281295299171181003946587900828762494070464913013199431320848528967035169
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.82113441016619723813058195879581943631026832461505003007063523498168166704704
Short name T445
Test name
Test status
Simulation time 2162831562 ps
CPU time 7.99 seconds
Started Nov 22 12:39:29 PM PST 23
Finished Nov 22 12:39:39 PM PST 23
Peak memory 216944 kb
Host smart-d478aaeb-fc16-4eaa-835e-7573fd6f9e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82113441016619723813058195879581943631026832461505003007063523498168166704704 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 0.rstmgr_leaf_rst_cnsty.82113441016619723813058195879581943631026832461505003007063523498168166704704
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.73421756043831233268007655534310956959764601643456290942526915331858585674727
Short name T454
Test name
Test status
Simulation time 243816210 ps
CPU time 1.05 seconds
Started Nov 22 12:39:19 PM PST 23
Finished Nov 22 12:39:23 PM PST 23
Peak memory 216824 kb
Host smart-7bc2c5b4-1b62-4000-8a2f-a4749d1b615f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73421756043831233268007655534310956959764601643456290942526915331858585674727 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.73421756043831233268007655534310956959764601643456290942526915331858585674727
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.108410219348757797301343125822173609270114505966343423376845731003637338524436
Short name T284
Test name
Test status
Simulation time 230357768 ps
CPU time 0.95 seconds
Started Nov 22 12:39:23 PM PST 23
Finished Nov 22 12:39:26 PM PST 23
Peak memory 199676 kb
Host smart-11dbf927-2f12-4ca0-97fe-217b066e4392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108410219348757797301343125822173609270114505966343423376845731003637338524436 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 0.rstmgr_por_stretcher.108410219348757797301343125822173609270114505966343423376845731003637338524436
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.57544516986090938873463982599632584145671936596913565572975036754109016076139
Short name T6
Test name
Test status
Simulation time 1729953098 ps
CPU time 6.69 seconds
Started Nov 22 12:39:17 PM PST 23
Finished Nov 22 12:39:27 PM PST 23
Peak memory 199964 kb
Host smart-c1c59cfa-ba51-455d-928a-495b2f3f8090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57544516986090938873463982599632584145671936596913565572975036754109016076139 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 0.rstmgr_reset.57544516986090938873463982599632584145671936596913565572975036754109016076139
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.96403916427548805180234930970061556193463002863254188766482432534264111131604
Short name T342
Test name
Test status
Simulation time 170065619 ps
CPU time 1.14 seconds
Started Nov 22 12:39:22 PM PST 23
Finished Nov 22 12:39:26 PM PST 23
Peak memory 199876 kb
Host smart-cdd92c7f-b1c9-4dc5-a1f4-2ada809b1b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96403916427548805180234930970061556193463002863254188766482432534264111131604 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.96403916427548805180234930970061556193463002863254188766482432534264111131604
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.90941651806909405572970650649829079103748788330811015310021611942290150477274
Short name T511
Test name
Test status
Simulation time 223941050 ps
CPU time 1.41 seconds
Started Nov 22 12:39:23 PM PST 23
Finished Nov 22 12:39:27 PM PST 23
Peak memory 199896 kb
Host smart-efc4766e-fd44-4cd1-9a76-0466dcac3509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90941651806909405572970650649829079103748788330811015310021611942290150477274 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 0.rstmgr_smoke.90941651806909405572970650649829079103748788330811015310021611942290150477274
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.83369204394184583595191141186340330212417656043654701656873293599644219537571
Short name T540
Test name
Test status
Simulation time 473109710 ps
CPU time 2.66 seconds
Started Nov 22 12:39:34 PM PST 23
Finished Nov 22 12:39:40 PM PST 23
Peak memory 199840 kb
Host smart-c6589537-6fc3-4116-8a66-082ac6ee154f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83369204394184583595191141186340330212417656043654701656873293599644219537571 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 0.rstmgr_sw_rst.83369204394184583595191141186340330212417656043654701656873293599644219537571
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.24684471796729368225052228268548207887105587378754087396630578738138882844583
Short name T289
Test name
Test status
Simulation time 241232855 ps
CPU time 1.48 seconds
Started Nov 22 12:39:23 PM PST 23
Finished Nov 22 12:39:27 PM PST 23
Peak memory 199780 kb
Host smart-db90ec1b-b614-449a-bce8-02010519eab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24684471796729368225052228268548207887105587378754087396630578738138882844583 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.rstmgr_sw_rst_reset_race.24684471796729368225052228268548207887105587378754087396630578738138882844583
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.97016625666656612148742811956276418650710332032944607228117814046008697763688
Short name T500
Test name
Test status
Simulation time 78981557 ps
CPU time 0.83 seconds
Started Nov 22 12:39:43 PM PST 23
Finished Nov 22 12:39:47 PM PST 23
Peak memory 199684 kb
Host smart-e5cc649f-b2a8-4f68-b3a5-746185c9f9f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97016625666656612148742811956276418650710332032944607228117814046008697763688 -assert nopostpr
oc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.97016625666656612148742811956276418650710332032944607228117814046008697763688
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.45355392272902914086162731248676988690705176965103525700807042807799821354762
Short name T432
Test name
Test status
Simulation time 2162831562 ps
CPU time 8.33 seconds
Started Nov 22 12:39:30 PM PST 23
Finished Nov 22 12:39:42 PM PST 23
Peak memory 217004 kb
Host smart-2bc35e08-5482-42c6-8999-5b223aa89bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45355392272902914086162731248676988690705176965103525700807042807799821354762 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 1.rstmgr_leaf_rst_cnsty.45355392272902914086162731248676988690705176965103525700807042807799821354762
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.58204113394909755842252215881471945415004739925381406081088969988620660201671
Short name T581
Test name
Test status
Simulation time 243816210 ps
CPU time 1.06 seconds
Started Nov 22 12:39:35 PM PST 23
Finished Nov 22 12:39:40 PM PST 23
Peak memory 216860 kb
Host smart-1de34466-c7d1-48ad-ac55-66d7b21663ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58204113394909755842252215881471945415004739925381406081088969988620660201671 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.58204113394909755842252215881471945415004739925381406081088969988620660201671
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.16566105205035995351424061135234389528124805614607611610367650013231591553371
Short name T120
Test name
Test status
Simulation time 230357768 ps
CPU time 0.92 seconds
Started Nov 22 12:39:54 PM PST 23
Finished Nov 22 12:39:57 PM PST 23
Peak memory 199700 kb
Host smart-8f647828-64cb-40b7-916a-2fa4a47b3f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16566105205035995351424061135234389528124805614607611610367650013231591553371 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.rstmgr_por_stretcher.16566105205035995351424061135234389528124805614607611610367650013231591553371
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.114201596732763861449967833530325204203437818530571433165344824780888158091401
Short name T110
Test name
Test status
Simulation time 1729953098 ps
CPU time 6.75 seconds
Started Nov 22 12:39:30 PM PST 23
Finished Nov 22 12:39:40 PM PST 23
Peak memory 199940 kb
Host smart-dc0dfc5a-3f04-4d31-82a8-977f32156791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114201596732763861449967833530325204203437818530571433165344824780888158091401 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 1.rstmgr_reset.114201596732763861449967833530325204203437818530571433165344824780888158091401
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.93535033919247477074950147999571644178107714193021604410248789489574906816901
Short name T58
Test name
Test status
Simulation time 8294713949 ps
CPU time 13.95 seconds
Started Nov 22 12:39:52 PM PST 23
Finished Nov 22 12:40:06 PM PST 23
Peak memory 216664 kb
Host smart-98ca9a99-a7f7-4eba-b057-b947697558c9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93535033919247477074950147999571644178107714193021604410248789489574906816901 -assert nopostpro
c +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.93535033919247477074950147999571644178107714193021604410248789489574906816901
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.51696255506194655236527821771775916068111646084084139835503267290897394117577
Short name T421
Test name
Test status
Simulation time 170065619 ps
CPU time 1.15 seconds
Started Nov 22 12:39:40 PM PST 23
Finished Nov 22 12:39:45 PM PST 23
Peak memory 199792 kb
Host smart-ca24c940-ed11-43b8-a015-8e911d308473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51696255506194655236527821771775916068111646084084139835503267290897394117577 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.51696255506194655236527821771775916068111646084084139835503267290897394117577
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.49121008376591148059894896411703284525185829275059258547003013893346100849981
Short name T93
Test name
Test status
Simulation time 223941050 ps
CPU time 1.43 seconds
Started Nov 22 12:39:32 PM PST 23
Finished Nov 22 12:39:36 PM PST 23
Peak memory 199936 kb
Host smart-ee90af22-8dca-4ee8-bcb0-284e0bd2cf76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49121008376591148059894896411703284525185829275059258547003013893346100849981 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 1.rstmgr_smoke.49121008376591148059894896411703284525185829275059258547003013893346100849981
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.56453629334989497754935732736331953347274954753255539440150492493764189565376
Short name T448
Test name
Test status
Simulation time 11131278308 ps
CPU time 39.34 seconds
Started Nov 22 12:39:30 PM PST 23
Finished Nov 22 12:40:13 PM PST 23
Peak memory 200088 kb
Host smart-55ded25f-7105-47c9-8eef-cc065992dd70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56453629334989497754935732736331953347274954753255539440150492493764189565376 -assert nopos
tproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.56453629334989497754935732736331953347274954753255539440150492493764189565376
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.113575889446117574778013508055948256205644627560168982511476835397897778482183
Short name T275
Test name
Test status
Simulation time 473109710 ps
CPU time 2.84 seconds
Started Nov 22 12:39:36 PM PST 23
Finished Nov 22 12:39:44 PM PST 23
Peak memory 199856 kb
Host smart-67808105-9a3c-46f8-a70a-1fcdd140c7c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113575889446117574778013508055948256205644627560168982511476835397897778482183 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.rstmgr_sw_rst.113575889446117574778013508055948256205644627560168982511476835397897778482183
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.96929755520541485209205181594602227463878446541591033754303010215676718971094
Short name T323
Test name
Test status
Simulation time 241232855 ps
CPU time 1.43 seconds
Started Nov 22 12:39:37 PM PST 23
Finished Nov 22 12:39:43 PM PST 23
Peak memory 199740 kb
Host smart-ba7de884-83a6-4561-9338-b60b89319d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96929755520541485209205181594602227463878446541591033754303010215676718971094 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.rstmgr_sw_rst_reset_race.96929755520541485209205181594602227463878446541591033754303010215676718971094
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.51728837776931442300918331881120357569965909645092420443568290518111960568504
Short name T337
Test name
Test status
Simulation time 78981557 ps
CPU time 0.77 seconds
Started Nov 22 12:40:08 PM PST 23
Finished Nov 22 12:40:11 PM PST 23
Peak memory 199696 kb
Host smart-3b7bca45-1772-4ea9-a3be-10a58c5a6a23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51728837776931442300918331881120357569965909645092420443568290518111960568504 -assert nopostpr
oc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.51728837776931442300918331881120357569965909645092420443568290518111960568504
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.33125378726083691758632772768005312828048092051705831388211047440437028876898
Short name T558
Test name
Test status
Simulation time 2162831562 ps
CPU time 7.93 seconds
Started Nov 22 12:40:38 PM PST 23
Finished Nov 22 12:40:49 PM PST 23
Peak memory 215532 kb
Host smart-b864f565-2066-45e6-a556-b2b11b1e8fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33125378726083691758632772768005312828048092051705831388211047440437028876898 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 10.rstmgr_leaf_rst_cnsty.33125378726083691758632772768005312828048092051705831388211047440437028876898
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.1762563296427356243090237305274303613473010365380368837141936023971038687299
Short name T137
Test name
Test status
Simulation time 243816210 ps
CPU time 1.06 seconds
Started Nov 22 12:39:56 PM PST 23
Finished Nov 22 12:39:58 PM PST 23
Peak memory 216760 kb
Host smart-d50a5d00-343f-4de0-bc79-aa14bb33d582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762563296427356243090237305274303613473010365380368837141936023971038687299 -assert nopostproc +UVM_TESTNAME=rstmgr_bas
e_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.1762563296427356243090237305274303613473010365380368837141936023971038687299
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_reset.80752385513408173611837531285882602650556469467193398437463085248791880642431
Short name T320
Test name
Test status
Simulation time 1729953098 ps
CPU time 6.64 seconds
Started Nov 22 12:40:16 PM PST 23
Finished Nov 22 12:40:24 PM PST 23
Peak memory 200076 kb
Host smart-6b40b03f-1e1d-4e8b-baf5-9349800feb52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80752385513408173611837531285882602650556469467193398437463085248791880642431 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 10.rstmgr_reset.80752385513408173611837531285882602650556469467193398437463085248791880642431
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.43682170922563153288282198807304325994320635309343679125110758071825008905625
Short name T518
Test name
Test status
Simulation time 170065619 ps
CPU time 1.13 seconds
Started Nov 22 12:40:43 PM PST 23
Finished Nov 22 12:40:45 PM PST 23
Peak memory 199788 kb
Host smart-a8cd9532-6de6-4671-b62f-b08dc44ef63c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43682170922563153288282198807304325994320635309343679125110758071825008905625 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.43682170922563153288282198807304325994320635309343679125110758071825008905625
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.60813826314906144414237858141782045039049570296821875547564800100903746716481
Short name T520
Test name
Test status
Simulation time 223941050 ps
CPU time 1.42 seconds
Started Nov 22 12:40:41 PM PST 23
Finished Nov 22 12:40:44 PM PST 23
Peak memory 199792 kb
Host smart-9df7160a-bd2c-4487-b7d5-8d0c39184c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60813826314906144414237858141782045039049570296821875547564800100903746716481 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 10.rstmgr_smoke.60813826314906144414237858141782045039049570296821875547564800100903746716481
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.20443944383385614247111604610437688798955678797428075131687566349534477978744
Short name T472
Test name
Test status
Simulation time 11131278308 ps
CPU time 39.27 seconds
Started Nov 22 12:39:50 PM PST 23
Finished Nov 22 12:40:30 PM PST 23
Peak memory 199936 kb
Host smart-435375d4-bea0-49ce-acaa-0ebcd590ffae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20443944383385614247111604610437688798955678797428075131687566349534477978744 -assert nopos
tproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.20443944383385614247111604610437688798955678797428075131687566349534477978744
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.54293783840994138198511945949359363828999812844116665979538202339277514457428
Short name T241
Test name
Test status
Simulation time 473109710 ps
CPU time 2.68 seconds
Started Nov 22 12:40:39 PM PST 23
Finished Nov 22 12:40:43 PM PST 23
Peak memory 199264 kb
Host smart-4e2ba813-f41d-4321-aa39-a8a05a0910bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54293783840994138198511945949359363828999812844116665979538202339277514457428 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 10.rstmgr_sw_rst.54293783840994138198511945949359363828999812844116665979538202339277514457428
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.98311694118170242217045771982186518936024968987475362817606930178877053151466
Short name T265
Test name
Test status
Simulation time 241232855 ps
CPU time 1.39 seconds
Started Nov 22 12:40:02 PM PST 23
Finished Nov 22 12:40:05 PM PST 23
Peak memory 199888 kb
Host smart-ba3b9460-ef5c-40e2-b8b3-96791c35b497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98311694118170242217045771982186518936024968987475362817606930178877053151466 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.rstmgr_sw_rst_reset_race.98311694118170242217045771982186518936024968987475362817606930178877053151466
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.19101435050568885771622972100030598284257349960575222773323721528358357980663
Short name T538
Test name
Test status
Simulation time 78981557 ps
CPU time 0.76 seconds
Started Nov 22 12:40:05 PM PST 23
Finished Nov 22 12:40:08 PM PST 23
Peak memory 199552 kb
Host smart-8d047201-9eb1-49a3-801c-108ef9200f49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19101435050568885771622972100030598284257349960575222773323721528358357980663 -assert nopostpr
oc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.19101435050568885771622972100030598284257349960575222773323721528358357980663
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.66293197883302437875710049987196765749086429261444732010885417685019208110222
Short name T485
Test name
Test status
Simulation time 2162831562 ps
CPU time 8.55 seconds
Started Nov 22 12:40:05 PM PST 23
Finished Nov 22 12:40:16 PM PST 23
Peak memory 217076 kb
Host smart-c5d5a84f-c0e1-43ce-911d-904bc4d8617e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66293197883302437875710049987196765749086429261444732010885417685019208110222 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 11.rstmgr_leaf_rst_cnsty.66293197883302437875710049987196765749086429261444732010885417685019208110222
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.103887309057650878560192118145885904167558992330917880307943959285282524318270
Short name T455
Test name
Test status
Simulation time 243816210 ps
CPU time 1.09 seconds
Started Nov 22 12:40:04 PM PST 23
Finished Nov 22 12:40:08 PM PST 23
Peak memory 216848 kb
Host smart-80905f0e-588b-43b3-9022-68f46c93a9ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103887309057650878560192118145885904167558992330917880307943959285282524318270 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.103887309057650878560192118145885904167558992330917880307943959285282524318270
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.112867224200080885692425803739186661600737978244708055027781031724295711301853
Short name T354
Test name
Test status
Simulation time 230357768 ps
CPU time 0.92 seconds
Started Nov 22 12:39:58 PM PST 23
Finished Nov 22 12:40:00 PM PST 23
Peak memory 199572 kb
Host smart-5cc12946-3562-4a99-9865-2f0b56f6467b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112867224200080885692425803739186661600737978244708055027781031724295711301853 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 11.rstmgr_por_stretcher.112867224200080885692425803739186661600737978244708055027781031724295711301853
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.80777474358538502953881218095996000792306629597734359089962632330551609500943
Short name T43
Test name
Test status
Simulation time 1729953098 ps
CPU time 6.57 seconds
Started Nov 22 12:39:55 PM PST 23
Finished Nov 22 12:40:03 PM PST 23
Peak memory 200132 kb
Host smart-bd7f5426-072b-484a-a06d-1535d6e7ad1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80777474358538502953881218095996000792306629597734359089962632330551609500943 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 11.rstmgr_reset.80777474358538502953881218095996000792306629597734359089962632330551609500943
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.76853844727492542845229893170437756807891853182062722650360355201658870279979
Short name T554
Test name
Test status
Simulation time 170065619 ps
CPU time 1.15 seconds
Started Nov 22 12:40:15 PM PST 23
Finished Nov 22 12:40:19 PM PST 23
Peak memory 199720 kb
Host smart-37fbe0c6-9251-4718-ba41-ca4b71224451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76853844727492542845229893170437756807891853182062722650360355201658870279979 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.76853844727492542845229893170437756807891853182062722650360355201658870279979
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.22074092735520337411153612168330775856310065805105536736674694800594637405316
Short name T492
Test name
Test status
Simulation time 223941050 ps
CPU time 1.43 seconds
Started Nov 22 12:39:54 PM PST 23
Finished Nov 22 12:39:57 PM PST 23
Peak memory 199908 kb
Host smart-6c283180-1026-4037-998e-5842ef0b158b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22074092735520337411153612168330775856310065805105536736674694800594637405316 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 11.rstmgr_smoke.22074092735520337411153612168330775856310065805105536736674694800594637405316
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.34948653612929868353026086656057850494198305392598271439321054729477334232825
Short name T259
Test name
Test status
Simulation time 11131278308 ps
CPU time 39.34 seconds
Started Nov 22 12:40:04 PM PST 23
Finished Nov 22 12:40:45 PM PST 23
Peak memory 200088 kb
Host smart-93411855-a6f5-4599-b3d6-a4bbfbbc73e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34948653612929868353026086656057850494198305392598271439321054729477334232825 -assert nopos
tproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.34948653612929868353026086656057850494198305392598271439321054729477334232825
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.78552611985803000192026012605758697491102383359955583746511527685119283930531
Short name T328
Test name
Test status
Simulation time 473109710 ps
CPU time 2.7 seconds
Started Nov 22 12:40:02 PM PST 23
Finished Nov 22 12:40:06 PM PST 23
Peak memory 199848 kb
Host smart-7b8721ac-c44c-46eb-8aa7-26f22f0c8658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78552611985803000192026012605758697491102383359955583746511527685119283930531 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 11.rstmgr_sw_rst.78552611985803000192026012605758697491102383359955583746511527685119283930531
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.48541516647498076503761331668069256807322188390672899585076147227366435226171
Short name T615
Test name
Test status
Simulation time 241232855 ps
CPU time 1.4 seconds
Started Nov 22 12:40:05 PM PST 23
Finished Nov 22 12:40:09 PM PST 23
Peak memory 199736 kb
Host smart-e07dcd9b-dfbf-4cea-b6c2-8f3fe506a5ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48541516647498076503761331668069256807322188390672899585076147227366435226171 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.rstmgr_sw_rst_reset_race.48541516647498076503761331668069256807322188390672899585076147227366435226171
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.96675745820901031926983531780582029851226278559285293192769231389985732887250
Short name T138
Test name
Test status
Simulation time 78981557 ps
CPU time 0.79 seconds
Started Nov 22 12:40:07 PM PST 23
Finished Nov 22 12:40:10 PM PST 23
Peak memory 199560 kb
Host smart-5d8a9797-67bb-4b51-b4d5-cf4628bbc32d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96675745820901031926983531780582029851226278559285293192769231389985732887250 -assert nopostpr
oc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.96675745820901031926983531780582029851226278559285293192769231389985732887250
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.103321603082983923021556414576029909975207085032434895168069873373030253209150
Short name T549
Test name
Test status
Simulation time 243816210 ps
CPU time 1.07 seconds
Started Nov 22 12:40:06 PM PST 23
Finished Nov 22 12:40:10 PM PST 23
Peak memory 216864 kb
Host smart-0f1a8f2a-5349-4dfe-be9a-c9681670ecb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103321603082983923021556414576029909975207085032434895168069873373030253209150 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.103321603082983923021556414576029909975207085032434895168069873373030253209150
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.82284276287674888008768273434385479803095135308100181721603610406032500135737
Short name T365
Test name
Test status
Simulation time 230357768 ps
CPU time 0.92 seconds
Started Nov 22 12:40:10 PM PST 23
Finished Nov 22 12:40:12 PM PST 23
Peak memory 199696 kb
Host smart-b9d1329f-6494-4482-a448-ab19d4090e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82284276287674888008768273434385479803095135308100181721603610406032500135737 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.rstmgr_por_stretcher.82284276287674888008768273434385479803095135308100181721603610406032500135737
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.52297754771634053075079750683086115798869558878439873651963715099001698242457
Short name T118
Test name
Test status
Simulation time 1729953098 ps
CPU time 6.32 seconds
Started Nov 22 12:40:06 PM PST 23
Finished Nov 22 12:40:16 PM PST 23
Peak memory 200096 kb
Host smart-0aed02f8-8f7c-4938-a795-86293d6addaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52297754771634053075079750683086115798869558878439873651963715099001698242457 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 12.rstmgr_reset.52297754771634053075079750683086115798869558878439873651963715099001698242457
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.43955826858134291164714412089989264959470824765097600330551504815282287493253
Short name T494
Test name
Test status
Simulation time 170065619 ps
CPU time 1.18 seconds
Started Nov 22 12:40:06 PM PST 23
Finished Nov 22 12:40:10 PM PST 23
Peak memory 199852 kb
Host smart-5a937d7f-5f7f-4de4-a0c9-7ccbf91b4d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43955826858134291164714412089989264959470824765097600330551504815282287493253 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.43955826858134291164714412089989264959470824765097600330551504815282287493253
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.23955898362661194185604849446079144236215606821509352460267963038318398959106
Short name T588
Test name
Test status
Simulation time 223941050 ps
CPU time 1.46 seconds
Started Nov 22 12:40:13 PM PST 23
Finished Nov 22 12:40:16 PM PST 23
Peak memory 199944 kb
Host smart-e1922d85-665c-4a49-bd3e-f8703b962179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23955898362661194185604849446079144236215606821509352460267963038318398959106 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 12.rstmgr_smoke.23955898362661194185604849446079144236215606821509352460267963038318398959106
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.31526210335838355075638857741828872311265943318752737158455285911314975388324
Short name T583
Test name
Test status
Simulation time 11131278308 ps
CPU time 39.43 seconds
Started Nov 22 12:40:07 PM PST 23
Finished Nov 22 12:40:49 PM PST 23
Peak memory 199996 kb
Host smart-d8c0d2c3-ba4e-40af-88c9-4a5981bb3e31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31526210335838355075638857741828872311265943318752737158455285911314975388324 -assert nopos
tproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.31526210335838355075638857741828872311265943318752737158455285911314975388324
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.41201856752212566392299153953253145454904268864733182575468594891361792379077
Short name T582
Test name
Test status
Simulation time 473109710 ps
CPU time 2.7 seconds
Started Nov 22 12:40:06 PM PST 23
Finished Nov 22 12:40:12 PM PST 23
Peak memory 199864 kb
Host smart-e5c1ed75-51b5-4564-9ccd-df35a10f71fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41201856752212566392299153953253145454904268864733182575468594891361792379077 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 12.rstmgr_sw_rst.41201856752212566392299153953253145454904268864733182575468594891361792379077
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.29552397737337530540491561511006502639788365077757829625672007384868073484160
Short name T333
Test name
Test status
Simulation time 241232855 ps
CPU time 1.42 seconds
Started Nov 22 12:40:12 PM PST 23
Finished Nov 22 12:40:15 PM PST 23
Peak memory 199884 kb
Host smart-0bffc0d9-cb45-4a78-957c-24d9ff0137fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29552397737337530540491561511006502639788365077757829625672007384868073484160 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.rstmgr_sw_rst_reset_race.29552397737337530540491561511006502639788365077757829625672007384868073484160
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.109710621729135951957959099735372919742792361195102559007195244532200004822154
Short name T129
Test name
Test status
Simulation time 78981557 ps
CPU time 0.79 seconds
Started Nov 22 12:40:05 PM PST 23
Finished Nov 22 12:40:08 PM PST 23
Peak memory 199552 kb
Host smart-7bee5927-d38b-47d2-824e-40bfe838875a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109710621729135951957959099735372919742792361195102559007195244532200004822154 -assert nopostp
roc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.109710621729135951957959099735372919742792361195102559007195244532200004822154
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.35646467412766136179122547309182212439654348321100624121133975892810777359903
Short name T33
Test name
Test status
Simulation time 2162831562 ps
CPU time 8.24 seconds
Started Nov 22 12:40:06 PM PST 23
Finished Nov 22 12:40:17 PM PST 23
Peak memory 217104 kb
Host smart-8cd486cd-86a6-4712-a2f0-15a3e78133ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35646467412766136179122547309182212439654348321100624121133975892810777359903 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 13.rstmgr_leaf_rst_cnsty.35646467412766136179122547309182212439654348321100624121133975892810777359903
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.34788898218227314764058279096078038173879164300107343552715099386431516310100
Short name T422
Test name
Test status
Simulation time 243816210 ps
CPU time 1.05 seconds
Started Nov 22 12:40:12 PM PST 23
Finished Nov 22 12:40:15 PM PST 23
Peak memory 216844 kb
Host smart-e7070eb8-03f1-41a9-ac82-3e2c0705ea7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34788898218227314764058279096078038173879164300107343552715099386431516310100 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.34788898218227314764058279096078038173879164300107343552715099386431516310100
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.65498693362930031329525129201801857152659267396749460519577042603722985340355
Short name T21
Test name
Test status
Simulation time 230357768 ps
CPU time 0.98 seconds
Started Nov 22 12:40:04 PM PST 23
Finished Nov 22 12:40:07 PM PST 23
Peak memory 199592 kb
Host smart-361e5338-2026-4cb1-9bca-76a20351298a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65498693362930031329525129201801857152659267396749460519577042603722985340355 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.rstmgr_por_stretcher.65498693362930031329525129201801857152659267396749460519577042603722985340355
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.46040646885239147419414152686248024124930040555117793612661864419786979561533
Short name T516
Test name
Test status
Simulation time 1729953098 ps
CPU time 6.93 seconds
Started Nov 22 12:40:06 PM PST 23
Finished Nov 22 12:40:16 PM PST 23
Peak memory 200072 kb
Host smart-6cc2ab46-ad77-45a8-8ab2-94c5b9e74a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46040646885239147419414152686248024124930040555117793612661864419786979561533 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 13.rstmgr_reset.46040646885239147419414152686248024124930040555117793612661864419786979561533
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.82953538374604109015845870299699381030431902596773818414727789108083318146065
Short name T594
Test name
Test status
Simulation time 170065619 ps
CPU time 1.24 seconds
Started Nov 22 12:40:05 PM PST 23
Finished Nov 22 12:40:08 PM PST 23
Peak memory 199868 kb
Host smart-ec6a778c-5d11-44c2-96d5-4c110f081e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82953538374604109015845870299699381030431902596773818414727789108083318146065 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.82953538374604109015845870299699381030431902596773818414727789108083318146065
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.65386374644631338303685633046617034665621801590116834631093714796420705327329
Short name T3
Test name
Test status
Simulation time 223941050 ps
CPU time 1.39 seconds
Started Nov 22 12:40:12 PM PST 23
Finished Nov 22 12:40:15 PM PST 23
Peak memory 199888 kb
Host smart-b848e10a-d570-4c0c-b43f-09f4d4729bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65386374644631338303685633046617034665621801590116834631093714796420705327329 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 13.rstmgr_smoke.65386374644631338303685633046617034665621801590116834631093714796420705327329
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.57901744164270686096015646721738247687590130181399142239115290902960859932077
Short name T460
Test name
Test status
Simulation time 11131278308 ps
CPU time 39.55 seconds
Started Nov 22 12:40:05 PM PST 23
Finished Nov 22 12:40:47 PM PST 23
Peak memory 199952 kb
Host smart-101d7bd9-da20-47b9-a055-8cb32e6aa91c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57901744164270686096015646721738247687590130181399142239115290902960859932077 -assert nopos
tproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.57901744164270686096015646721738247687590130181399142239115290902960859932077
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.24144050798516443162830552836497565354542352136295515325721755006677957213606
Short name T522
Test name
Test status
Simulation time 473109710 ps
CPU time 2.73 seconds
Started Nov 22 12:40:06 PM PST 23
Finished Nov 22 12:40:11 PM PST 23
Peak memory 199812 kb
Host smart-2e41e731-107f-4a13-bcd4-355e2a06cbb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24144050798516443162830552836497565354542352136295515325721755006677957213606 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 13.rstmgr_sw_rst.24144050798516443162830552836497565354542352136295515325721755006677957213606
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.61022032970522489698818427680282495083459812918003605003277394418919085700476
Short name T620
Test name
Test status
Simulation time 241232855 ps
CPU time 1.41 seconds
Started Nov 22 12:40:07 PM PST 23
Finished Nov 22 12:40:11 PM PST 23
Peak memory 199908 kb
Host smart-b180bdc6-276a-4ad2-8f92-daae825b645f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61022032970522489698818427680282495083459812918003605003277394418919085700476 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 13.rstmgr_sw_rst_reset_race.61022032970522489698818427680282495083459812918003605003277394418919085700476
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.52731214313555141495293882151035986216972028252479067935169485791181090072505
Short name T579
Test name
Test status
Simulation time 2162831562 ps
CPU time 7.62 seconds
Started Nov 22 12:40:07 PM PST 23
Finished Nov 22 12:40:17 PM PST 23
Peak memory 217012 kb
Host smart-a59d62f5-a797-4a77-85fb-9096d6b725c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52731214313555141495293882151035986216972028252479067935169485791181090072505 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 14.rstmgr_leaf_rst_cnsty.52731214313555141495293882151035986216972028252479067935169485791181090072505
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.33842081993391374281463933048090356378830028441659115034567528873688066800073
Short name T115
Test name
Test status
Simulation time 243816210 ps
CPU time 1.13 seconds
Started Nov 22 12:40:04 PM PST 23
Finished Nov 22 12:40:07 PM PST 23
Peak memory 216860 kb
Host smart-f120224e-1d63-4d9e-b92d-fd4afd5b4a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33842081993391374281463933048090356378830028441659115034567528873688066800073 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.33842081993391374281463933048090356378830028441659115034567528873688066800073
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.46260044349264155316256825380935555753519428983795352736392519532091024667460
Short name T22
Test name
Test status
Simulation time 230357768 ps
CPU time 0.94 seconds
Started Nov 22 12:40:01 PM PST 23
Finished Nov 22 12:40:04 PM PST 23
Peak memory 199548 kb
Host smart-2887e9f6-df41-41a2-a6c8-3379b67ddea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46260044349264155316256825380935555753519428983795352736392519532091024667460 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.rstmgr_por_stretcher.46260044349264155316256825380935555753519428983795352736392519532091024667460
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.82084029849297856513735138986559644321590999574051408617339656462534583477532
Short name T389
Test name
Test status
Simulation time 1729953098 ps
CPU time 6.43 seconds
Started Nov 22 12:40:04 PM PST 23
Finished Nov 22 12:40:13 PM PST 23
Peak memory 199948 kb
Host smart-a8e870e8-abb8-49e6-b15d-012e73f4b3f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82084029849297856513735138986559644321590999574051408617339656462534583477532 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 14.rstmgr_reset.82084029849297856513735138986559644321590999574051408617339656462534583477532
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.65829763397375566229709285228948700345238035510755364451877759678550380238266
Short name T519
Test name
Test status
Simulation time 170065619 ps
CPU time 1.13 seconds
Started Nov 22 12:40:11 PM PST 23
Finished Nov 22 12:40:14 PM PST 23
Peak memory 199780 kb
Host smart-ac29652a-cc85-4d34-a6fe-f2e2abcfb02d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65829763397375566229709285228948700345238035510755364451877759678550380238266 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.65829763397375566229709285228948700345238035510755364451877759678550380238266
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.6791319478969539184356705251376761073547111209896326812118232341970870578693
Short name T466
Test name
Test status
Simulation time 223941050 ps
CPU time 1.38 seconds
Started Nov 22 12:40:01 PM PST 23
Finished Nov 22 12:40:04 PM PST 23
Peak memory 200004 kb
Host smart-1d3669e8-7f24-4755-8a5b-27cac6555d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6791319478969539184356705251376761073547111209896326812118232341970870578693 -assert nopostproc +UVM_TESTNAME=rstmgr_bas
e_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rstmgr_smoke.6791319478969539184356705251376761073547111209896326812118232341970870578693
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.21485454469556190411145753477573282242923191629973949273508810500766763143327
Short name T567
Test name
Test status
Simulation time 11131278308 ps
CPU time 38.47 seconds
Started Nov 22 12:40:09 PM PST 23
Finished Nov 22 12:40:49 PM PST 23
Peak memory 200120 kb
Host smart-1a90c29d-647c-4400-9cbf-cd1a8313b07e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21485454469556190411145753477573282242923191629973949273508810500766763143327 -assert nopos
tproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.21485454469556190411145753477573282242923191629973949273508810500766763143327
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.36018250281322508554838596042354393381932118063736263739059045316962921307602
Short name T66
Test name
Test status
Simulation time 473109710 ps
CPU time 2.72 seconds
Started Nov 22 12:40:05 PM PST 23
Finished Nov 22 12:40:10 PM PST 23
Peak memory 199708 kb
Host smart-b1706b10-0f5c-4c3f-8404-86f148efc8a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36018250281322508554838596042354393381932118063736263739059045316962921307602 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 14.rstmgr_sw_rst.36018250281322508554838596042354393381932118063736263739059045316962921307602
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.12885234648649078562627599727399293301704293261553093925222724907302742302966
Short name T277
Test name
Test status
Simulation time 241232855 ps
CPU time 1.6 seconds
Started Nov 22 12:40:05 PM PST 23
Finished Nov 22 12:40:09 PM PST 23
Peak memory 199888 kb
Host smart-dee24f91-9ff1-4d5a-becf-26b710e80be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12885234648649078562627599727399293301704293261553093925222724907302742302966 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 14.rstmgr_sw_rst_reset_race.12885234648649078562627599727399293301704293261553093925222724907302742302966
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.29201173804317581238548211262535663749860843140077719429705906436471088305090
Short name T388
Test name
Test status
Simulation time 78981557 ps
CPU time 0.76 seconds
Started Nov 22 12:40:09 PM PST 23
Finished Nov 22 12:40:12 PM PST 23
Peak memory 199560 kb
Host smart-f063142d-f8d0-4d16-b184-4ab18f08e265
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29201173804317581238548211262535663749860843140077719429705906436471088305090 -assert nopostpr
oc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.29201173804317581238548211262535663749860843140077719429705906436471088305090
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.22977845350393667110668713189404750854974499983765547046228771437718057137858
Short name T334
Test name
Test status
Simulation time 2162831562 ps
CPU time 7.82 seconds
Started Nov 22 12:40:10 PM PST 23
Finished Nov 22 12:40:19 PM PST 23
Peak memory 216992 kb
Host smart-6e0639e1-8923-4bca-9ae7-9a8d36308e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22977845350393667110668713189404750854974499983765547046228771437718057137858 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 15.rstmgr_leaf_rst_cnsty.22977845350393667110668713189404750854974499983765547046228771437718057137858
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.16586905063543514850711610032367938032471523257980600632550868657531060507953
Short name T357
Test name
Test status
Simulation time 243816210 ps
CPU time 1.08 seconds
Started Nov 22 12:40:10 PM PST 23
Finished Nov 22 12:40:18 PM PST 23
Peak memory 216836 kb
Host smart-134875e5-fa23-4813-8bac-5f710259b83e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16586905063543514850711610032367938032471523257980600632550868657531060507953 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.16586905063543514850711610032367938032471523257980600632550868657531060507953
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.103555586384852046822477301040447938523378971259235349574890254040492467869467
Short name T249
Test name
Test status
Simulation time 230357768 ps
CPU time 0.91 seconds
Started Nov 22 12:40:13 PM PST 23
Finished Nov 22 12:40:15 PM PST 23
Peak memory 199652 kb
Host smart-8787ea81-75cc-44fa-8f66-554e359ff49d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103555586384852046822477301040447938523378971259235349574890254040492467869467 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 15.rstmgr_por_stretcher.103555586384852046822477301040447938523378971259235349574890254040492467869467
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.54246891653876255377938315804642345134193017699767060384394152966781721694354
Short name T283
Test name
Test status
Simulation time 1729953098 ps
CPU time 6.7 seconds
Started Nov 22 12:40:04 PM PST 23
Finished Nov 22 12:40:13 PM PST 23
Peak memory 199964 kb
Host smart-482909ae-df59-4e98-83f4-3b4f4b5be7db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54246891653876255377938315804642345134193017699767060384394152966781721694354 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 15.rstmgr_reset.54246891653876255377938315804642345134193017699767060384394152966781721694354
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.91819857790627606935552638001613554728698088881092115477236800081397887976360
Short name T614
Test name
Test status
Simulation time 170065619 ps
CPU time 1.23 seconds
Started Nov 22 12:40:04 PM PST 23
Finished Nov 22 12:40:08 PM PST 23
Peak memory 199848 kb
Host smart-535bdcba-f826-4266-91b7-414f2386d4db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91819857790627606935552638001613554728698088881092115477236800081397887976360 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.91819857790627606935552638001613554728698088881092115477236800081397887976360
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.109073064451611188863999464030069684394799378973984831233224662604345336675442
Short name T112
Test name
Test status
Simulation time 223941050 ps
CPU time 1.41 seconds
Started Nov 22 12:40:06 PM PST 23
Finished Nov 22 12:40:10 PM PST 23
Peak memory 200040 kb
Host smart-29789da3-9357-407e-b22c-b1d4be45c595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109073064451611188863999464030069684394799378973984831233224662604345336675442 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 15.rstmgr_smoke.109073064451611188863999464030069684394799378973984831233224662604345336675442
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.115547073271057667091290996213134570543388445701319002427608775242563619802755
Short name T428
Test name
Test status
Simulation time 11131278308 ps
CPU time 39.15 seconds
Started Nov 22 12:40:10 PM PST 23
Finished Nov 22 12:40:51 PM PST 23
Peak memory 199960 kb
Host smart-b4030f56-9e7a-4a9d-9255-24f8f522df67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115547073271057667091290996213134570543388445701319002427608775242563619802755 -assert nopo
stproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.115547073271057667091290996213134570543388445701319002427608775242563619802755
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.84856888212372350755110525284860741888577025401132486245262019497089142651892
Short name T296
Test name
Test status
Simulation time 473109710 ps
CPU time 2.62 seconds
Started Nov 22 12:40:13 PM PST 23
Finished Nov 22 12:40:17 PM PST 23
Peak memory 199852 kb
Host smart-4aaa04c5-a9c2-48c2-bef0-fcbd3e11e076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84856888212372350755110525284860741888577025401132486245262019497089142651892 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 15.rstmgr_sw_rst.84856888212372350755110525284860741888577025401132486245262019497089142651892
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.69841244158859681764067094236551166055795985491575857066172462371736215549453
Short name T403
Test name
Test status
Simulation time 78981557 ps
CPU time 0.78 seconds
Started Nov 22 12:40:17 PM PST 23
Finished Nov 22 12:40:20 PM PST 23
Peak memory 199512 kb
Host smart-2a22f7bc-a26d-4195-b01a-db7f86585e1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69841244158859681764067094236551166055795985491575857066172462371736215549453 -assert nopostpr
oc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.69841244158859681764067094236551166055795985491575857066172462371736215549453
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.98314564983482783214466507138943191233909528518897757281551484483437261754426
Short name T510
Test name
Test status
Simulation time 2162831562 ps
CPU time 8.06 seconds
Started Nov 22 12:40:09 PM PST 23
Finished Nov 22 12:40:19 PM PST 23
Peak memory 216948 kb
Host smart-9f8e5c1c-43c1-4aa9-b259-dc6ae388293e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98314564983482783214466507138943191233909528518897757281551484483437261754426 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 16.rstmgr_leaf_rst_cnsty.98314564983482783214466507138943191233909528518897757281551484483437261754426
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.92287989648700452827687989950145357687139375118517604307178492638602229283151
Short name T238
Test name
Test status
Simulation time 243816210 ps
CPU time 1.14 seconds
Started Nov 22 12:40:17 PM PST 23
Finished Nov 22 12:40:20 PM PST 23
Peak memory 216668 kb
Host smart-771b1798-27a1-47d3-a8d6-ce49416e0d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92287989648700452827687989950145357687139375118517604307178492638602229283151 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.92287989648700452827687989950145357687139375118517604307178492638602229283151
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.108130777670127334131785527155776366972081540771077072414994675635136597490618
Short name T515
Test name
Test status
Simulation time 230357768 ps
CPU time 0.92 seconds
Started Nov 22 12:40:15 PM PST 23
Finished Nov 22 12:40:17 PM PST 23
Peak memory 199684 kb
Host smart-e7d7ec77-328f-4006-bb46-b1cf494ce2e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108130777670127334131785527155776366972081540771077072414994675635136597490618 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 16.rstmgr_por_stretcher.108130777670127334131785527155776366972081540771077072414994675635136597490618
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.109628849509556870319269733476618562947370009361533997448178278801859869708705
Short name T39
Test name
Test status
Simulation time 1729953098 ps
CPU time 6.77 seconds
Started Nov 22 12:40:08 PM PST 23
Finished Nov 22 12:40:17 PM PST 23
Peak memory 199980 kb
Host smart-da938b57-faec-49e0-a2ce-552fce28b660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109628849509556870319269733476618562947370009361533997448178278801859869708705 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 16.rstmgr_reset.109628849509556870319269733476618562947370009361533997448178278801859869708705
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.46510505925900406377330623656850595959563733361928486825582429813512757723394
Short name T436
Test name
Test status
Simulation time 170065619 ps
CPU time 1.16 seconds
Started Nov 22 12:40:05 PM PST 23
Finished Nov 22 12:40:08 PM PST 23
Peak memory 199780 kb
Host smart-67f5ea48-5ce3-4813-89cb-927a78fc5702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46510505925900406377330623656850595959563733361928486825582429813512757723394 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.46510505925900406377330623656850595959563733361928486825582429813512757723394
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.8565097534835669391442953775599177171712762704724065987448446157364744720746
Short name T263
Test name
Test status
Simulation time 223941050 ps
CPU time 1.4 seconds
Started Nov 22 12:40:17 PM PST 23
Finished Nov 22 12:40:20 PM PST 23
Peak memory 199832 kb
Host smart-138a56da-1754-4e68-b197-440ae869ee25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8565097534835669391442953775599177171712762704724065987448446157364744720746 -assert nopostproc +UVM_TESTNAME=rstmgr_bas
e_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rstmgr_smoke.8565097534835669391442953775599177171712762704724065987448446157364744720746
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.91268992362233926256204857024424744740579858493723880201181686882774156776789
Short name T537
Test name
Test status
Simulation time 11131278308 ps
CPU time 39.58 seconds
Started Nov 22 12:40:06 PM PST 23
Finished Nov 22 12:40:49 PM PST 23
Peak memory 199948 kb
Host smart-0e558cd2-56ba-4e8a-be5c-e7d93d47ef6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91268992362233926256204857024424744740579858493723880201181686882774156776789 -assert nopos
tproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.91268992362233926256204857024424744740579858493723880201181686882774156776789
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.53943345125086549152862161346761470497146829410163771729735387666549907875227
Short name T543
Test name
Test status
Simulation time 473109710 ps
CPU time 2.58 seconds
Started Nov 22 12:40:18 PM PST 23
Finished Nov 22 12:40:22 PM PST 23
Peak memory 199840 kb
Host smart-8c2a0af0-9966-4bef-947e-3cac868487d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53943345125086549152862161346761470497146829410163771729735387666549907875227 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 16.rstmgr_sw_rst.53943345125086549152862161346761470497146829410163771729735387666549907875227
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.50685569166814651114755956649197886835415580096462429742528117188777687581845
Short name T473
Test name
Test status
Simulation time 241232855 ps
CPU time 1.45 seconds
Started Nov 22 12:40:07 PM PST 23
Finished Nov 22 12:40:11 PM PST 23
Peak memory 199780 kb
Host smart-8415e860-e117-4ace-a3dc-389e6c6d9a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50685569166814651114755956649197886835415580096462429742528117188777687581845 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.rstmgr_sw_rst_reset_race.50685569166814651114755956649197886835415580096462429742528117188777687581845
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.71671428605355270516480661414129812726409593150468654257277471139322365758554
Short name T40
Test name
Test status
Simulation time 78981557 ps
CPU time 0.79 seconds
Started Nov 22 12:40:09 PM PST 23
Finished Nov 22 12:40:12 PM PST 23
Peak memory 199560 kb
Host smart-8a757e78-2ce4-4be1-943f-81e994f2acac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71671428605355270516480661414129812726409593150468654257277471139322365758554 -assert nopostpr
oc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.71671428605355270516480661414129812726409593150468654257277471139322365758554
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.108966729628164414461124880398711864402514722674624212326757779969166665856479
Short name T31
Test name
Test status
Simulation time 2162831562 ps
CPU time 7.7 seconds
Started Nov 22 12:40:22 PM PST 23
Finished Nov 22 12:40:32 PM PST 23
Peak memory 217016 kb
Host smart-e149e7b3-3ac6-4a53-97d9-827fff15458e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108966729628164414461124880398711864402514722674624212326757779969166665856479 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 17.rstmgr_leaf_rst_cnsty.108966729628164414461124880398711864402514722674624212326757779969166665856479
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.61125200757808880340604631992022512773028215945812804009477562464229191102202
Short name T531
Test name
Test status
Simulation time 243816210 ps
CPU time 1.09 seconds
Started Nov 22 12:40:15 PM PST 23
Finished Nov 22 12:40:18 PM PST 23
Peak memory 216812 kb
Host smart-3a73d6dc-309d-4a27-a118-db275c3caee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61125200757808880340604631992022512773028215945812804009477562464229191102202 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.61125200757808880340604631992022512773028215945812804009477562464229191102202
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.10871436537304139911880216110883438085653763221172821995683074830519772301462
Short name T17
Test name
Test status
Simulation time 230357768 ps
CPU time 0.95 seconds
Started Nov 22 12:40:22 PM PST 23
Finished Nov 22 12:40:25 PM PST 23
Peak memory 199616 kb
Host smart-fbe3c764-664f-47ac-9bcc-40b8f92ccfcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10871436537304139911880216110883438085653763221172821995683074830519772301462 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.rstmgr_por_stretcher.10871436537304139911880216110883438085653763221172821995683074830519772301462
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.9295403534397880539798098289920298075436097690313558333437919965669932009873
Short name T542
Test name
Test status
Simulation time 1729953098 ps
CPU time 6.22 seconds
Started Nov 22 12:40:07 PM PST 23
Finished Nov 22 12:40:16 PM PST 23
Peak memory 199860 kb
Host smart-b650d73d-3db7-46a9-84e9-6f52122674b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9295403534397880539798098289920298075436097690313558333437919965669932009873 -assert nopostproc +UVM_TESTNAME=rstmgr_bas
e_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rstmgr_reset.9295403534397880539798098289920298075436097690313558333437919965669932009873
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.57505234696244497849152761173668532738327566347794369573488069847970545240799
Short name T398
Test name
Test status
Simulation time 170065619 ps
CPU time 1.07 seconds
Started Nov 22 12:40:07 PM PST 23
Finished Nov 22 12:40:11 PM PST 23
Peak memory 199664 kb
Host smart-e90f2a11-4144-4885-af33-5d414a59e7b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57505234696244497849152761173668532738327566347794369573488069847970545240799 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.57505234696244497849152761173668532738327566347794369573488069847970545240799
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.41432309224514477857457688470798466947650359179046771647848459874721180691742
Short name T247
Test name
Test status
Simulation time 223941050 ps
CPU time 1.39 seconds
Started Nov 22 12:40:10 PM PST 23
Finished Nov 22 12:40:13 PM PST 23
Peak memory 199812 kb
Host smart-b16ca426-63f4-4d8f-93d5-aafecf8525c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41432309224514477857457688470798466947650359179046771647848459874721180691742 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 17.rstmgr_smoke.41432309224514477857457688470798466947650359179046771647848459874721180691742
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.3865399569141911164112896793577573823889063445747915176832242890562807838853
Short name T592
Test name
Test status
Simulation time 11131278308 ps
CPU time 39.71 seconds
Started Nov 22 12:40:22 PM PST 23
Finished Nov 22 12:41:04 PM PST 23
Peak memory 199940 kb
Host smart-cd70ce39-4058-4a37-bbe1-55469c3b592b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865399569141911164112896793577573823889063445747915176832242890562807838853 -assert nopost
proc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.3865399569141911164112896793577573823889063445747915176832242890562807838853
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.2705754296780449502288038110785129211788589626132136434689271093487301496305
Short name T453
Test name
Test status
Simulation time 473109710 ps
CPU time 2.6 seconds
Started Nov 22 12:40:21 PM PST 23
Finished Nov 22 12:40:27 PM PST 23
Peak memory 199788 kb
Host smart-3666c6ce-9f89-4606-b1ad-3075d1284acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705754296780449502288038110785129211788589626132136434689271093487301496305 -assert nopostproc +UVM_TESTNAME=rstmgr_bas
e_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 17.rstmgr_sw_rst.2705754296780449502288038110785129211788589626132136434689271093487301496305
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.42058714942664099160078079068600542226052413820021949667927214005186442991702
Short name T512
Test name
Test status
Simulation time 241232855 ps
CPU time 1.55 seconds
Started Nov 22 12:40:22 PM PST 23
Finished Nov 22 12:40:26 PM PST 23
Peak memory 199824 kb
Host smart-4895bea6-a811-4318-970b-f4b4d4771868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42058714942664099160078079068600542226052413820021949667927214005186442991702 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 17.rstmgr_sw_rst_reset_race.42058714942664099160078079068600542226052413820021949667927214005186442991702
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.28456490376512905692254159764613763364897756888068492645321760778698328908468
Short name T339
Test name
Test status
Simulation time 78981557 ps
CPU time 0.82 seconds
Started Nov 22 12:40:22 PM PST 23
Finished Nov 22 12:40:25 PM PST 23
Peak memory 199668 kb
Host smart-daa3caf4-425e-44ae-93cd-f9d96af67825
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28456490376512905692254159764613763364897756888068492645321760778698328908468 -assert nopostpr
oc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.28456490376512905692254159764613763364897756888068492645321760778698328908468
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.30893098372905852542137705679485857479955878591654147878452965026966236955743
Short name T426
Test name
Test status
Simulation time 2162831562 ps
CPU time 7.88 seconds
Started Nov 22 12:40:25 PM PST 23
Finished Nov 22 12:40:35 PM PST 23
Peak memory 217040 kb
Host smart-25072ef6-18e1-4709-b041-d5f6fb33617c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30893098372905852542137705679485857479955878591654147878452965026966236955743 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 18.rstmgr_leaf_rst_cnsty.30893098372905852542137705679485857479955878591654147878452965026966236955743
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.94209888828530481041171523705141083397605173175705322338416651201818387571502
Short name T414
Test name
Test status
Simulation time 243816210 ps
CPU time 1.11 seconds
Started Nov 22 12:40:31 PM PST 23
Finished Nov 22 12:40:34 PM PST 23
Peak memory 216800 kb
Host smart-00fcf594-dbf2-46fe-9143-5c234088ffb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94209888828530481041171523705141083397605173175705322338416651201818387571502 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.94209888828530481041171523705141083397605173175705322338416651201818387571502
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.85488621950268854010260387232746004382032762150659204425669254079729730220804
Short name T556
Test name
Test status
Simulation time 230357768 ps
CPU time 0.96 seconds
Started Nov 22 12:40:05 PM PST 23
Finished Nov 22 12:40:08 PM PST 23
Peak memory 199552 kb
Host smart-120a3220-c1d3-4ea8-b149-216f7b618a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85488621950268854010260387232746004382032762150659204425669254079729730220804 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.rstmgr_por_stretcher.85488621950268854010260387232746004382032762150659204425669254079729730220804
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.79823069227029870119275889474560359736498292653004160130625724882547931589704
Short name T607
Test name
Test status
Simulation time 1729953098 ps
CPU time 6.46 seconds
Started Nov 22 12:40:22 PM PST 23
Finished Nov 22 12:40:31 PM PST 23
Peak memory 199912 kb
Host smart-33509c94-01b4-44b1-b5ad-bac3a79fcb34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79823069227029870119275889474560359736498292653004160130625724882547931589704 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 18.rstmgr_reset.79823069227029870119275889474560359736498292653004160130625724882547931589704
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.1235274168677865047699601659716481862727882486439696993573896630334835344608
Short name T309
Test name
Test status
Simulation time 170065619 ps
CPU time 1.1 seconds
Started Nov 22 12:40:19 PM PST 23
Finished Nov 22 12:40:22 PM PST 23
Peak memory 199740 kb
Host smart-ddb13889-ea75-472d-8b7d-4985b55ecffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235274168677865047699601659716481862727882486439696993573896630334835344608 -assert nopostproc +UVM_TESTNAME=rstmgr_bas
e_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.1235274168677865047699601659716481862727882486439696993573896630334835344608
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.9190125217223380498315275627721168902208075657664237963357859883522883600100
Short name T565
Test name
Test status
Simulation time 223941050 ps
CPU time 1.38 seconds
Started Nov 22 12:40:22 PM PST 23
Finished Nov 22 12:40:25 PM PST 23
Peak memory 199980 kb
Host smart-7e05cdec-82d6-4329-8bec-5b50af333240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9190125217223380498315275627721168902208075657664237963357859883522883600100 -assert nopostproc +UVM_TESTNAME=rstmgr_bas
e_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rstmgr_smoke.9190125217223380498315275627721168902208075657664237963357859883522883600100
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.3651690750252814995984178255145733484024139129452214188437595057556335429735
Short name T610
Test name
Test status
Simulation time 11131278308 ps
CPU time 38.36 seconds
Started Nov 22 12:40:23 PM PST 23
Finished Nov 22 12:41:05 PM PST 23
Peak memory 200088 kb
Host smart-bbd6d2ba-b78f-48ac-9626-639eb938d2fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651690750252814995984178255145733484024139129452214188437595057556335429735 -assert nopost
proc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.3651690750252814995984178255145733484024139129452214188437595057556335429735
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.23727931912520633557587404717330831116901197271624320519549785580159082316158
Short name T317
Test name
Test status
Simulation time 473109710 ps
CPU time 2.56 seconds
Started Nov 22 12:40:26 PM PST 23
Finished Nov 22 12:40:31 PM PST 23
Peak memory 199732 kb
Host smart-b8c53249-a541-4372-8bb4-752a81f65fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23727931912520633557587404717330831116901197271624320519549785580159082316158 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 18.rstmgr_sw_rst.23727931912520633557587404717330831116901197271624320519549785580159082316158
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.96716335710617565415069777895874682444559664056311425879955141538599390513068
Short name T367
Test name
Test status
Simulation time 241232855 ps
CPU time 1.38 seconds
Started Nov 22 12:40:28 PM PST 23
Finished Nov 22 12:40:31 PM PST 23
Peak memory 199852 kb
Host smart-a0537333-462a-4449-8df6-90be0f66002f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96716335710617565415069777895874682444559664056311425879955141538599390513068 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 18.rstmgr_sw_rst_reset_race.96716335710617565415069777895874682444559664056311425879955141538599390513068
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.111152058279617207070182857518645513794793071525544368892438895602506629123069
Short name T318
Test name
Test status
Simulation time 78981557 ps
CPU time 0.83 seconds
Started Nov 22 12:40:22 PM PST 23
Finished Nov 22 12:40:26 PM PST 23
Peak memory 199692 kb
Host smart-04fb026c-6b9e-424b-900a-a9cf64e568b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111152058279617207070182857518645513794793071525544368892438895602506629123069 -assert nopostp
roc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.111152058279617207070182857518645513794793071525544368892438895602506629123069
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.19474972231341145750239068983874272339684805032879816170603196537848123317075
Short name T483
Test name
Test status
Simulation time 2162831562 ps
CPU time 7.85 seconds
Started Nov 22 12:40:21 PM PST 23
Finished Nov 22 12:40:32 PM PST 23
Peak memory 216988 kb
Host smart-a626b2c4-01ea-482f-a2c4-01629ebdd168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19474972231341145750239068983874272339684805032879816170603196537848123317075 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 19.rstmgr_leaf_rst_cnsty.19474972231341145750239068983874272339684805032879816170603196537848123317075
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.10826064535380135675793386854640399090164716008881236358336359659805206897763
Short name T258
Test name
Test status
Simulation time 243816210 ps
CPU time 1.13 seconds
Started Nov 22 12:40:29 PM PST 23
Finished Nov 22 12:40:32 PM PST 23
Peak memory 216840 kb
Host smart-38b8614f-eff2-4ed5-b8a6-db1ac8dbfe33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10826064535380135675793386854640399090164716008881236358336359659805206897763 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.10826064535380135675793386854640399090164716008881236358336359659805206897763
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.107211027830095355789425096466676554809513643622082879953085468007935951297279
Short name T20
Test name
Test status
Simulation time 230357768 ps
CPU time 0.97 seconds
Started Nov 22 12:40:28 PM PST 23
Finished Nov 22 12:40:30 PM PST 23
Peak memory 199652 kb
Host smart-d5423714-db2f-4cc7-9058-54c09d173180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107211027830095355789425096466676554809513643622082879953085468007935951297279 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 19.rstmgr_por_stretcher.107211027830095355789425096466676554809513643622082879953085468007935951297279
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.76407507355147578580149694207407936932336695456845276348282335511860396752041
Short name T4
Test name
Test status
Simulation time 1729953098 ps
CPU time 6.53 seconds
Started Nov 22 12:40:23 PM PST 23
Finished Nov 22 12:40:33 PM PST 23
Peak memory 199964 kb
Host smart-430a96d6-85a7-4025-ab67-72f320066cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76407507355147578580149694207407936932336695456845276348282335511860396752041 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 19.rstmgr_reset.76407507355147578580149694207407936932336695456845276348282335511860396752041
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.67768784461370673490642509134679970160326685691133185252253720959811431630640
Short name T235
Test name
Test status
Simulation time 170065619 ps
CPU time 1.17 seconds
Started Nov 22 12:40:23 PM PST 23
Finished Nov 22 12:40:27 PM PST 23
Peak memory 199888 kb
Host smart-6673fb35-cdaa-4792-8fa4-9431e438b01b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67768784461370673490642509134679970160326685691133185252253720959811431630640 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.67768784461370673490642509134679970160326685691133185252253720959811431630640
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.52219534642891433282965290604700435990716230654191025212878555792437689029338
Short name T490
Test name
Test status
Simulation time 223941050 ps
CPU time 1.45 seconds
Started Nov 22 12:40:34 PM PST 23
Finished Nov 22 12:40:37 PM PST 23
Peak memory 200056 kb
Host smart-9080761c-d782-4441-bb7c-bf1427cdc8ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52219534642891433282965290604700435990716230654191025212878555792437689029338 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 19.rstmgr_smoke.52219534642891433282965290604700435990716230654191025212878555792437689029338
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.53017033232119944393061446659978057514658208898358721747040046541956187669345
Short name T618
Test name
Test status
Simulation time 11131278308 ps
CPU time 39.18 seconds
Started Nov 22 12:40:23 PM PST 23
Finished Nov 22 12:41:05 PM PST 23
Peak memory 200060 kb
Host smart-6736cd7b-c05e-464b-87ad-5a4d1bbe3f6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53017033232119944393061446659978057514658208898358721747040046541956187669345 -assert nopos
tproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.53017033232119944393061446659978057514658208898358721747040046541956187669345
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.113115026760452093984866665562454195821863341688255880025757931173763138062347
Short name T311
Test name
Test status
Simulation time 473109710 ps
CPU time 2.67 seconds
Started Nov 22 12:40:34 PM PST 23
Finished Nov 22 12:40:38 PM PST 23
Peak memory 199852 kb
Host smart-b4c6ac84-16c0-4580-b1db-58635609da86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113115026760452093984866665562454195821863341688255880025757931173763138062347 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.rstmgr_sw_rst.113115026760452093984866665562454195821863341688255880025757931173763138062347
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.55895730498620909040640678041550739199389257459993524906533469552686251866815
Short name T394
Test name
Test status
Simulation time 241232855 ps
CPU time 1.41 seconds
Started Nov 22 12:40:25 PM PST 23
Finished Nov 22 12:40:29 PM PST 23
Peak memory 199888 kb
Host smart-96814118-18bb-4d96-876f-cb632b2ecec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55895730498620909040640678041550739199389257459993524906533469552686251866815 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.rstmgr_sw_rst_reset_race.55895730498620909040640678041550739199389257459993524906533469552686251866815
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.83793962036683457821403774646141813424929947126585435054922793164064187771307
Short name T452
Test name
Test status
Simulation time 78981557 ps
CPU time 0.75 seconds
Started Nov 22 12:39:41 PM PST 23
Finished Nov 22 12:39:45 PM PST 23
Peak memory 199608 kb
Host smart-8d3e7085-36c8-4a5c-9ab2-378cce0169d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83793962036683457821403774646141813424929947126585435054922793164064187771307 -assert nopostpr
oc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.83793962036683457821403774646141813424929947126585435054922793164064187771307
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.78620339179566498963218768123801014734554126701515564011848028514508561199410
Short name T405
Test name
Test status
Simulation time 2162831562 ps
CPU time 8.07 seconds
Started Nov 22 12:39:37 PM PST 23
Finished Nov 22 12:39:50 PM PST 23
Peak memory 217120 kb
Host smart-8741ceb3-0c6d-4763-9db7-39a0db434584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78620339179566498963218768123801014734554126701515564011848028514508561199410 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 2.rstmgr_leaf_rst_cnsty.78620339179566498963218768123801014734554126701515564011848028514508561199410
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.27575053133231337900838750421970033258359017314638339144808911284637742195356
Short name T503
Test name
Test status
Simulation time 243816210 ps
CPU time 1.09 seconds
Started Nov 22 12:39:38 PM PST 23
Finished Nov 22 12:39:44 PM PST 23
Peak memory 216660 kb
Host smart-76785221-0f77-43de-9979-6f54953eded2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27575053133231337900838750421970033258359017314638339144808911284637742195356 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.27575053133231337900838750421970033258359017314638339144808911284637742195356
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.33098240059415728100772769231293394596250328841734927285514294081744927162453
Short name T345
Test name
Test status
Simulation time 230357768 ps
CPU time 0.93 seconds
Started Nov 22 12:39:32 PM PST 23
Finished Nov 22 12:39:36 PM PST 23
Peak memory 199552 kb
Host smart-38c54f1e-16fb-41bf-8dcf-2d0dc36461a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33098240059415728100772769231293394596250328841734927285514294081744927162453 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.rstmgr_por_stretcher.33098240059415728100772769231293394596250328841734927285514294081744927162453
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.18018050693502753088720099807347419552811289521732705202288577501943886529977
Short name T237
Test name
Test status
Simulation time 1729953098 ps
CPU time 6.67 seconds
Started Nov 22 12:39:33 PM PST 23
Finished Nov 22 12:39:42 PM PST 23
Peak memory 199960 kb
Host smart-16494ec3-40a5-46f7-919a-f71deb68b1ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18018050693502753088720099807347419552811289521732705202288577501943886529977 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 2.rstmgr_reset.18018050693502753088720099807347419552811289521732705202288577501943886529977
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.68157993645765134446927516432069459853118477905747970190762985785588220480982
Short name T62
Test name
Test status
Simulation time 8294713949 ps
CPU time 13.98 seconds
Started Nov 22 12:39:58 PM PST 23
Finished Nov 22 12:40:14 PM PST 23
Peak memory 216676 kb
Host smart-18bd53d4-53d7-4ad5-ae17-440efd6380ab
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68157993645765134446927516432069459853118477905747970190762985785588220480982 -assert nopostpro
c +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.68157993645765134446927516432069459853118477905747970190762985785588220480982
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.91693863626096502750547557430108705548806332604836435904510833450799663524271
Short name T272
Test name
Test status
Simulation time 223941050 ps
CPU time 1.44 seconds
Started Nov 22 12:39:34 PM PST 23
Finished Nov 22 12:39:37 PM PST 23
Peak memory 199916 kb
Host smart-4d5e6239-46cb-4e91-b7f1-ad329092423d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91693863626096502750547557430108705548806332604836435904510833450799663524271 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 2.rstmgr_smoke.91693863626096502750547557430108705548806332604836435904510833450799663524271
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.11387997671648916443919699870841804794495492011668463145899009159109284309160
Short name T11
Test name
Test status
Simulation time 11131278308 ps
CPU time 39.1 seconds
Started Nov 22 12:39:29 PM PST 23
Finished Nov 22 12:40:10 PM PST 23
Peak memory 200068 kb
Host smart-50441f70-cd91-4d1b-8fc1-f1d8fe01878f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11387997671648916443919699870841804794495492011668463145899009159109284309160 -assert nopos
tproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.11387997671648916443919699870841804794495492011668463145899009159109284309160
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.56497344716928677538874358147153312928851155377002274659118821468590789884881
Short name T560
Test name
Test status
Simulation time 473109710 ps
CPU time 2.78 seconds
Started Nov 22 12:39:31 PM PST 23
Finished Nov 22 12:39:37 PM PST 23
Peak memory 199700 kb
Host smart-b1f3ad92-33c7-41ef-82ec-b3b0cc7f1d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56497344716928677538874358147153312928851155377002274659118821468590789884881 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 2.rstmgr_sw_rst.56497344716928677538874358147153312928851155377002274659118821468590789884881
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.79835906901554650230968343329998424031572173240464610487330451952430824682067
Short name T553
Test name
Test status
Simulation time 241232855 ps
CPU time 1.4 seconds
Started Nov 22 12:39:27 PM PST 23
Finished Nov 22 12:39:30 PM PST 23
Peak memory 199748 kb
Host smart-bc91fd77-8f6d-4e5a-b02e-66606327c2b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79835906901554650230968343329998424031572173240464610487330451952430824682067 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.rstmgr_sw_rst_reset_race.79835906901554650230968343329998424031572173240464610487330451952430824682067
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.5143201165413188102648392043935305271074334245259115477503523369624826536361
Short name T106
Test name
Test status
Simulation time 78981557 ps
CPU time 0.76 seconds
Started Nov 22 12:40:24 PM PST 23
Finished Nov 22 12:40:28 PM PST 23
Peak memory 199564 kb
Host smart-76f60ab3-8fa2-4a8d-850b-b14a27e02232
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5143201165413188102648392043935305271074334245259115477503523369624826536361 -assert nopostpro
c +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.5143201165413188102648392043935305271074334245259115477503523369624826536361
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.33302751516448334594753303329483348320935042060262018467665373429448909242189
Short name T463
Test name
Test status
Simulation time 2162831562 ps
CPU time 8.22 seconds
Started Nov 22 12:40:26 PM PST 23
Finished Nov 22 12:40:36 PM PST 23
Peak memory 217076 kb
Host smart-9e25755a-4b05-413b-bbb7-e65fb8e10b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33302751516448334594753303329483348320935042060262018467665373429448909242189 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 20.rstmgr_leaf_rst_cnsty.33302751516448334594753303329483348320935042060262018467665373429448909242189
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.78728152206489858039253548424875130626366210414829750420662915979047314475807
Short name T465
Test name
Test status
Simulation time 243816210 ps
CPU time 1.14 seconds
Started Nov 22 12:40:25 PM PST 23
Finished Nov 22 12:40:29 PM PST 23
Peak memory 216808 kb
Host smart-e53db7eb-c523-4c5f-a025-c4df3c3e5193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78728152206489858039253548424875130626366210414829750420662915979047314475807 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.78728152206489858039253548424875130626366210414829750420662915979047314475807
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.109228425630556602143294409773577421849571856788049987927989822440922130917854
Short name T142
Test name
Test status
Simulation time 230357768 ps
CPU time 0.97 seconds
Started Nov 22 12:40:41 PM PST 23
Finished Nov 22 12:40:43 PM PST 23
Peak memory 199588 kb
Host smart-b804697f-b13b-49f0-bc21-29dba92cebd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109228425630556602143294409773577421849571856788049987927989822440922130917854 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 20.rstmgr_por_stretcher.109228425630556602143294409773577421849571856788049987927989822440922130917854
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.79516275998150917907292894239934662082984148609634366587571217611479582125574
Short name T105
Test name
Test status
Simulation time 1729953098 ps
CPU time 6.59 seconds
Started Nov 22 12:40:27 PM PST 23
Finished Nov 22 12:40:35 PM PST 23
Peak memory 199940 kb
Host smart-d2abb100-453a-4591-a969-1cee4c9d29ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79516275998150917907292894239934662082984148609634366587571217611479582125574 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 20.rstmgr_reset.79516275998150917907292894239934662082984148609634366587571217611479582125574
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.11451247507995279720869477452022086309767737270769163704734656761914036978788
Short name T496
Test name
Test status
Simulation time 170065619 ps
CPU time 1.15 seconds
Started Nov 22 12:40:32 PM PST 23
Finished Nov 22 12:40:35 PM PST 23
Peak memory 199880 kb
Host smart-98a7b4d5-ffd1-4ad5-8d19-619e654f3ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11451247507995279720869477452022086309767737270769163704734656761914036978788 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.11451247507995279720869477452022086309767737270769163704734656761914036978788
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.64031547861518328409236654909590609612582745277130638731987408327158993736645
Short name T608
Test name
Test status
Simulation time 223941050 ps
CPU time 1.43 seconds
Started Nov 22 12:40:32 PM PST 23
Finished Nov 22 12:40:34 PM PST 23
Peak memory 199924 kb
Host smart-651e8327-ce18-452f-90cf-f44ec9c505eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64031547861518328409236654909590609612582745277130638731987408327158993736645 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 20.rstmgr_smoke.64031547861518328409236654909590609612582745277130638731987408327158993736645
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.57990532022128488460643375350409631174270906224636082339569439257214157145516
Short name T418
Test name
Test status
Simulation time 11131278308 ps
CPU time 38.41 seconds
Started Nov 22 12:40:32 PM PST 23
Finished Nov 22 12:41:12 PM PST 23
Peak memory 200000 kb
Host smart-cd880ae4-8af1-4131-b1a4-fd550878fbaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57990532022128488460643375350409631174270906224636082339569439257214157145516 -assert nopos
tproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.57990532022128488460643375350409631174270906224636082339569439257214157145516
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.54731186493705106229435827688137817933708209490220745079810328942196499612352
Short name T340
Test name
Test status
Simulation time 473109710 ps
CPU time 2.78 seconds
Started Nov 22 12:40:49 PM PST 23
Finished Nov 22 12:40:53 PM PST 23
Peak memory 199840 kb
Host smart-f7f30ead-b4cf-4bb0-9c3d-1b4e88743799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54731186493705106229435827688137817933708209490220745079810328942196499612352 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 20.rstmgr_sw_rst.54731186493705106229435827688137817933708209490220745079810328942196499612352
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.110269809527700105144823077734100241871141995449281048611493167129936045033053
Short name T589
Test name
Test status
Simulation time 241232855 ps
CPU time 1.35 seconds
Started Nov 22 12:40:21 PM PST 23
Finished Nov 22 12:40:25 PM PST 23
Peak memory 199744 kb
Host smart-72b97392-d476-414e-aeca-160e8a7e6d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110269809527700105144823077734100241871141995449281048611493167129936045033053 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 20.rstmgr_sw_rst_reset_race.110269809527700105144823077734100241871141995449281048611493167129936045033053
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.5970659648472356404802768442223854561439761273458645356119671091777766446616
Short name T107
Test name
Test status
Simulation time 78981557 ps
CPU time 0.81 seconds
Started Nov 22 12:40:27 PM PST 23
Finished Nov 22 12:40:30 PM PST 23
Peak memory 199536 kb
Host smart-369d9266-319a-4055-960a-239c43ba99d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5970659648472356404802768442223854561439761273458645356119671091777766446616 -assert nopostpro
c +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.5970659648472356404802768442223854561439761273458645356119671091777766446616
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.12136233641010899366677955914466423211151491818433917826038376843906706459038
Short name T34
Test name
Test status
Simulation time 2162831562 ps
CPU time 7.96 seconds
Started Nov 22 12:40:26 PM PST 23
Finished Nov 22 12:40:36 PM PST 23
Peak memory 217100 kb
Host smart-18d98238-7f99-4e8b-b109-2d5848d7098d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12136233641010899366677955914466423211151491818433917826038376843906706459038 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 21.rstmgr_leaf_rst_cnsty.12136233641010899366677955914466423211151491818433917826038376843906706459038
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.17464952682076319789063944895992942379737289973298840030457972625176329617072
Short name T287
Test name
Test status
Simulation time 243816210 ps
CPU time 1.09 seconds
Started Nov 22 12:40:29 PM PST 23
Finished Nov 22 12:40:32 PM PST 23
Peak memory 216812 kb
Host smart-460fec29-cd3c-41eb-8d59-06f42aae8b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17464952682076319789063944895992942379737289973298840030457972625176329617072 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.17464952682076319789063944895992942379737289973298840030457972625176329617072
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.22319438265417596273070492087507044600098191674742381518707501759598505391662
Short name T2
Test name
Test status
Simulation time 230357768 ps
CPU time 0.94 seconds
Started Nov 22 12:40:25 PM PST 23
Finished Nov 22 12:40:29 PM PST 23
Peak memory 199572 kb
Host smart-d468b341-1120-4ded-9789-dcb40fa220a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22319438265417596273070492087507044600098191674742381518707501759598505391662 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.rstmgr_por_stretcher.22319438265417596273070492087507044600098191674742381518707501759598505391662
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.100131120439989511897430141882196139147860416703280093874642415237212018501910
Short name T100
Test name
Test status
Simulation time 1729953098 ps
CPU time 6.6 seconds
Started Nov 22 12:40:29 PM PST 23
Finished Nov 22 12:40:37 PM PST 23
Peak memory 200056 kb
Host smart-bb491957-282b-47ce-b3a3-188631a0fea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100131120439989511897430141882196139147860416703280093874642415237212018501910 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 21.rstmgr_reset.100131120439989511897430141882196139147860416703280093874642415237212018501910
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.50122687643943722017334193647122288292851977308798996498613648527371703676825
Short name T35
Test name
Test status
Simulation time 170065619 ps
CPU time 1.15 seconds
Started Nov 22 12:40:41 PM PST 23
Finished Nov 22 12:40:44 PM PST 23
Peak memory 199904 kb
Host smart-f342fa65-7dce-4046-a523-c2708452e339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50122687643943722017334193647122288292851977308798996498613648527371703676825 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.50122687643943722017334193647122288292851977308798996498613648527371703676825
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.49101120948624982727556967623793329014813222698918183160557499111796045447264
Short name T254
Test name
Test status
Simulation time 223941050 ps
CPU time 1.43 seconds
Started Nov 22 12:40:23 PM PST 23
Finished Nov 22 12:40:28 PM PST 23
Peak memory 200012 kb
Host smart-7bb874e7-1964-4350-8076-b149ac335ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49101120948624982727556967623793329014813222698918183160557499111796045447264 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 21.rstmgr_smoke.49101120948624982727556967623793329014813222698918183160557499111796045447264
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.35508722100955566218710218551727913512823991769733057837648448652738310091281
Short name T359
Test name
Test status
Simulation time 11131278308 ps
CPU time 40.41 seconds
Started Nov 22 12:40:34 PM PST 23
Finished Nov 22 12:41:16 PM PST 23
Peak memory 199996 kb
Host smart-44362a4f-bcad-42e6-9a57-e63950698add
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35508722100955566218710218551727913512823991769733057837648448652738310091281 -assert nopos
tproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.35508722100955566218710218551727913512823991769733057837648448652738310091281
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.67341165323931286562427853448923145480723910891885888978990488020399754229280
Short name T573
Test name
Test status
Simulation time 473109710 ps
CPU time 2.63 seconds
Started Nov 22 12:40:29 PM PST 23
Finished Nov 22 12:40:33 PM PST 23
Peak memory 199812 kb
Host smart-e45946b1-aaa2-4e8c-99b4-0bca94083020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67341165323931286562427853448923145480723910891885888978990488020399754229280 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 21.rstmgr_sw_rst.67341165323931286562427853448923145480723910891885888978990488020399754229280
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.9906685405999915415546613957171810037888827740773277478545023076902810948522
Short name T92
Test name
Test status
Simulation time 241232855 ps
CPU time 1.4 seconds
Started Nov 22 12:40:24 PM PST 23
Finished Nov 22 12:40:29 PM PST 23
Peak memory 199868 kb
Host smart-af31882a-7d7c-4e65-bc60-0bd70df74fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9906685405999915415546613957171810037888827740773277478545023076902810948522 -assert nopostproc +UVM_TESTNAME=rstmgr_bas
e_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 21.rstmgr_sw_rst_reset_race.9906685405999915415546613957171810037888827740773277478545023076902810948522
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.86817565722768052627739920748374126204965623789634249050010034658108573524249
Short name T410
Test name
Test status
Simulation time 78981557 ps
CPU time 0.76 seconds
Started Nov 22 12:40:42 PM PST 23
Finished Nov 22 12:40:45 PM PST 23
Peak memory 199708 kb
Host smart-fcb9875e-7cbb-4b29-9984-580d14f65c82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86817565722768052627739920748374126204965623789634249050010034658108573524249 -assert nopostpr
oc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.86817565722768052627739920748374126204965623789634249050010034658108573524249
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.44807872812888039099265354018670529671192614341877545403285985406616635633677
Short name T599
Test name
Test status
Simulation time 2162831562 ps
CPU time 8.34 seconds
Started Nov 22 12:40:39 PM PST 23
Finished Nov 22 12:40:49 PM PST 23
Peak memory 216936 kb
Host smart-0ce4b461-0376-4566-8c96-33d19d2227f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44807872812888039099265354018670529671192614341877545403285985406616635633677 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 22.rstmgr_leaf_rst_cnsty.44807872812888039099265354018670529671192614341877545403285985406616635633677
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.22893294617962543449204168826573843547465769051648566884905648230052987641121
Short name T586
Test name
Test status
Simulation time 243816210 ps
CPU time 1.11 seconds
Started Nov 22 12:40:42 PM PST 23
Finished Nov 22 12:40:45 PM PST 23
Peak memory 216844 kb
Host smart-ae3ea30a-0b1e-4842-bfc1-b92685d9ad05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22893294617962543449204168826573843547465769051648566884905648230052987641121 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.22893294617962543449204168826573843547465769051648566884905648230052987641121
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.106626561621697764060593558644702948419028778824264765049713047953869710968749
Short name T16
Test name
Test status
Simulation time 230357768 ps
CPU time 0.91 seconds
Started Nov 22 12:40:27 PM PST 23
Finished Nov 22 12:40:30 PM PST 23
Peak memory 199616 kb
Host smart-719b977c-e83a-4a63-a885-224fe693b625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106626561621697764060593558644702948419028778824264765049713047953869710968749 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 22.rstmgr_por_stretcher.106626561621697764060593558644702948419028778824264765049713047953869710968749
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.18661902790383664794023794377579541416016918674226655565381699046141215383349
Short name T232
Test name
Test status
Simulation time 1729953098 ps
CPU time 6.74 seconds
Started Nov 22 12:40:45 PM PST 23
Finished Nov 22 12:40:53 PM PST 23
Peak memory 200084 kb
Host smart-53c112b6-be8c-46be-a635-ff2dc89bbf6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18661902790383664794023794377579541416016918674226655565381699046141215383349 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 22.rstmgr_reset.18661902790383664794023794377579541416016918674226655565381699046141215383349
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.53271679807530473930531185000757703594824602709398346694289907253938760243463
Short name T94
Test name
Test status
Simulation time 170065619 ps
CPU time 1.17 seconds
Started Nov 22 12:40:30 PM PST 23
Finished Nov 22 12:40:33 PM PST 23
Peak memory 199860 kb
Host smart-37cf1f09-6a34-41f2-ab9a-d7109493e992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53271679807530473930531185000757703594824602709398346694289907253938760243463 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.53271679807530473930531185000757703594824602709398346694289907253938760243463
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.93766013507659212265344107336678542200053017572406939199897302771012937456340
Short name T598
Test name
Test status
Simulation time 223941050 ps
CPU time 1.47 seconds
Started Nov 22 12:40:29 PM PST 23
Finished Nov 22 12:40:32 PM PST 23
Peak memory 199928 kb
Host smart-30b716e5-dbdd-4651-a191-20bb8df9767d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93766013507659212265344107336678542200053017572406939199897302771012937456340 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 22.rstmgr_smoke.93766013507659212265344107336678542200053017572406939199897302771012937456340
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.4004198412760966317628513089099312605738394051104440189411525904312096612874
Short name T119
Test name
Test status
Simulation time 11131278308 ps
CPU time 39.79 seconds
Started Nov 22 12:40:30 PM PST 23
Finished Nov 22 12:41:11 PM PST 23
Peak memory 200116 kb
Host smart-99ae9833-3242-40d3-93ba-31ef45d38340
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004198412760966317628513089099312605738394051104440189411525904312096612874 -assert nopost
proc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.4004198412760966317628513089099312605738394051104440189411525904312096612874
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.76842220730261567685647277787117345387764419777768613899055563765317240451212
Short name T387
Test name
Test status
Simulation time 473109710 ps
CPU time 2.62 seconds
Started Nov 22 12:40:31 PM PST 23
Finished Nov 22 12:40:35 PM PST 23
Peak memory 199888 kb
Host smart-64b09363-8ef3-4692-81e2-b8d0a761550a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76842220730261567685647277787117345387764419777768613899055563765317240451212 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 22.rstmgr_sw_rst.76842220730261567685647277787117345387764419777768613899055563765317240451212
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.64157706799405786119682038136207861352763860218639969307550592924657962261301
Short name T488
Test name
Test status
Simulation time 241232855 ps
CPU time 1.4 seconds
Started Nov 22 12:40:26 PM PST 23
Finished Nov 22 12:40:29 PM PST 23
Peak memory 199824 kb
Host smart-31ec096d-0ed1-4371-915f-77c23714a13b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64157706799405786119682038136207861352763860218639969307550592924657962261301 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.rstmgr_sw_rst_reset_race.64157706799405786119682038136207861352763860218639969307550592924657962261301
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.76153789270288455861547859205603363372045303798974637986675011888651110993022
Short name T514
Test name
Test status
Simulation time 78981557 ps
CPU time 0.78 seconds
Started Nov 22 12:40:49 PM PST 23
Finished Nov 22 12:40:51 PM PST 23
Peak memory 199720 kb
Host smart-418bb585-62a0-4a11-b7c5-5a945ecff61f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76153789270288455861547859205603363372045303798974637986675011888651110993022 -assert nopostpr
oc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.76153789270288455861547859205603363372045303798974637986675011888651110993022
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.80448661126419129082833106217393233177385767371767164583284477839636058537369
Short name T536
Test name
Test status
Simulation time 2162831562 ps
CPU time 7.98 seconds
Started Nov 22 12:40:43 PM PST 23
Finished Nov 22 12:40:53 PM PST 23
Peak memory 217124 kb
Host smart-58a272b5-9968-41d2-b7a5-5edcac0ad8f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80448661126419129082833106217393233177385767371767164583284477839636058537369 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 23.rstmgr_leaf_rst_cnsty.80448661126419129082833106217393233177385767371767164583284477839636058537369
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.22956941779574837733078633864883256942015526525770989792745236323193130800012
Short name T335
Test name
Test status
Simulation time 243816210 ps
CPU time 1.12 seconds
Started Nov 22 12:40:34 PM PST 23
Finished Nov 22 12:40:37 PM PST 23
Peak memory 216732 kb
Host smart-b3f1e6d4-6f3f-42be-ae89-58191e0b05b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22956941779574837733078633864883256942015526525770989792745236323193130800012 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.22956941779574837733078633864883256942015526525770989792745236323193130800012
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.16827201687269380049241001171368280867839801710089413437924994586536042067430
Short name T361
Test name
Test status
Simulation time 230357768 ps
CPU time 0.95 seconds
Started Nov 22 12:40:36 PM PST 23
Finished Nov 22 12:40:38 PM PST 23
Peak memory 199680 kb
Host smart-1f51675a-fc7e-4dc4-8568-ae67654daaf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16827201687269380049241001171368280867839801710089413437924994586536042067430 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.rstmgr_por_stretcher.16827201687269380049241001171368280867839801710089413437924994586536042067430
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.49841969210604511133929548113287957787734333142880067011338855640804611719575
Short name T108
Test name
Test status
Simulation time 1729953098 ps
CPU time 6.53 seconds
Started Nov 22 12:40:48 PM PST 23
Finished Nov 22 12:40:56 PM PST 23
Peak memory 200080 kb
Host smart-99f697c5-0fbc-4d37-b164-bde9def8387f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49841969210604511133929548113287957787734333142880067011338855640804611719575 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 23.rstmgr_reset.49841969210604511133929548113287957787734333142880067011338855640804611719575
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.89240150043210276448471228981936597124531263508713112103049414497913092969089
Short name T69
Test name
Test status
Simulation time 170065619 ps
CPU time 1.18 seconds
Started Nov 22 12:40:35 PM PST 23
Finished Nov 22 12:40:38 PM PST 23
Peak memory 199364 kb
Host smart-5b7b9e60-d46c-45ca-979c-9408ff96bfec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89240150043210276448471228981936597124531263508713112103049414497913092969089 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.89240150043210276448471228981936597124531263508713112103049414497913092969089
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.59449986259141446298639644961298934371530430151214335590125725332268888873774
Short name T477
Test name
Test status
Simulation time 223941050 ps
CPU time 1.42 seconds
Started Nov 22 12:40:31 PM PST 23
Finished Nov 22 12:40:34 PM PST 23
Peak memory 200044 kb
Host smart-086afa09-22a9-44f5-9eeb-5b9076473840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59449986259141446298639644961298934371530430151214335590125725332268888873774 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 23.rstmgr_smoke.59449986259141446298639644961298934371530430151214335590125725332268888873774
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.114461282701240091174462471895944324513960309908482815975986569309926865152636
Short name T12
Test name
Test status
Simulation time 11131278308 ps
CPU time 39.72 seconds
Started Nov 22 12:40:41 PM PST 23
Finished Nov 22 12:41:21 PM PST 23
Peak memory 200100 kb
Host smart-1cf869f3-bd14-4265-8872-71a8cbab3bf0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114461282701240091174462471895944324513960309908482815975986569309926865152636 -assert nopo
stproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.114461282701240091174462471895944324513960309908482815975986569309926865152636
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.43493847399823493772804105956874290822575162717988210564155483747972675903137
Short name T438
Test name
Test status
Simulation time 473109710 ps
CPU time 2.66 seconds
Started Nov 22 12:40:31 PM PST 23
Finished Nov 22 12:40:35 PM PST 23
Peak memory 199748 kb
Host smart-5d3f8c4b-2770-4deb-a20b-4b8a5c75cdf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43493847399823493772804105956874290822575162717988210564155483747972675903137 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 23.rstmgr_sw_rst.43493847399823493772804105956874290822575162717988210564155483747972675903137
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.84291116738356035068653910471448606950241972426013321498888836083584020505898
Short name T462
Test name
Test status
Simulation time 241232855 ps
CPU time 1.41 seconds
Started Nov 22 12:40:46 PM PST 23
Finished Nov 22 12:40:48 PM PST 23
Peak memory 199884 kb
Host smart-a27e872d-e1e3-4247-85e7-a2843a1fdb38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84291116738356035068653910471448606950241972426013321498888836083584020505898 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 23.rstmgr_sw_rst_reset_race.84291116738356035068653910471448606950241972426013321498888836083584020505898
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.37471379145415892631195566251175887697229405444901061737179991751271509759024
Short name T481
Test name
Test status
Simulation time 78981557 ps
CPU time 0.72 seconds
Started Nov 22 12:40:30 PM PST 23
Finished Nov 22 12:40:33 PM PST 23
Peak memory 199588 kb
Host smart-51ca0d95-0dc0-449b-885f-0eb43f2590a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37471379145415892631195566251175887697229405444901061737179991751271509759024 -assert nopostpr
oc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.37471379145415892631195566251175887697229405444901061737179991751271509759024
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.62816265910973739949132429867913836128571934653116285691797458590391194888146
Short name T282
Test name
Test status
Simulation time 2162831562 ps
CPU time 7.97 seconds
Started Nov 22 12:40:51 PM PST 23
Finished Nov 22 12:41:00 PM PST 23
Peak memory 217072 kb
Host smart-0ff33e23-1f4f-4c49-abb1-36314c90b99e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62816265910973739949132429867913836128571934653116285691797458590391194888146 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 24.rstmgr_leaf_rst_cnsty.62816265910973739949132429867913836128571934653116285691797458590391194888146
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.26424943375658341187736800517564889218441372575720859072722666905738719337478
Short name T434
Test name
Test status
Simulation time 243816210 ps
CPU time 1.09 seconds
Started Nov 22 12:40:41 PM PST 23
Finished Nov 22 12:40:44 PM PST 23
Peak memory 216808 kb
Host smart-d7af680e-bf73-428c-a8d4-b0859e271948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26424943375658341187736800517564889218441372575720859072722666905738719337478 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.26424943375658341187736800517564889218441372575720859072722666905738719337478
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.25453901855722146651111457987056899709528206121775006723173455722880124316453
Short name T295
Test name
Test status
Simulation time 230357768 ps
CPU time 0.91 seconds
Started Nov 22 12:40:41 PM PST 23
Finished Nov 22 12:40:43 PM PST 23
Peak memory 199652 kb
Host smart-f14de8f7-d495-472e-828b-7c17bfe31dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25453901855722146651111457987056899709528206121775006723173455722880124316453 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.rstmgr_por_stretcher.25453901855722146651111457987056899709528206121775006723173455722880124316453
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.46097155584464728518951294531208258674997598947510053772143372731992536236348
Short name T276
Test name
Test status
Simulation time 1729953098 ps
CPU time 6.75 seconds
Started Nov 22 12:40:47 PM PST 23
Finished Nov 22 12:40:55 PM PST 23
Peak memory 200104 kb
Host smart-6cfcd7d4-0935-4b39-9acc-5241563e4a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46097155584464728518951294531208258674997598947510053772143372731992536236348 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 24.rstmgr_reset.46097155584464728518951294531208258674997598947510053772143372731992536236348
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.107105162980146531052346913156129292929372064390362777338904931212611724936466
Short name T487
Test name
Test status
Simulation time 170065619 ps
CPU time 1.11 seconds
Started Nov 22 12:40:28 PM PST 23
Finished Nov 22 12:40:30 PM PST 23
Peak memory 199764 kb
Host smart-731bec82-fc0d-4bb4-9696-a12d43191884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107105162980146531052346913156129292929372064390362777338904931212611724936466 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.107105162980146531052346913156129292929372064390362777338904931212611724936466
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.88508324891147182488244549073049082173574998499587261636617184562302375490278
Short name T521
Test name
Test status
Simulation time 223941050 ps
CPU time 1.38 seconds
Started Nov 22 12:40:39 PM PST 23
Finished Nov 22 12:40:42 PM PST 23
Peak memory 200040 kb
Host smart-79b96751-0fbb-40dd-a68c-e9dda7cb0c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88508324891147182488244549073049082173574998499587261636617184562302375490278 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 24.rstmgr_smoke.88508324891147182488244549073049082173574998499587261636617184562302375490278
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.113287166483494045487367395907327969444263346163488119764775028467671425353746
Short name T123
Test name
Test status
Simulation time 11131278308 ps
CPU time 39.87 seconds
Started Nov 22 12:40:30 PM PST 23
Finished Nov 22 12:41:12 PM PST 23
Peak memory 199960 kb
Host smart-93dfe786-24f6-472d-bcdb-12a1ae482708
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113287166483494045487367395907327969444263346163488119764775028467671425353746 -assert nopo
stproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.113287166483494045487367395907327969444263346163488119764775028467671425353746
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.42980112695914774232829228137779424200957251202026648905856940335355622336148
Short name T539
Test name
Test status
Simulation time 473109710 ps
CPU time 2.58 seconds
Started Nov 22 12:40:51 PM PST 23
Finished Nov 22 12:40:54 PM PST 23
Peak memory 199784 kb
Host smart-8936b8b9-a2ec-4d2b-b50c-68855816efe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42980112695914774232829228137779424200957251202026648905856940335355622336148 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 24.rstmgr_sw_rst.42980112695914774232829228137779424200957251202026648905856940335355622336148
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.25831085284003710633695354111354643318669541639224150789760814915472960282044
Short name T338
Test name
Test status
Simulation time 241232855 ps
CPU time 1.45 seconds
Started Nov 22 12:40:34 PM PST 23
Finished Nov 22 12:40:37 PM PST 23
Peak memory 199748 kb
Host smart-ecd9fbcc-b48f-46d1-9c83-4b8eaf409c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25831085284003710633695354111354643318669541639224150789760814915472960282044 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 24.rstmgr_sw_rst_reset_race.25831085284003710633695354111354643318669541639224150789760814915472960282044
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.24632284193041776404582550686348325965668019238094230989247340754471484387837
Short name T552
Test name
Test status
Simulation time 78981557 ps
CPU time 0.78 seconds
Started Nov 22 12:40:46 PM PST 23
Finished Nov 22 12:40:48 PM PST 23
Peak memory 199600 kb
Host smart-0dcc7cae-8463-49c1-b32f-017f3818a388
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24632284193041776404582550686348325965668019238094230989247340754471484387837 -assert nopostpr
oc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.24632284193041776404582550686348325965668019238094230989247340754471484387837
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.13695598050483592112023002111430512415646646604427020000371299390675528332459
Short name T299
Test name
Test status
Simulation time 2162831562 ps
CPU time 8.07 seconds
Started Nov 22 12:40:45 PM PST 23
Finished Nov 22 12:40:54 PM PST 23
Peak memory 217120 kb
Host smart-ce5a9b0f-c406-4725-a1ce-8ad85aa68d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13695598050483592112023002111430512415646646604427020000371299390675528332459 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 25.rstmgr_leaf_rst_cnsty.13695598050483592112023002111430512415646646604427020000371299390675528332459
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.26016806490682473908488731115999030428304848471555915713472815093194236257754
Short name T68
Test name
Test status
Simulation time 243816210 ps
CPU time 1.07 seconds
Started Nov 22 12:40:31 PM PST 23
Finished Nov 22 12:40:33 PM PST 23
Peak memory 216844 kb
Host smart-e5a75d0d-0910-4cc3-9d58-32af62da5927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26016806490682473908488731115999030428304848471555915713472815093194236257754 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.26016806490682473908488731115999030428304848471555915713472815093194236257754
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.109315680299234593298673635544636514855753480775680652480470607214742180464567
Short name T347
Test name
Test status
Simulation time 230357768 ps
CPU time 0.93 seconds
Started Nov 22 12:40:31 PM PST 23
Finished Nov 22 12:40:34 PM PST 23
Peak memory 199680 kb
Host smart-648d2b08-1b3d-46f5-8f51-34930c1c8628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109315680299234593298673635544636514855753480775680652480470607214742180464567 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 25.rstmgr_por_stretcher.109315680299234593298673635544636514855753480775680652480470607214742180464567
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.10173209268953074940848101718867615355197772763882092354427512837620122546446
Short name T368
Test name
Test status
Simulation time 1729953098 ps
CPU time 6.22 seconds
Started Nov 22 12:40:30 PM PST 23
Finished Nov 22 12:40:37 PM PST 23
Peak memory 199992 kb
Host smart-4de5cbb4-29ad-47d4-aedb-50f902ffa31f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10173209268953074940848101718867615355197772763882092354427512837620122546446 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 25.rstmgr_reset.10173209268953074940848101718867615355197772763882092354427512837620122546446
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.92347911769554509011505081322888282323068931929223103232667663460160325077466
Short name T404
Test name
Test status
Simulation time 170065619 ps
CPU time 1.12 seconds
Started Nov 22 12:40:50 PM PST 23
Finished Nov 22 12:40:52 PM PST 23
Peak memory 199840 kb
Host smart-d1f23506-1c27-4b2b-bc7c-ac7e7e3291a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92347911769554509011505081322888282323068931929223103232667663460160325077466 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.92347911769554509011505081322888282323068931929223103232667663460160325077466
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.10171075482318017502381161671766601184728569892421273921712428381205313776507
Short name T431
Test name
Test status
Simulation time 223941050 ps
CPU time 1.43 seconds
Started Nov 22 12:40:34 PM PST 23
Finished Nov 22 12:40:38 PM PST 23
Peak memory 199996 kb
Host smart-d2bfcafc-c537-4466-a4b3-9d39efcace6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10171075482318017502381161671766601184728569892421273921712428381205313776507 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 25.rstmgr_smoke.10171075482318017502381161671766601184728569892421273921712428381205313776507
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.17068555249520494996844123333605057757654751542028854886169753895161262562028
Short name T126
Test name
Test status
Simulation time 11131278308 ps
CPU time 39 seconds
Started Nov 22 12:40:49 PM PST 23
Finished Nov 22 12:41:29 PM PST 23
Peak memory 200000 kb
Host smart-194b978e-e380-4c72-9721-cdeb57b20381
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17068555249520494996844123333605057757654751542028854886169753895161262562028 -assert nopos
tproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.17068555249520494996844123333605057757654751542028854886169753895161262562028
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.74294220800984993094716802266814917441447705281261423957273128578500024720959
Short name T475
Test name
Test status
Simulation time 473109710 ps
CPU time 2.66 seconds
Started Nov 22 12:40:32 PM PST 23
Finished Nov 22 12:40:36 PM PST 23
Peak memory 199828 kb
Host smart-45dbdb86-e7c0-4e47-bc4d-6db0ad32820d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74294220800984993094716802266814917441447705281261423957273128578500024720959 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 25.rstmgr_sw_rst.74294220800984993094716802266814917441447705281261423957273128578500024720959
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.86208622484519185854015032077429788886919722422390408718030825106647456200710
Short name T456
Test name
Test status
Simulation time 241232855 ps
CPU time 1.43 seconds
Started Nov 22 12:40:40 PM PST 23
Finished Nov 22 12:40:42 PM PST 23
Peak memory 199856 kb
Host smart-38792877-07c7-42c0-a651-4a5f38c97f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86208622484519185854015032077429788886919722422390408718030825106647456200710 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 25.rstmgr_sw_rst_reset_race.86208622484519185854015032077429788886919722422390408718030825106647456200710
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.31218669320881657418797027549582049135956418002637207748871061294487719348559
Short name T114
Test name
Test status
Simulation time 78981557 ps
CPU time 0.77 seconds
Started Nov 22 12:41:02 PM PST 23
Finished Nov 22 12:41:04 PM PST 23
Peak memory 199720 kb
Host smart-2c7aefb9-84cf-4402-b678-1a7833933a70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31218669320881657418797027549582049135956418002637207748871061294487719348559 -assert nopostpr
oc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.31218669320881657418797027549582049135956418002637207748871061294487719348559
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.14951562737364461765245154380078690567402433763772172842344061285295964350695
Short name T423
Test name
Test status
Simulation time 2162831562 ps
CPU time 8.02 seconds
Started Nov 22 12:40:58 PM PST 23
Finished Nov 22 12:41:07 PM PST 23
Peak memory 217068 kb
Host smart-f6793ddb-e72c-4b96-b7cd-2386b97ca890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14951562737364461765245154380078690567402433763772172842344061285295964350695 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 26.rstmgr_leaf_rst_cnsty.14951562737364461765245154380078690567402433763772172842344061285295964350695
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.113303610289053362450453137229495604334182398991664566138298959235321199835839
Short name T502
Test name
Test status
Simulation time 243816210 ps
CPU time 1.16 seconds
Started Nov 22 12:40:38 PM PST 23
Finished Nov 22 12:40:40 PM PST 23
Peak memory 216708 kb
Host smart-92acf102-af73-4a35-abae-ce09c732c072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113303610289053362450453137229495604334182398991664566138298959235321199835839 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.113303610289053362450453137229495604334182398991664566138298959235321199835839
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.94836527880842370360994251688500467170865599542679453193760206131463365524907
Short name T245
Test name
Test status
Simulation time 230357768 ps
CPU time 0.94 seconds
Started Nov 22 12:40:48 PM PST 23
Finished Nov 22 12:40:50 PM PST 23
Peak memory 199684 kb
Host smart-58bc19a7-c0cd-4c04-a446-4e6eea370dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94836527880842370360994251688500467170865599542679453193760206131463365524907 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.rstmgr_por_stretcher.94836527880842370360994251688500467170865599542679453193760206131463365524907
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.10378261707082809757619285169002086310961900298003220320691252625062937645404
Short name T366
Test name
Test status
Simulation time 1729953098 ps
CPU time 6.52 seconds
Started Nov 22 12:40:52 PM PST 23
Finished Nov 22 12:40:59 PM PST 23
Peak memory 199972 kb
Host smart-1318d405-4399-49c7-95ec-d38cfed9b415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10378261707082809757619285169002086310961900298003220320691252625062937645404 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 26.rstmgr_reset.10378261707082809757619285169002086310961900298003220320691252625062937645404
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.77072917924983960899540681932615511889427636426220970695151829769591952619891
Short name T286
Test name
Test status
Simulation time 170065619 ps
CPU time 1.21 seconds
Started Nov 22 12:41:06 PM PST 23
Finished Nov 22 12:41:09 PM PST 23
Peak memory 199928 kb
Host smart-2b2117c2-709c-4dd5-a62f-baf5cc2dbaa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77072917924983960899540681932615511889427636426220970695151829769591952619891 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.77072917924983960899540681932615511889427636426220970695151829769591952619891
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.102207833396637744745195666710367717366980062214571809840576627009027289719670
Short name T96
Test name
Test status
Simulation time 223941050 ps
CPU time 1.48 seconds
Started Nov 22 12:40:44 PM PST 23
Finished Nov 22 12:40:47 PM PST 23
Peak memory 200052 kb
Host smart-7c041472-05cb-457d-85f1-5922a5d59b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102207833396637744745195666710367717366980062214571809840576627009027289719670 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 26.rstmgr_smoke.102207833396637744745195666710367717366980062214571809840576627009027289719670
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.75562010163707014853674991629617670130148084891573175499770448919081921940396
Short name T616
Test name
Test status
Simulation time 11131278308 ps
CPU time 38.91 seconds
Started Nov 22 12:41:03 PM PST 23
Finished Nov 22 12:41:43 PM PST 23
Peak memory 200100 kb
Host smart-57eca4e6-1429-4cf6-be5c-3881c2840653
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75562010163707014853674991629617670130148084891573175499770448919081921940396 -assert nopos
tproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.75562010163707014853674991629617670130148084891573175499770448919081921940396
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.100975256684280982643949082711825719682505135512223450729611423079421137930773
Short name T441
Test name
Test status
Simulation time 473109710 ps
CPU time 2.63 seconds
Started Nov 22 12:40:37 PM PST 23
Finished Nov 22 12:40:41 PM PST 23
Peak memory 199832 kb
Host smart-f2f3f05a-6782-484b-b75a-2de3f8601241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100975256684280982643949082711825719682505135512223450729611423079421137930773 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 26.rstmgr_sw_rst.100975256684280982643949082711825719682505135512223450729611423079421137930773
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.89035022760878491256689976843976974238713236239123226723245059525675053001094
Short name T135
Test name
Test status
Simulation time 241232855 ps
CPU time 1.39 seconds
Started Nov 22 12:40:42 PM PST 23
Finished Nov 22 12:40:45 PM PST 23
Peak memory 199764 kb
Host smart-565252a9-2f5c-4ac0-bf53-11a686c9e10c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89035022760878491256689976843976974238713236239123226723245059525675053001094 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 26.rstmgr_sw_rst_reset_race.89035022760878491256689976843976974238713236239123226723245059525675053001094
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.79073243261276618118643945641513581895680447240481165684204114031693443762307
Short name T315
Test name
Test status
Simulation time 78981557 ps
CPU time 0.79 seconds
Started Nov 22 12:40:57 PM PST 23
Finished Nov 22 12:40:59 PM PST 23
Peak memory 199676 kb
Host smart-c0dc8802-b44a-45d1-876f-752da657908f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79073243261276618118643945641513581895680447240481165684204114031693443762307 -assert nopostpr
oc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.79073243261276618118643945641513581895680447240481165684204114031693443762307
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.41580949266733386043734365589831513850811562400606431174067770606274300189737
Short name T369
Test name
Test status
Simulation time 2162831562 ps
CPU time 7.88 seconds
Started Nov 22 12:41:02 PM PST 23
Finished Nov 22 12:41:11 PM PST 23
Peak memory 217008 kb
Host smart-43acec44-7f9c-4a78-b7eb-1fd20d677d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41580949266733386043734365589831513850811562400606431174067770606274300189737 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 27.rstmgr_leaf_rst_cnsty.41580949266733386043734365589831513850811562400606431174067770606274300189737
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.52372050907151265640345946217389443364781089540762165414745871631899334338182
Short name T497
Test name
Test status
Simulation time 243816210 ps
CPU time 1.15 seconds
Started Nov 22 12:40:46 PM PST 23
Finished Nov 22 12:40:48 PM PST 23
Peak memory 216788 kb
Host smart-8fca8fe3-a0b4-49a6-a7e0-7a0a008c84d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52372050907151265640345946217389443364781089540762165414745871631899334338182 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.52372050907151265640345946217389443364781089540762165414745871631899334338182
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.29172484454779385567412682544165765320039114658651215756999549107683021988004
Short name T291
Test name
Test status
Simulation time 230357768 ps
CPU time 0.95 seconds
Started Nov 22 12:40:33 PM PST 23
Finished Nov 22 12:40:36 PM PST 23
Peak memory 199568 kb
Host smart-8b78cc4f-dc3d-4f8b-934c-4cde4a465372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29172484454779385567412682544165765320039114658651215756999549107683021988004 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.rstmgr_por_stretcher.29172484454779385567412682544165765320039114658651215756999549107683021988004
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.40416801367516747125083849110834163189750687384390394749325794142282240346221
Short name T450
Test name
Test status
Simulation time 1729953098 ps
CPU time 6.76 seconds
Started Nov 22 12:40:59 PM PST 23
Finished Nov 22 12:41:06 PM PST 23
Peak memory 200080 kb
Host smart-0c493953-0b30-44c6-a18e-cd42b6f6b2da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40416801367516747125083849110834163189750687384390394749325794142282240346221 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 27.rstmgr_reset.40416801367516747125083849110834163189750687384390394749325794142282240346221
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.60814105503601233098057677839385881136741346607014405338434025731016948754688
Short name T300
Test name
Test status
Simulation time 170065619 ps
CPU time 1.23 seconds
Started Nov 22 12:40:38 PM PST 23
Finished Nov 22 12:40:40 PM PST 23
Peak memory 199512 kb
Host smart-2c5fff59-77a9-46d5-8409-2ce2d58d3909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60814105503601233098057677839385881136741346607014405338434025731016948754688 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.60814105503601233098057677839385881136741346607014405338434025731016948754688
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.17261401060800999109495919822046574790450697498314919846016581550549947744966
Short name T125
Test name
Test status
Simulation time 223941050 ps
CPU time 1.45 seconds
Started Nov 22 12:40:38 PM PST 23
Finished Nov 22 12:40:41 PM PST 23
Peak memory 200044 kb
Host smart-5ac4843c-03d2-4cc7-93b6-1d5408951573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17261401060800999109495919822046574790450697498314919846016581550549947744966 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 27.rstmgr_smoke.17261401060800999109495919822046574790450697498314919846016581550549947744966
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.24302570382897661779628366635601342802888111381304338036227249633618224040650
Short name T261
Test name
Test status
Simulation time 11131278308 ps
CPU time 37.88 seconds
Started Nov 22 12:40:47 PM PST 23
Finished Nov 22 12:41:25 PM PST 23
Peak memory 200068 kb
Host smart-376b9789-189c-4398-8b0f-66244ffe05b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24302570382897661779628366635601342802888111381304338036227249633618224040650 -assert nopos
tproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.24302570382897661779628366635601342802888111381304338036227249633618224040650
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.73227153617212787551849409808356328475124949109727193832574403986851404376572
Short name T314
Test name
Test status
Simulation time 473109710 ps
CPU time 2.69 seconds
Started Nov 22 12:40:59 PM PST 23
Finished Nov 22 12:41:02 PM PST 23
Peak memory 199848 kb
Host smart-e993fd63-29c9-4c1d-8ede-77310411b04a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73227153617212787551849409808356328475124949109727193832574403986851404376572 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 27.rstmgr_sw_rst.73227153617212787551849409808356328475124949109727193832574403986851404376572
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.24512335408190237329951152557205747488918023670705858313885311636686111115002
Short name T239
Test name
Test status
Simulation time 241232855 ps
CPU time 1.39 seconds
Started Nov 22 12:40:39 PM PST 23
Finished Nov 22 12:40:42 PM PST 23
Peak memory 199872 kb
Host smart-0e145670-6925-45bf-a1fc-ddd29d5de199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24512335408190237329951152557205747488918023670705858313885311636686111115002 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.rstmgr_sw_rst_reset_race.24512335408190237329951152557205747488918023670705858313885311636686111115002
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.12439521899467669275400531938921456123356077477729425795619627494882399308400
Short name T480
Test name
Test status
Simulation time 78981557 ps
CPU time 0.76 seconds
Started Nov 22 12:41:09 PM PST 23
Finished Nov 22 12:41:12 PM PST 23
Peak memory 199716 kb
Host smart-eb65ecf2-3ada-4cd0-9a40-89fa81085aaa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12439521899467669275400531938921456123356077477729425795619627494882399308400 -assert nopostpr
oc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.12439521899467669275400531938921456123356077477729425795619627494882399308400
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.39429272580942281482153921934168098111581688821521134065067691772270170942578
Short name T372
Test name
Test status
Simulation time 2162831562 ps
CPU time 7.94 seconds
Started Nov 22 12:40:54 PM PST 23
Finished Nov 22 12:41:04 PM PST 23
Peak memory 217004 kb
Host smart-c5736861-fb71-4257-ba87-565108415b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39429272580942281482153921934168098111581688821521134065067691772270170942578 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 28.rstmgr_leaf_rst_cnsty.39429272580942281482153921934168098111581688821521134065067691772270170942578
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.99108894676154933354145826211120590242129752161904258185007808970058807029149
Short name T489
Test name
Test status
Simulation time 243816210 ps
CPU time 1.06 seconds
Started Nov 22 12:40:54 PM PST 23
Finished Nov 22 12:40:56 PM PST 23
Peak memory 216848 kb
Host smart-e0b5630a-ca59-443c-89b4-4e85e28608d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99108894676154933354145826211120590242129752161904258185007808970058807029149 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.99108894676154933354145826211120590242129752161904258185007808970058807029149
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.7830399831899204273079551460936148138124064303174450064862081485942549650099
Short name T15
Test name
Test status
Simulation time 230357768 ps
CPU time 0.91 seconds
Started Nov 22 12:41:02 PM PST 23
Finished Nov 22 12:41:05 PM PST 23
Peak memory 199676 kb
Host smart-267b3651-ccf7-45ea-8d17-db0ae9faa272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7830399831899204273079551460936148138124064303174450064862081485942549650099 -assert nopostproc +UVM_TESTNAME=rstmgr_bas
e_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 28.rstmgr_por_stretcher.7830399831899204273079551460936148138124064303174450064862081485942549650099
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.30946447661670028316216062460256999885151515721330781790755725534058344993653
Short name T77
Test name
Test status
Simulation time 1729953098 ps
CPU time 6.47 seconds
Started Nov 22 12:41:21 PM PST 23
Finished Nov 22 12:41:29 PM PST 23
Peak memory 199988 kb
Host smart-7a9f883f-5bcb-4b42-9146-ad1bb5e991cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30946447661670028316216062460256999885151515721330781790755725534058344993653 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 28.rstmgr_reset.30946447661670028316216062460256999885151515721330781790755725534058344993653
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.54964496977864587262912374429677268213342659244633852138699889440889577636173
Short name T101
Test name
Test status
Simulation time 170065619 ps
CPU time 1.1 seconds
Started Nov 22 12:40:56 PM PST 23
Finished Nov 22 12:40:58 PM PST 23
Peak memory 199868 kb
Host smart-2029a633-460d-4c02-bbce-942b349bd29b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54964496977864587262912374429677268213342659244633852138699889440889577636173 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.54964496977864587262912374429677268213342659244633852138699889440889577636173
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.103171753536831009115739013429341100456191200758891199708728255088124499411289
Short name T292
Test name
Test status
Simulation time 223941050 ps
CPU time 1.4 seconds
Started Nov 22 12:40:43 PM PST 23
Finished Nov 22 12:40:46 PM PST 23
Peak memory 200020 kb
Host smart-6f9512c7-d77b-4014-9ac8-fd39f4d833d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103171753536831009115739013429341100456191200758891199708728255088124499411289 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 28.rstmgr_smoke.103171753536831009115739013429341100456191200758891199708728255088124499411289
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.38756278448905562450367240673509090974860901641321450117994824385029459753485
Short name T546
Test name
Test status
Simulation time 11131278308 ps
CPU time 40.06 seconds
Started Nov 22 12:40:53 PM PST 23
Finished Nov 22 12:41:34 PM PST 23
Peak memory 200068 kb
Host smart-e1f9be61-f18c-46e4-a3a9-f21c424ea292
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38756278448905562450367240673509090974860901641321450117994824385029459753485 -assert nopos
tproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.38756278448905562450367240673509090974860901641321450117994824385029459753485
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.71721460684063540377762373652327114151677383705354313491240976471442622742266
Short name T297
Test name
Test status
Simulation time 473109710 ps
CPU time 2.6 seconds
Started Nov 22 12:41:08 PM PST 23
Finished Nov 22 12:41:12 PM PST 23
Peak memory 199836 kb
Host smart-53edf398-febd-43e2-8d56-64679edfecac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71721460684063540377762373652327114151677383705354313491240976471442622742266 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 28.rstmgr_sw_rst.71721460684063540377762373652327114151677383705354313491240976471442622742266
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.110444773041266923900364124753659710161789237197751504024231270828740167352226
Short name T427
Test name
Test status
Simulation time 241232855 ps
CPU time 1.37 seconds
Started Nov 22 12:40:58 PM PST 23
Finished Nov 22 12:41:00 PM PST 23
Peak memory 199760 kb
Host smart-a4bcf642-77a6-4d3c-b55d-07d5b37f0abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110444773041266923900364124753659710161789237197751504024231270828740167352226 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 28.rstmgr_sw_rst_reset_race.110444773041266923900364124753659710161789237197751504024231270828740167352226
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.75421588857013825667676419758096689491741963419393352105453620509574305240041
Short name T353
Test name
Test status
Simulation time 78981557 ps
CPU time 0.76 seconds
Started Nov 22 12:41:25 PM PST 23
Finished Nov 22 12:41:27 PM PST 23
Peak memory 199720 kb
Host smart-ddc7480d-ae2a-4c1f-87c3-3fdccf9977d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75421588857013825667676419758096689491741963419393352105453620509574305240041 -assert nopostpr
oc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.75421588857013825667676419758096689491741963419393352105453620509574305240041
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.38593046820787736796849940992474023173994552202037923591012225460057769753518
Short name T140
Test name
Test status
Simulation time 2162831562 ps
CPU time 7.75 seconds
Started Nov 22 12:41:19 PM PST 23
Finished Nov 22 12:41:27 PM PST 23
Peak memory 217008 kb
Host smart-a3c12579-3260-48ec-8885-2938e5da53df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38593046820787736796849940992474023173994552202037923591012225460057769753518 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 29.rstmgr_leaf_rst_cnsty.38593046820787736796849940992474023173994552202037923591012225460057769753518
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.107337359184751580668844708799998706742293448116236767158139885880009187720364
Short name T304
Test name
Test status
Simulation time 243816210 ps
CPU time 1.12 seconds
Started Nov 22 12:41:33 PM PST 23
Finished Nov 22 12:41:35 PM PST 23
Peak memory 216868 kb
Host smart-cd9b2482-357f-4a91-b93e-8b15797d4256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107337359184751580668844708799998706742293448116236767158139885880009187720364 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.107337359184751580668844708799998706742293448116236767158139885880009187720364
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.93930437522466370739879372328494838825456471128512663895995289076539358002778
Short name T564
Test name
Test status
Simulation time 230357768 ps
CPU time 0.92 seconds
Started Nov 22 12:41:11 PM PST 23
Finished Nov 22 12:41:13 PM PST 23
Peak memory 199704 kb
Host smart-8e343ed2-53af-45b4-b5cf-2b85280dff97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93930437522466370739879372328494838825456471128512663895995289076539358002778 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.rstmgr_por_stretcher.93930437522466370739879372328494838825456471128512663895995289076539358002778
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.42484490604394466793359501041621771477328757426666004241567625633946758063347
Short name T568
Test name
Test status
Simulation time 1729953098 ps
CPU time 6.61 seconds
Started Nov 22 12:41:17 PM PST 23
Finished Nov 22 12:41:24 PM PST 23
Peak memory 200100 kb
Host smart-a820b050-7022-47f3-8597-390b41a4b018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42484490604394466793359501041621771477328757426666004241567625633946758063347 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 29.rstmgr_reset.42484490604394466793359501041621771477328757426666004241567625633946758063347
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.52380271541038348787717498567740417573502713809504379452674464187233956230430
Short name T102
Test name
Test status
Simulation time 170065619 ps
CPU time 1.17 seconds
Started Nov 22 12:41:08 PM PST 23
Finished Nov 22 12:41:11 PM PST 23
Peak memory 199724 kb
Host smart-db5ea847-2b78-4778-8725-d7269798acaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52380271541038348787717498567740417573502713809504379452674464187233956230430 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.52380271541038348787717498567740417573502713809504379452674464187233956230430
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.12267617132273165949302224171782423063521728657447740787832301878218397194103
Short name T550
Test name
Test status
Simulation time 223941050 ps
CPU time 1.48 seconds
Started Nov 22 12:41:09 PM PST 23
Finished Nov 22 12:41:16 PM PST 23
Peak memory 200028 kb
Host smart-d5923319-5093-474b-b74b-d0ab30714545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12267617132273165949302224171782423063521728657447740787832301878218397194103 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 29.rstmgr_smoke.12267617132273165949302224171782423063521728657447740787832301878218397194103
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.7063591408805120510410175772381822862434047287898796070530983184663832631845
Short name T416
Test name
Test status
Simulation time 11131278308 ps
CPU time 38.95 seconds
Started Nov 22 12:41:16 PM PST 23
Finished Nov 22 12:41:56 PM PST 23
Peak memory 199988 kb
Host smart-4d1e8d16-2526-4fc3-b868-64f85d390824
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7063591408805120510410175772381822862434047287898796070530983184663832631845 -assert nopost
proc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.7063591408805120510410175772381822862434047287898796070530983184663832631845
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.51733174971692266628877450057816971837424875230213569154308515887053880731034
Short name T373
Test name
Test status
Simulation time 241232855 ps
CPU time 1.42 seconds
Started Nov 22 12:41:28 PM PST 23
Finished Nov 22 12:41:31 PM PST 23
Peak memory 199896 kb
Host smart-35124f0a-5cb8-42eb-ae80-d4af05974963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51733174971692266628877450057816971837424875230213569154308515887053880731034 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.rstmgr_sw_rst_reset_race.51733174971692266628877450057816971837424875230213569154308515887053880731034
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.40276516119863313896735929363203405785165504823798623279674406228772629999460
Short name T587
Test name
Test status
Simulation time 78981557 ps
CPU time 0.76 seconds
Started Nov 22 12:39:36 PM PST 23
Finished Nov 22 12:39:40 PM PST 23
Peak memory 199592 kb
Host smart-6ff9da41-07d4-4dfb-89f4-07d12e572b4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40276516119863313896735929363203405785165504823798623279674406228772629999460 -assert nopostpr
oc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.40276516119863313896735929363203405785165504823798623279674406228772629999460
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.64956338244605501521037014981201973314695715795530073172016676339952918978715
Short name T25
Test name
Test status
Simulation time 2162831562 ps
CPU time 7.97 seconds
Started Nov 22 12:39:37 PM PST 23
Finished Nov 22 12:39:49 PM PST 23
Peak memory 216964 kb
Host smart-466a2442-af28-4256-a932-ae77b9d0aa55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64956338244605501521037014981201973314695715795530073172016676339952918978715 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 3.rstmgr_leaf_rst_cnsty.64956338244605501521037014981201973314695715795530073172016676339952918978715
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.58304859596662160995959180617619887929746395003804570078059918834681612027586
Short name T606
Test name
Test status
Simulation time 243816210 ps
CPU time 1.1 seconds
Started Nov 22 12:39:30 PM PST 23
Finished Nov 22 12:39:34 PM PST 23
Peak memory 216868 kb
Host smart-6d9c0c3f-7bc5-4ebe-983b-591c38a7f0da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58304859596662160995959180617619887929746395003804570078059918834681612027586 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.58304859596662160995959180617619887929746395003804570078059918834681612027586
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.104588669491086605536380239422972051690977075313149394835257269034311699749340
Short name T127
Test name
Test status
Simulation time 230357768 ps
CPU time 0.91 seconds
Started Nov 22 12:39:31 PM PST 23
Finished Nov 22 12:39:35 PM PST 23
Peak memory 199696 kb
Host smart-569b3794-3735-4859-8013-daf574206159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104588669491086605536380239422972051690977075313149394835257269034311699749340 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 3.rstmgr_por_stretcher.104588669491086605536380239422972051690977075313149394835257269034311699749340
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.25628275226772955696718089665631363204899910724321090891710162835470311805805
Short name T313
Test name
Test status
Simulation time 1729953098 ps
CPU time 7.29 seconds
Started Nov 22 12:39:52 PM PST 23
Finished Nov 22 12:40:00 PM PST 23
Peak memory 200056 kb
Host smart-c627df4f-2d4d-4a0e-8eb0-594dbc62cf0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25628275226772955696718089665631363204899910724321090891710162835470311805805 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 3.rstmgr_reset.25628275226772955696718089665631363204899910724321090891710162835470311805805
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.69435737913649305122942391388421124889793192416218572766581082397850056971098
Short name T56
Test name
Test status
Simulation time 8294713949 ps
CPU time 14.42 seconds
Started Nov 22 12:39:31 PM PST 23
Finished Nov 22 12:39:49 PM PST 23
Peak memory 216648 kb
Host smart-ffe4dc98-84e8-49a5-b59d-0caa9bb55925
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69435737913649305122942391388421124889793192416218572766581082397850056971098 -assert nopostpro
c +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.69435737913649305122942391388421124889793192416218572766581082397850056971098
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.103190006440681071290938412433737880850846288014171739104228312120099526165422
Short name T415
Test name
Test status
Simulation time 170065619 ps
CPU time 1.23 seconds
Started Nov 22 12:39:32 PM PST 23
Finished Nov 22 12:39:36 PM PST 23
Peak memory 199752 kb
Host smart-f3febf2a-78e9-44c7-bc3f-def7661c8bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103190006440681071290938412433737880850846288014171739104228312120099526165422 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.103190006440681071290938412433737880850846288014171739104228312120099526165422
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.57263755112865198461444245817154156533310511476407761154771879721290030725265
Short name T526
Test name
Test status
Simulation time 223941050 ps
CPU time 1.46 seconds
Started Nov 22 12:39:43 PM PST 23
Finished Nov 22 12:39:47 PM PST 23
Peak memory 200052 kb
Host smart-34ee2d7c-66dd-49fc-92e4-1a8114bee7f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57263755112865198461444245817154156533310511476407761154771879721290030725265 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 3.rstmgr_smoke.57263755112865198461444245817154156533310511476407761154771879721290030725265
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.105597397806396629058390182376982963068453133345301934282458048951394142324922
Short name T548
Test name
Test status
Simulation time 11131278308 ps
CPU time 41.15 seconds
Started Nov 22 12:39:33 PM PST 23
Finished Nov 22 12:40:17 PM PST 23
Peak memory 199948 kb
Host smart-80664945-e771-47bf-aa06-917637a68b21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105597397806396629058390182376982963068453133345301934282458048951394142324922 -assert nopo
stproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.105597397806396629058390182376982963068453133345301934282458048951394142324922
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.57814375097807588718940951749332039320058538761162018494980651328664159334064
Short name T312
Test name
Test status
Simulation time 473109710 ps
CPU time 2.88 seconds
Started Nov 22 12:39:28 PM PST 23
Finished Nov 22 12:39:32 PM PST 23
Peak memory 199740 kb
Host smart-a9ca53df-945c-40d0-8f9b-9713e49ca142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57814375097807588718940951749332039320058538761162018494980651328664159334064 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 3.rstmgr_sw_rst.57814375097807588718940951749332039320058538761162018494980651328664159334064
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.89600470120822439976580189247106757216436447299935536119446279058576327361468
Short name T574
Test name
Test status
Simulation time 241232855 ps
CPU time 1.46 seconds
Started Nov 22 12:39:40 PM PST 23
Finished Nov 22 12:39:46 PM PST 23
Peak memory 199864 kb
Host smart-9a4877f7-6e2b-46e7-a021-58b0d88fcf33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89600470120822439976580189247106757216436447299935536119446279058576327361468 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.rstmgr_sw_rst_reset_race.89600470120822439976580189247106757216436447299935536119446279058576327361468
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.15345172143466669454630807832319222536288650220297058107331093524911085352114
Short name T425
Test name
Test status
Simulation time 78981557 ps
CPU time 0.76 seconds
Started Nov 22 12:40:32 PM PST 23
Finished Nov 22 12:40:34 PM PST 23
Peak memory 199668 kb
Host smart-6dcdde57-9c7d-4d03-b05d-c6ff378df407
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15345172143466669454630807832319222536288650220297058107331093524911085352114 -assert nopostpr
oc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.15345172143466669454630807832319222536288650220297058107331093524911085352114
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.40673269139345025480123067600672417775671976490368292238100552904274568365495
Short name T576
Test name
Test status
Simulation time 2162831562 ps
CPU time 8.18 seconds
Started Nov 22 12:40:43 PM PST 23
Finished Nov 22 12:40:53 PM PST 23
Peak memory 217076 kb
Host smart-9c3b3b15-d659-4fde-896e-12c96dedf0a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40673269139345025480123067600672417775671976490368292238100552904274568365495 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 30.rstmgr_leaf_rst_cnsty.40673269139345025480123067600672417775671976490368292238100552904274568365495
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.19541576297525694870722996054055369454175223254268754020765811945724029080855
Short name T613
Test name
Test status
Simulation time 243816210 ps
CPU time 1.08 seconds
Started Nov 22 12:40:42 PM PST 23
Finished Nov 22 12:40:44 PM PST 23
Peak memory 216716 kb
Host smart-627a8cb3-8800-4cfd-abe2-f1e5a00af155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19541576297525694870722996054055369454175223254268754020765811945724029080855 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.19541576297525694870722996054055369454175223254268754020765811945724029080855
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.60295132128066435630692308234493616452116148384309071758466119061721253342116
Short name T18
Test name
Test status
Simulation time 230357768 ps
CPU time 0.95 seconds
Started Nov 22 12:40:42 PM PST 23
Finished Nov 22 12:40:45 PM PST 23
Peak memory 199568 kb
Host smart-7003c408-9fe7-4bf1-9ac1-db68f5a47847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60295132128066435630692308234493616452116148384309071758466119061721253342116 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.rstmgr_por_stretcher.60295132128066435630692308234493616452116148384309071758466119061721253342116
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.107807084517121320776946638265722474218216538392052854189611063053937537465335
Short name T319
Test name
Test status
Simulation time 1729953098 ps
CPU time 6.4 seconds
Started Nov 22 12:40:55 PM PST 23
Finished Nov 22 12:41:03 PM PST 23
Peak memory 200036 kb
Host smart-3cfdcf1c-bbe9-442b-8389-52b5cda94db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107807084517121320776946638265722474218216538392052854189611063053937537465335 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 30.rstmgr_reset.107807084517121320776946638265722474218216538392052854189611063053937537465335
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.67224207506277104121505813614224081523806984107722114454888056374462218790450
Short name T143
Test name
Test status
Simulation time 170065619 ps
CPU time 1.2 seconds
Started Nov 22 12:40:45 PM PST 23
Finished Nov 22 12:40:48 PM PST 23
Peak memory 199856 kb
Host smart-a2667498-34dc-48a4-8e7a-b6bd1eda2f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67224207506277104121505813614224081523806984107722114454888056374462218790450 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.67224207506277104121505813614224081523806984107722114454888056374462218790450
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.920346873413691785071487307458737874817186149236180537148241848206943795122
Short name T242
Test name
Test status
Simulation time 223941050 ps
CPU time 1.45 seconds
Started Nov 22 12:40:44 PM PST 23
Finished Nov 22 12:40:47 PM PST 23
Peak memory 200008 kb
Host smart-f5068c68-ef36-4a04-aec9-1a32c7631be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920346873413691785071487307458737874817186149236180537148241848206943795122 -assert nopostproc +UVM_TESTNAME=rstmgr_base
_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 30.rstmgr_smoke.920346873413691785071487307458737874817186149236180537148241848206943795122
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.6986347153013766058822798643292515033171475152475132780284368433711394254680
Short name T355
Test name
Test status
Simulation time 11131278308 ps
CPU time 37.91 seconds
Started Nov 22 12:40:35 PM PST 23
Finished Nov 22 12:41:15 PM PST 23
Peak memory 200000 kb
Host smart-07b55611-32f6-4683-9ac7-4c56fe40a039
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6986347153013766058822798643292515033171475152475132780284368433711394254680 -assert nopost
proc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.6986347153013766058822798643292515033171475152475132780284368433711394254680
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.6350288205911680541531748820337819273552270614309668264701705039538697895485
Short name T476
Test name
Test status
Simulation time 473109710 ps
CPU time 2.59 seconds
Started Nov 22 12:40:35 PM PST 23
Finished Nov 22 12:40:39 PM PST 23
Peak memory 199764 kb
Host smart-75aa9240-9a5c-46b9-9439-0b9d75deb75a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6350288205911680541531748820337819273552270614309668264701705039538697895485 -assert nopostproc +UVM_TESTNAME=rstmgr_bas
e_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 30.rstmgr_sw_rst.6350288205911680541531748820337819273552270614309668264701705039538697895485
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.41344577552995566843418676586120581574622307923532876810318982148597119843131
Short name T513
Test name
Test status
Simulation time 241232855 ps
CPU time 1.46 seconds
Started Nov 22 12:40:31 PM PST 23
Finished Nov 22 12:40:34 PM PST 23
Peak memory 199888 kb
Host smart-0c316b9f-1352-423d-818c-11f2259911e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41344577552995566843418676586120581574622307923532876810318982148597119843131 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.rstmgr_sw_rst_reset_race.41344577552995566843418676586120581574622307923532876810318982148597119843131
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.18210137203633430969843272319611481803078704739183066049758640215976694109658
Short name T99
Test name
Test status
Simulation time 78981557 ps
CPU time 0.81 seconds
Started Nov 22 12:41:10 PM PST 23
Finished Nov 22 12:41:12 PM PST 23
Peak memory 199672 kb
Host smart-c4d473b0-fa5f-4208-99dd-7e07cf893150
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18210137203633430969843272319611481803078704739183066049758640215976694109658 -assert nopostpr
oc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.18210137203633430969843272319611481803078704739183066049758640215976694109658
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.50755517120496755311506120874838604076340358298799488812561579881922542932518
Short name T375
Test name
Test status
Simulation time 2162831562 ps
CPU time 8.25 seconds
Started Nov 22 12:41:07 PM PST 23
Finished Nov 22 12:41:17 PM PST 23
Peak memory 217124 kb
Host smart-e2839963-d9f2-4071-889c-447adbb27682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50755517120496755311506120874838604076340358298799488812561579881922542932518 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 31.rstmgr_leaf_rst_cnsty.50755517120496755311506120874838604076340358298799488812561579881922542932518
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.70399798408014492274468763332964985796817656864311607958257019377484770637914
Short name T128
Test name
Test status
Simulation time 243816210 ps
CPU time 1.09 seconds
Started Nov 22 12:41:03 PM PST 23
Finished Nov 22 12:41:06 PM PST 23
Peak memory 216816 kb
Host smart-f98110ca-8c7e-4982-9c3e-273ff22d2a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70399798408014492274468763332964985796817656864311607958257019377484770637914 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.70399798408014492274468763332964985796817656864311607958257019377484770637914
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.93028094806862193351904342016062492148137348347581659598985445186626510615118
Short name T534
Test name
Test status
Simulation time 230357768 ps
CPU time 1 seconds
Started Nov 22 12:40:37 PM PST 23
Finished Nov 22 12:40:40 PM PST 23
Peak memory 199660 kb
Host smart-1f0bc495-17ad-4cf4-be35-8d1e33f459a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93028094806862193351904342016062492148137348347581659598985445186626510615118 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.rstmgr_por_stretcher.93028094806862193351904342016062492148137348347581659598985445186626510615118
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.79170543057022102423806668413271946621438471297730232339713227370680880188112
Short name T246
Test name
Test status
Simulation time 1729953098 ps
CPU time 6.68 seconds
Started Nov 22 12:40:54 PM PST 23
Finished Nov 22 12:41:02 PM PST 23
Peak memory 200052 kb
Host smart-495019ed-0eb9-40c1-8972-05cd74ad0b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79170543057022102423806668413271946621438471297730232339713227370680880188112 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 31.rstmgr_reset.79170543057022102423806668413271946621438471297730232339713227370680880188112
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.99084491027302990096229529895256870978263484926040483737821754918617835608087
Short name T141
Test name
Test status
Simulation time 170065619 ps
CPU time 1.16 seconds
Started Nov 22 12:41:03 PM PST 23
Finished Nov 22 12:41:05 PM PST 23
Peak memory 199916 kb
Host smart-a8399e75-b739-4fc2-994c-3ecf75176e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99084491027302990096229529895256870978263484926040483737821754918617835608087 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.99084491027302990096229529895256870978263484926040483737821754918617835608087
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.103874289053438738091516231609554961113488920877616481710847807773064747398029
Short name T240
Test name
Test status
Simulation time 223941050 ps
CPU time 1.5 seconds
Started Nov 22 12:40:38 PM PST 23
Finished Nov 22 12:40:40 PM PST 23
Peak memory 200020 kb
Host smart-60b35bc3-91f0-4d21-8308-4e9b6b7a4327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103874289053438738091516231609554961113488920877616481710847807773064747398029 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 31.rstmgr_smoke.103874289053438738091516231609554961113488920877616481710847807773064747398029
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.74749959902139645543213234721168110184837092674901073440949513436438182611417
Short name T566
Test name
Test status
Simulation time 11131278308 ps
CPU time 37.87 seconds
Started Nov 22 12:40:55 PM PST 23
Finished Nov 22 12:41:34 PM PST 23
Peak memory 200000 kb
Host smart-5bc8b685-8d91-4989-b829-09bebc480a6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74749959902139645543213234721168110184837092674901073440949513436438182611417 -assert nopos
tproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.74749959902139645543213234721168110184837092674901073440949513436438182611417
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.102261725135869103489378647752727411455634073406824955200659925781368144643894
Short name T262
Test name
Test status
Simulation time 473109710 ps
CPU time 2.69 seconds
Started Nov 22 12:40:38 PM PST 23
Finished Nov 22 12:40:42 PM PST 23
Peak memory 199720 kb
Host smart-6072ec9e-bff5-4d83-8e6c-8e4dd9303f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102261725135869103489378647752727411455634073406824955200659925781368144643894 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 31.rstmgr_sw_rst.102261725135869103489378647752727411455634073406824955200659925781368144643894
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.38888882941427612787325673698068513028665644874183065956953667162048526751805
Short name T13
Test name
Test status
Simulation time 241232855 ps
CPU time 1.41 seconds
Started Nov 22 12:40:38 PM PST 23
Finished Nov 22 12:40:41 PM PST 23
Peak memory 199756 kb
Host smart-64e7023b-679e-441d-8870-3a07827b813d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38888882941427612787325673698068513028665644874183065956953667162048526751805 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.rstmgr_sw_rst_reset_race.38888882941427612787325673698068513028665644874183065956953667162048526751805
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.18848711686884996918229195021094456498953892574616514873783178968667675479149
Short name T376
Test name
Test status
Simulation time 78981557 ps
CPU time 0.74 seconds
Started Nov 22 12:41:06 PM PST 23
Finished Nov 22 12:41:09 PM PST 23
Peak memory 199600 kb
Host smart-2c550207-ddaa-4d87-9963-1ed8099e3165
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18848711686884996918229195021094456498953892574616514873783178968667675479149 -assert nopostpr
oc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.18848711686884996918229195021094456498953892574616514873783178968667675479149
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.88605812602284647202354561834784833605344624519448965075508817983927575180161
Short name T383
Test name
Test status
Simulation time 2162831562 ps
CPU time 7.86 seconds
Started Nov 22 12:41:16 PM PST 23
Finished Nov 22 12:41:25 PM PST 23
Peak memory 216980 kb
Host smart-29301911-b54a-4bdf-898f-f6476a92be46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88605812602284647202354561834784833605344624519448965075508817983927575180161 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 32.rstmgr_leaf_rst_cnsty.88605812602284647202354561834784833605344624519448965075508817983927575180161
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.70247274991425995957203285747459646318660898916760020342997658130990440369809
Short name T593
Test name
Test status
Simulation time 243816210 ps
CPU time 1.08 seconds
Started Nov 22 12:41:15 PM PST 23
Finished Nov 22 12:41:17 PM PST 23
Peak memory 216848 kb
Host smart-ffb4e398-7ce6-4758-b477-25ed3e18abaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70247274991425995957203285747459646318660898916760020342997658130990440369809 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.70247274991425995957203285747459646318660898916760020342997658130990440369809
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.19597735832028675443852317938524430908516027452552847752012151762510304918433
Short name T358
Test name
Test status
Simulation time 230357768 ps
CPU time 0.92 seconds
Started Nov 22 12:40:50 PM PST 23
Finished Nov 22 12:40:52 PM PST 23
Peak memory 199572 kb
Host smart-bac6b244-0715-408c-a94c-5e4b2bd4852b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19597735832028675443852317938524430908516027452552847752012151762510304918433 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.rstmgr_por_stretcher.19597735832028675443852317938524430908516027452552847752012151762510304918433
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.67648385672329026908102223147858497358277530837215474071685233150903877689002
Short name T325
Test name
Test status
Simulation time 1729953098 ps
CPU time 6.89 seconds
Started Nov 22 12:41:03 PM PST 23
Finished Nov 22 12:41:12 PM PST 23
Peak memory 200112 kb
Host smart-e0325a5a-ecb0-483b-9805-22471afecc33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67648385672329026908102223147858497358277530837215474071685233150903877689002 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 32.rstmgr_reset.67648385672329026908102223147858497358277530837215474071685233150903877689002
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.33107012086640437976502697525169999289442098191809096764197378473791963069505
Short name T330
Test name
Test status
Simulation time 170065619 ps
CPU time 1.17 seconds
Started Nov 22 12:41:22 PM PST 23
Finished Nov 22 12:41:24 PM PST 23
Peak memory 199916 kb
Host smart-18dfb8a5-b364-4375-91c6-0a2eb5d0cc6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33107012086640437976502697525169999289442098191809096764197378473791963069505 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.33107012086640437976502697525169999289442098191809096764197378473791963069505
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.27469355293784462870545912520664209960030407032445317046050700887539631007409
Short name T310
Test name
Test status
Simulation time 223941050 ps
CPU time 1.5 seconds
Started Nov 22 12:40:51 PM PST 23
Finished Nov 22 12:40:53 PM PST 23
Peak memory 200012 kb
Host smart-52e9a2b3-55f3-49d4-81f9-6e45b1e3673f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27469355293784462870545912520664209960030407032445317046050700887539631007409 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 32.rstmgr_smoke.27469355293784462870545912520664209960030407032445317046050700887539631007409
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.39356768084180984363369777265024216207606136980677454515659233321856335816581
Short name T346
Test name
Test status
Simulation time 11131278308 ps
CPU time 38.35 seconds
Started Nov 22 12:40:51 PM PST 23
Finished Nov 22 12:41:30 PM PST 23
Peak memory 200088 kb
Host smart-af1e7847-b511-4efb-b206-a01e7fee97c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39356768084180984363369777265024216207606136980677454515659233321856335816581 -assert nopos
tproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.39356768084180984363369777265024216207606136980677454515659233321856335816581
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.72853976187623604067813562261614720569130842327952358411477405688956081973589
Short name T301
Test name
Test status
Simulation time 473109710 ps
CPU time 2.71 seconds
Started Nov 22 12:40:46 PM PST 23
Finished Nov 22 12:40:49 PM PST 23
Peak memory 199888 kb
Host smart-c3c69aae-8515-42bb-9eef-345b602e1776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72853976187623604067813562261614720569130842327952358411477405688956081973589 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 32.rstmgr_sw_rst.72853976187623604067813562261614720569130842327952358411477405688956081973589
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.66237616974706647461472554571796874713624635055486828880210081690127445574282
Short name T397
Test name
Test status
Simulation time 241232855 ps
CPU time 1.34 seconds
Started Nov 22 12:41:02 PM PST 23
Finished Nov 22 12:41:05 PM PST 23
Peak memory 199884 kb
Host smart-ef58bb7f-de28-45fd-8696-35c8d20d4249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66237616974706647461472554571796874713624635055486828880210081690127445574282 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 32.rstmgr_sw_rst_reset_race.66237616974706647461472554571796874713624635055486828880210081690127445574282
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.78895598535916137719686337978563215662683895589279357842999271841415392750120
Short name T331
Test name
Test status
Simulation time 78981557 ps
CPU time 0.76 seconds
Started Nov 22 12:40:51 PM PST 23
Finished Nov 22 12:40:53 PM PST 23
Peak memory 199668 kb
Host smart-89dae909-62d0-47ef-871f-047fd2818d5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78895598535916137719686337978563215662683895589279357842999271841415392750120 -assert nopostpr
oc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.78895598535916137719686337978563215662683895589279357842999271841415392750120
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.16147259731003505487085232015073169469795829701762847498237222940891254318299
Short name T385
Test name
Test status
Simulation time 2162831562 ps
CPU time 8.32 seconds
Started Nov 22 12:41:15 PM PST 23
Finished Nov 22 12:41:25 PM PST 23
Peak memory 217120 kb
Host smart-b8907b49-e78e-4a59-af3a-e4f04e71fe30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16147259731003505487085232015073169469795829701762847498237222940891254318299 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 33.rstmgr_leaf_rst_cnsty.16147259731003505487085232015073169469795829701762847498237222940891254318299
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.3443454773113657677139009784574877313358940281004905224962027757740522706385
Short name T580
Test name
Test status
Simulation time 243816210 ps
CPU time 1.1 seconds
Started Nov 22 12:41:17 PM PST 23
Finished Nov 22 12:41:19 PM PST 23
Peak memory 216852 kb
Host smart-0a7eb5fa-549c-44a0-a0b3-a2a000c1924b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443454773113657677139009784574877313358940281004905224962027757740522706385 -assert nopostproc +UVM_TESTNAME=rstmgr_bas
e_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.3443454773113657677139009784574877313358940281004905224962027757740522706385
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.98958713440867542467324212421200384446887086966147366763708705428960745537608
Short name T461
Test name
Test status
Simulation time 230357768 ps
CPU time 0.97 seconds
Started Nov 22 12:41:23 PM PST 23
Finished Nov 22 12:41:25 PM PST 23
Peak memory 199688 kb
Host smart-7ff6a0fe-1d0c-4116-a89d-d2d4a815c4ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98958713440867542467324212421200384446887086966147366763708705428960745537608 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.rstmgr_por_stretcher.98958713440867542467324212421200384446887086966147366763708705428960745537608
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.58509315625798571728796013465284429795363907137953468039246893693405134254636
Short name T5
Test name
Test status
Simulation time 1729953098 ps
CPU time 6.58 seconds
Started Nov 22 12:41:14 PM PST 23
Finished Nov 22 12:41:22 PM PST 23
Peak memory 200032 kb
Host smart-858024f4-99a0-4b15-95da-42c0b69b0027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58509315625798571728796013465284429795363907137953468039246893693405134254636 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 33.rstmgr_reset.58509315625798571728796013465284429795363907137953468039246893693405134254636
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.105102993364549809570347228917973429795651529783713457059591501065855586714822
Short name T411
Test name
Test status
Simulation time 170065619 ps
CPU time 1.14 seconds
Started Nov 22 12:41:15 PM PST 23
Finished Nov 22 12:41:17 PM PST 23
Peak memory 199864 kb
Host smart-2cf342a2-1b55-416e-9590-333dc3bc1c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105102993364549809570347228917973429795651529783713457059591501065855586714822 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.105102993364549809570347228917973429795651529783713457059591501065855586714822
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.45380907309737817913808298808766412339208204806617315730930983276998848213726
Short name T274
Test name
Test status
Simulation time 223941050 ps
CPU time 1.4 seconds
Started Nov 22 12:41:05 PM PST 23
Finished Nov 22 12:41:09 PM PST 23
Peak memory 199940 kb
Host smart-0c178118-3f24-4d16-9343-5ae14a039c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45380907309737817913808298808766412339208204806617315730930983276998848213726 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 33.rstmgr_smoke.45380907309737817913808298808766412339208204806617315730930983276998848213726
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.34240544703851370642155876844073052126827995348105500169029094782156458304808
Short name T279
Test name
Test status
Simulation time 11131278308 ps
CPU time 40.37 seconds
Started Nov 22 12:40:47 PM PST 23
Finished Nov 22 12:41:29 PM PST 23
Peak memory 200052 kb
Host smart-5e766bf7-590c-4ae6-9230-f758148912ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34240544703851370642155876844073052126827995348105500169029094782156458304808 -assert nopos
tproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.34240544703851370642155876844073052126827995348105500169029094782156458304808
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.6322875306452026805104923935748101776538437986625216921336087764433039923100
Short name T377
Test name
Test status
Simulation time 473109710 ps
CPU time 2.58 seconds
Started Nov 22 12:40:46 PM PST 23
Finished Nov 22 12:40:50 PM PST 23
Peak memory 199832 kb
Host smart-b09991f3-8ca2-4066-8f17-1c0f2fc7cfd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6322875306452026805104923935748101776538437986625216921336087764433039923100 -assert nopostproc +UVM_TESTNAME=rstmgr_bas
e_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 33.rstmgr_sw_rst.6322875306452026805104923935748101776538437986625216921336087764433039923100
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.40519245574581060966954037691440546466266596824911668273003076643771785328505
Short name T236
Test name
Test status
Simulation time 241232855 ps
CPU time 1.35 seconds
Started Nov 22 12:41:10 PM PST 23
Finished Nov 22 12:41:13 PM PST 23
Peak memory 199788 kb
Host smart-014b3605-df5d-4e25-a5e1-017993763058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40519245574581060966954037691440546466266596824911668273003076643771785328505 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 33.rstmgr_sw_rst_reset_race.40519245574581060966954037691440546466266596824911668273003076643771785328505
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.27648087612426266094367399719076018904662002851253083046858068203442681721087
Short name T270
Test name
Test status
Simulation time 78981557 ps
CPU time 0.92 seconds
Started Nov 22 12:41:05 PM PST 23
Finished Nov 22 12:41:08 PM PST 23
Peak memory 199652 kb
Host smart-7aadc28a-c082-4798-8cbe-7f4e01481782
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27648087612426266094367399719076018904662002851253083046858068203442681721087 -assert nopostpr
oc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.27648087612426266094367399719076018904662002851253083046858068203442681721087
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.35544980167715664089834732258200369355579044929014157080737563774895480737350
Short name T532
Test name
Test status
Simulation time 2162831562 ps
CPU time 8.53 seconds
Started Nov 22 12:41:14 PM PST 23
Finished Nov 22 12:41:24 PM PST 23
Peak memory 217076 kb
Host smart-fa1b94d4-311f-4415-8fb2-df57e461efd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35544980167715664089834732258200369355579044929014157080737563774895480737350 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 34.rstmgr_leaf_rst_cnsty.35544980167715664089834732258200369355579044929014157080737563774895480737350
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.106400407214036115210799579034770947398501640299785324203679458627865698028978
Short name T252
Test name
Test status
Simulation time 243816210 ps
CPU time 1.08 seconds
Started Nov 22 12:40:52 PM PST 23
Finished Nov 22 12:40:54 PM PST 23
Peak memory 216760 kb
Host smart-e931abdb-024a-4c92-8630-505e0aed1ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106400407214036115210799579034770947398501640299785324203679458627865698028978 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.106400407214036115210799579034770947398501640299785324203679458627865698028978
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.88254571818905467476691001695331169347090276569130418835401219389800938304592
Short name T132
Test name
Test status
Simulation time 230357768 ps
CPU time 0.94 seconds
Started Nov 22 12:40:53 PM PST 23
Finished Nov 22 12:40:55 PM PST 23
Peak memory 199644 kb
Host smart-729972e2-2cd2-4e03-99e6-4572066b8a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88254571818905467476691001695331169347090276569130418835401219389800938304592 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.rstmgr_por_stretcher.88254571818905467476691001695331169347090276569130418835401219389800938304592
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.79685346525321523437050833243002456917245883351532780205413233891209381316371
Short name T111
Test name
Test status
Simulation time 1729953098 ps
CPU time 6.88 seconds
Started Nov 22 12:40:49 PM PST 23
Finished Nov 22 12:40:57 PM PST 23
Peak memory 200092 kb
Host smart-a31f11a8-585e-4714-8f7e-2d23bd6e8b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79685346525321523437050833243002456917245883351532780205413233891209381316371 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 34.rstmgr_reset.79685346525321523437050833243002456917245883351532780205413233891209381316371
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.46295594356965250067323131071909650130409773876711003860663807976854201108449
Short name T316
Test name
Test status
Simulation time 170065619 ps
CPU time 1.13 seconds
Started Nov 22 12:41:03 PM PST 23
Finished Nov 22 12:41:05 PM PST 23
Peak memory 199904 kb
Host smart-92db63e6-f2b5-409b-97ef-cce2a9bd5f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46295594356965250067323131071909650130409773876711003860663807976854201108449 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.46295594356965250067323131071909650130409773876711003860663807976854201108449
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.67680724788479098077608270329689912587421288758005065444877346481256499061543
Short name T413
Test name
Test status
Simulation time 223941050 ps
CPU time 1.42 seconds
Started Nov 22 12:40:48 PM PST 23
Finished Nov 22 12:40:50 PM PST 23
Peak memory 200044 kb
Host smart-1f2c7c65-5d2e-4c32-be0d-c2bb5fe7a64d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67680724788479098077608270329689912587421288758005065444877346481256499061543 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 34.rstmgr_smoke.67680724788479098077608270329689912587421288758005065444877346481256499061543
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.64029205169003076885789603727549180788529338884258108484989914593499494585282
Short name T505
Test name
Test status
Simulation time 11131278308 ps
CPU time 39.02 seconds
Started Nov 22 12:41:14 PM PST 23
Finished Nov 22 12:41:54 PM PST 23
Peak memory 200120 kb
Host smart-855be8c6-3fd0-456f-8959-a9e3a102cfba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64029205169003076885789603727549180788529338884258108484989914593499494585282 -assert nopos
tproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.64029205169003076885789603727549180788529338884258108484989914593499494585282
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.22895242968125357584610847284269362883714381816662413821002909181984264230698
Short name T290
Test name
Test status
Simulation time 473109710 ps
CPU time 2.65 seconds
Started Nov 22 12:40:49 PM PST 23
Finished Nov 22 12:40:53 PM PST 23
Peak memory 199828 kb
Host smart-8e9633a7-beea-42ca-9ab0-3936949c00c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22895242968125357584610847284269362883714381816662413821002909181984264230698 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 34.rstmgr_sw_rst.22895242968125357584610847284269362883714381816662413821002909181984264230698
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.86113130220148738133761334754645790396386365136440051123688410784734449548378
Short name T417
Test name
Test status
Simulation time 241232855 ps
CPU time 1.37 seconds
Started Nov 22 12:40:51 PM PST 23
Finished Nov 22 12:40:53 PM PST 23
Peak memory 199888 kb
Host smart-92c2023e-b7fc-4d49-a09e-9116e9b23f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86113130220148738133761334754645790396386365136440051123688410784734449548378 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 34.rstmgr_sw_rst_reset_race.86113130220148738133761334754645790396386365136440051123688410784734449548378
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.92008476191517253992401764054032406084316016106151539584479442171968558065042
Short name T498
Test name
Test status
Simulation time 78981557 ps
CPU time 0.78 seconds
Started Nov 22 12:41:35 PM PST 23
Finished Nov 22 12:41:36 PM PST 23
Peak memory 199720 kb
Host smart-22b2dfb1-97d0-4dc5-a516-134f7598eebc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92008476191517253992401764054032406084316016106151539584479442171968558065042 -assert nopostpr
oc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.92008476191517253992401764054032406084316016106151539584479442171968558065042
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.97957708202512437095926790901081611001768901295207202125823576393437109320397
Short name T30
Test name
Test status
Simulation time 2162831562 ps
CPU time 7.79 seconds
Started Nov 22 12:41:25 PM PST 23
Finished Nov 22 12:41:34 PM PST 23
Peak memory 217116 kb
Host smart-df3ece4f-1a1e-4673-9cc3-a487a5167046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97957708202512437095926790901081611001768901295207202125823576393437109320397 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 35.rstmgr_leaf_rst_cnsty.97957708202512437095926790901081611001768901295207202125823576393437109320397
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.113170426137263704795895768085158086209932009923175225165548426730464758588846
Short name T399
Test name
Test status
Simulation time 243816210 ps
CPU time 1.05 seconds
Started Nov 22 12:41:12 PM PST 23
Finished Nov 22 12:41:14 PM PST 23
Peak memory 216848 kb
Host smart-51d949c0-7de4-4496-a30d-9fa3fc2745b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113170426137263704795895768085158086209932009923175225165548426730464758588846 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.113170426137263704795895768085158086209932009923175225165548426730464758588846
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.3361097152515408945350232662951854623293328111337560804794397579445817389060
Short name T555
Test name
Test status
Simulation time 230357768 ps
CPU time 0.93 seconds
Started Nov 22 12:41:31 PM PST 23
Finished Nov 22 12:41:33 PM PST 23
Peak memory 199688 kb
Host smart-6d7a8a0e-7372-4956-9d57-c19e433d508d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361097152515408945350232662951854623293328111337560804794397579445817389060 -assert nopostproc +UVM_TESTNAME=rstmgr_bas
e_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 35.rstmgr_por_stretcher.3361097152515408945350232662951854623293328111337560804794397579445817389060
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.115566185768346729010906778139113895626947189623727984245524290684493469192050
Short name T509
Test name
Test status
Simulation time 1729953098 ps
CPU time 6.72 seconds
Started Nov 22 12:41:08 PM PST 23
Finished Nov 22 12:41:16 PM PST 23
Peak memory 200100 kb
Host smart-5bd5435f-23c5-4e36-b485-d3a85d423473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115566185768346729010906778139113895626947189623727984245524290684493469192050 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 35.rstmgr_reset.115566185768346729010906778139113895626947189623727984245524290684493469192050
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.65342324516439943302301302248503206071495540543446192084004547264726762169957
Short name T378
Test name
Test status
Simulation time 170065619 ps
CPU time 1.13 seconds
Started Nov 22 12:41:03 PM PST 23
Finished Nov 22 12:41:05 PM PST 23
Peak memory 199880 kb
Host smart-f2931e73-b92c-4eae-952f-8e09a97482c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65342324516439943302301302248503206071495540543446192084004547264726762169957 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.65342324516439943302301302248503206071495540543446192084004547264726762169957
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.95084151318636981971081145716810603632372575900841526551692991288313556735105
Short name T457
Test name
Test status
Simulation time 223941050 ps
CPU time 1.4 seconds
Started Nov 22 12:41:07 PM PST 23
Finished Nov 22 12:41:10 PM PST 23
Peak memory 199984 kb
Host smart-23503e47-e984-41c7-8fe7-020af014a99f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95084151318636981971081145716810603632372575900841526551692991288313556735105 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 35.rstmgr_smoke.95084151318636981971081145716810603632372575900841526551692991288313556735105
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.11317591922848061413945713099032374883608408869197612808930797404344882928541
Short name T336
Test name
Test status
Simulation time 11131278308 ps
CPU time 38.86 seconds
Started Nov 22 12:41:29 PM PST 23
Finished Nov 22 12:42:09 PM PST 23
Peak memory 200108 kb
Host smart-01d1902a-ea2b-48e4-b5aa-27f51dcd80e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11317591922848061413945713099032374883608408869197612808930797404344882928541 -assert nopos
tproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.11317591922848061413945713099032374883608408869197612808930797404344882928541
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.28941507879907339220758908989987945608878000290946994591874577808250681714612
Short name T407
Test name
Test status
Simulation time 473109710 ps
CPU time 2.63 seconds
Started Nov 22 12:41:30 PM PST 23
Finished Nov 22 12:41:33 PM PST 23
Peak memory 199840 kb
Host smart-f0636da6-6c76-4622-99dc-b8e2ee648596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28941507879907339220758908989987945608878000290946994591874577808250681714612 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 35.rstmgr_sw_rst.28941507879907339220758908989987945608878000290946994591874577808250681714612
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.93382154098723689466156871629682068682248922374410779386527464120686247220629
Short name T278
Test name
Test status
Simulation time 241232855 ps
CPU time 1.41 seconds
Started Nov 22 12:41:16 PM PST 23
Finished Nov 22 12:41:19 PM PST 23
Peak memory 199788 kb
Host smart-527ba4c6-25d3-4d21-8272-1f3b9ff9cce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93382154098723689466156871629682068682248922374410779386527464120686247220629 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.rstmgr_sw_rst_reset_race.93382154098723689466156871629682068682248922374410779386527464120686247220629
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.36936428131805497440557101915946551100685812224333740623207135092021681760980
Short name T443
Test name
Test status
Simulation time 78981557 ps
CPU time 0.78 seconds
Started Nov 22 12:41:08 PM PST 23
Finished Nov 22 12:41:10 PM PST 23
Peak memory 199720 kb
Host smart-67996316-88c6-4478-b1ff-7d8976664a66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36936428131805497440557101915946551100685812224333740623207135092021681760980 -assert nopostpr
oc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.36936428131805497440557101915946551100685812224333740623207135092021681760980
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.70828251007116833000343775422982111167623723702536762604837264920303148330860
Short name T424
Test name
Test status
Simulation time 2162831562 ps
CPU time 7.9 seconds
Started Nov 22 12:41:23 PM PST 23
Finished Nov 22 12:41:32 PM PST 23
Peak memory 217008 kb
Host smart-fe9a4cfa-c985-4839-a4ba-b3789e138faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70828251007116833000343775422982111167623723702536762604837264920303148330860 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 36.rstmgr_leaf_rst_cnsty.70828251007116833000343775422982111167623723702536762604837264920303148330860
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.101721145846158124119710742145296718403431327677004242156055009351010349470243
Short name T362
Test name
Test status
Simulation time 243816210 ps
CPU time 1.12 seconds
Started Nov 22 12:41:31 PM PST 23
Finished Nov 22 12:41:33 PM PST 23
Peak memory 216760 kb
Host smart-adf677f3-b6fb-47a2-b5d4-532cc96377e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101721145846158124119710742145296718403431327677004242156055009351010349470243 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.101721145846158124119710742145296718403431327677004242156055009351010349470243
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.94601060541294177301417322108380162737866064383763620329435074634414597675348
Short name T401
Test name
Test status
Simulation time 230357768 ps
CPU time 0.93 seconds
Started Nov 22 12:41:14 PM PST 23
Finished Nov 22 12:41:15 PM PST 23
Peak memory 199540 kb
Host smart-94120b7f-5547-42e8-819e-f5c83a53fdcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94601060541294177301417322108380162737866064383763620329435074634414597675348 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.rstmgr_por_stretcher.94601060541294177301417322108380162737866064383763620329435074634414597675348
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.56394705599832352569774884101559618513490886609354032192953390130644219565907
Short name T281
Test name
Test status
Simulation time 1729953098 ps
CPU time 6.51 seconds
Started Nov 22 12:41:20 PM PST 23
Finished Nov 22 12:41:27 PM PST 23
Peak memory 199988 kb
Host smart-5cdaecf2-d6f7-4c59-bc9d-34aa93c63183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56394705599832352569774884101559618513490886609354032192953390130644219565907 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 36.rstmgr_reset.56394705599832352569774884101559618513490886609354032192953390130644219565907
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.9244176141612856188960220277211538763866134392587133033393528595914714139969
Short name T391
Test name
Test status
Simulation time 170065619 ps
CPU time 1.16 seconds
Started Nov 22 12:41:18 PM PST 23
Finished Nov 22 12:41:21 PM PST 23
Peak memory 199828 kb
Host smart-de16c3ad-d25e-46bf-9e88-8cce30be52b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9244176141612856188960220277211538763866134392587133033393528595914714139969 -assert nopostproc +UVM_TESTNAME=rstmgr_bas
e_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.9244176141612856188960220277211538763866134392587133033393528595914714139969
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.1553645274453291474904393307234468430989223313251962695486235535095549210803
Short name T400
Test name
Test status
Simulation time 223941050 ps
CPU time 1.39 seconds
Started Nov 22 12:41:26 PM PST 23
Finished Nov 22 12:41:28 PM PST 23
Peak memory 199892 kb
Host smart-3fddd02a-ea4b-415d-a25f-2decddd23a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553645274453291474904393307234468430989223313251962695486235535095549210803 -assert nopostproc +UVM_TESTNAME=rstmgr_bas
e_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rstmgr_smoke.1553645274453291474904393307234468430989223313251962695486235535095549210803
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.94624448069553870950171557632380585977920201565246226850603939360537833622977
Short name T435
Test name
Test status
Simulation time 11131278308 ps
CPU time 38.57 seconds
Started Nov 22 12:41:28 PM PST 23
Finished Nov 22 12:42:07 PM PST 23
Peak memory 200100 kb
Host smart-4b1844da-14c7-4f7f-894d-003035c0c68f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94624448069553870950171557632380585977920201565246226850603939360537833622977 -assert nopos
tproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.94624448069553870950171557632380585977920201565246226850603939360537833622977
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.28157825309610098182976485758510246435795998313439433011181140688312428927628
Short name T363
Test name
Test status
Simulation time 473109710 ps
CPU time 2.69 seconds
Started Nov 22 12:41:42 PM PST 23
Finished Nov 22 12:41:45 PM PST 23
Peak memory 199800 kb
Host smart-f10ecdef-c6ce-45cf-99dc-c9edcfdca594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28157825309610098182976485758510246435795998313439433011181140688312428927628 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 36.rstmgr_sw_rst.28157825309610098182976485758510246435795998313439433011181140688312428927628
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.111879206146889500847670710832675788597737440577426211285367290533512811953482
Short name T395
Test name
Test status
Simulation time 241232855 ps
CPU time 1.46 seconds
Started Nov 22 12:41:18 PM PST 23
Finished Nov 22 12:41:21 PM PST 23
Peak memory 199828 kb
Host smart-e6bf9132-925c-4dae-99d0-87235ff36b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111879206146889500847670710832675788597737440577426211285367290533512811953482 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 36.rstmgr_sw_rst_reset_race.111879206146889500847670710832675788597737440577426211285367290533512811953482
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.54924350658881767222182506254857964692350523253648477547385277923915852549134
Short name T381
Test name
Test status
Simulation time 78981557 ps
CPU time 0.77 seconds
Started Nov 22 12:41:21 PM PST 23
Finished Nov 22 12:41:23 PM PST 23
Peak memory 199684 kb
Host smart-f96c09d2-ae45-47dc-9a7f-1fac2405e2cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54924350658881767222182506254857964692350523253648477547385277923915852549134 -assert nopostpr
oc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.54924350658881767222182506254857964692350523253648477547385277923915852549134
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.15423349039415038296514070584991464506091531588175069795400153012639385018383
Short name T305
Test name
Test status
Simulation time 2162831562 ps
CPU time 7.9 seconds
Started Nov 22 12:41:21 PM PST 23
Finished Nov 22 12:41:30 PM PST 23
Peak memory 217064 kb
Host smart-2111abe9-2e7e-4dd4-8519-292ad22c93f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15423349039415038296514070584991464506091531588175069795400153012639385018383 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 37.rstmgr_leaf_rst_cnsty.15423349039415038296514070584991464506091531588175069795400153012639385018383
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.9670307702790156569351373347533721988787821230606250576291440526083303370147
Short name T619
Test name
Test status
Simulation time 243816210 ps
CPU time 1.08 seconds
Started Nov 22 12:41:14 PM PST 23
Finished Nov 22 12:41:16 PM PST 23
Peak memory 216852 kb
Host smart-81138f7e-12bc-4a6f-b332-7d54a51eb9c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9670307702790156569351373347533721988787821230606250576291440526083303370147 -assert nopostproc +UVM_TESTNAME=rstmgr_bas
e_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.9670307702790156569351373347533721988787821230606250576291440526083303370147
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.40029184224213015368155994943648709083336455334879489542143824396401537226349
Short name T343
Test name
Test status
Simulation time 230357768 ps
CPU time 0.93 seconds
Started Nov 22 12:41:07 PM PST 23
Finished Nov 22 12:41:09 PM PST 23
Peak memory 199648 kb
Host smart-35230741-fbfb-483f-b453-8a38c9e972eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40029184224213015368155994943648709083336455334879489542143824396401537226349 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.rstmgr_por_stretcher.40029184224213015368155994943648709083336455334879489542143824396401537226349
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.81585225383500026016338134762936641876093394972143467876054128897211864984747
Short name T507
Test name
Test status
Simulation time 1729953098 ps
CPU time 6.28 seconds
Started Nov 22 12:41:03 PM PST 23
Finished Nov 22 12:41:12 PM PST 23
Peak memory 200004 kb
Host smart-d644b8d9-0519-46b2-94ef-2f89893ab048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81585225383500026016338134762936641876093394972143467876054128897211864984747 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 37.rstmgr_reset.81585225383500026016338134762936641876093394972143467876054128897211864984747
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.13420406276773012305225984325576889660752380182905888883480722725448289200980
Short name T370
Test name
Test status
Simulation time 170065619 ps
CPU time 1.18 seconds
Started Nov 22 12:41:02 PM PST 23
Finished Nov 22 12:41:04 PM PST 23
Peak memory 199760 kb
Host smart-cd8818d4-4242-4559-8372-ac6bc1dc0e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13420406276773012305225984325576889660752380182905888883480722725448289200980 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.13420406276773012305225984325576889660752380182905888883480722725448289200980
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.11436188033135043862256466187432990136491951981809284448130054359710292722760
Short name T569
Test name
Test status
Simulation time 223941050 ps
CPU time 1.48 seconds
Started Nov 22 12:41:22 PM PST 23
Finished Nov 22 12:41:24 PM PST 23
Peak memory 200024 kb
Host smart-71d282b9-fa8d-4d11-be81-5a6a5909dc09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11436188033135043862256466187432990136491951981809284448130054359710292722760 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 37.rstmgr_smoke.11436188033135043862256466187432990136491951981809284448130054359710292722760
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.73707333198441462931948634765390850918120962945166104828232953087995454053659
Short name T351
Test name
Test status
Simulation time 11131278308 ps
CPU time 39.15 seconds
Started Nov 22 12:41:04 PM PST 23
Finished Nov 22 12:41:45 PM PST 23
Peak memory 199956 kb
Host smart-9150e797-8903-4d91-85ea-2209de95bb0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73707333198441462931948634765390850918120962945166104828232953087995454053659 -assert nopos
tproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.73707333198441462931948634765390850918120962945166104828232953087995454053659
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.9932865559999307124270647848655981093642746378048362501356689487968111875666
Short name T9
Test name
Test status
Simulation time 473109710 ps
CPU time 2.68 seconds
Started Nov 22 12:40:59 PM PST 23
Finished Nov 22 12:41:02 PM PST 23
Peak memory 199852 kb
Host smart-5bb591d3-2b5b-44df-bb7f-9b210ee3a654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9932865559999307124270647848655981093642746378048362501356689487968111875666 -assert nopostproc +UVM_TESTNAME=rstmgr_bas
e_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 37.rstmgr_sw_rst.9932865559999307124270647848655981093642746378048362501356689487968111875666
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.94947362824171027526960580441766321447752179966855286873636699469505725887348
Short name T584
Test name
Test status
Simulation time 241232855 ps
CPU time 1.34 seconds
Started Nov 22 12:41:09 PM PST 23
Finished Nov 22 12:41:12 PM PST 23
Peak memory 199672 kb
Host smart-34a8ae63-93a0-44c1-b8d1-c57003be9220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94947362824171027526960580441766321447752179966855286873636699469505725887348 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 37.rstmgr_sw_rst_reset_race.94947362824171027526960580441766321447752179966855286873636699469505725887348
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.69527409249753108003544895188600622038744529994259040543466954825516419545498
Short name T230
Test name
Test status
Simulation time 78981557 ps
CPU time 0.77 seconds
Started Nov 22 12:41:05 PM PST 23
Finished Nov 22 12:41:08 PM PST 23
Peak memory 199652 kb
Host smart-c7339c1c-f881-4087-b120-94a1c27e89c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69527409249753108003544895188600622038744529994259040543466954825516419545498 -assert nopostpr
oc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.69527409249753108003544895188600622038744529994259040543466954825516419545498
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.79488868690954589635712740050801421873997795681676482660795909986186490414132
Short name T384
Test name
Test status
Simulation time 2162831562 ps
CPU time 8.27 seconds
Started Nov 22 12:41:02 PM PST 23
Finished Nov 22 12:41:12 PM PST 23
Peak memory 216984 kb
Host smart-f9e2821f-a153-4162-9f39-975e6e83f1ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79488868690954589635712740050801421873997795681676482660795909986186490414132 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 38.rstmgr_leaf_rst_cnsty.79488868690954589635712740050801421873997795681676482660795909986186490414132
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.22940734010666460435583025575144383042049263526617116464471135890761938971630
Short name T243
Test name
Test status
Simulation time 243816210 ps
CPU time 1.08 seconds
Started Nov 22 12:41:01 PM PST 23
Finished Nov 22 12:41:02 PM PST 23
Peak memory 216848 kb
Host smart-c6123a46-69aa-4b78-a0a7-6dbdbd9c5a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22940734010666460435583025575144383042049263526617116464471135890761938971630 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.22940734010666460435583025575144383042049263526617116464471135890761938971630
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.14135507217513540021377379861667563032313945260800312723173243864793098260984
Short name T386
Test name
Test status
Simulation time 230357768 ps
CPU time 0.91 seconds
Started Nov 22 12:41:03 PM PST 23
Finished Nov 22 12:41:06 PM PST 23
Peak memory 199660 kb
Host smart-5ba82405-b0a0-4126-8457-eb95706a7ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14135507217513540021377379861667563032313945260800312723173243864793098260984 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.rstmgr_por_stretcher.14135507217513540021377379861667563032313945260800312723173243864793098260984
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.10883871558681597848363084032509981548750747393047938027040097930094922556579
Short name T379
Test name
Test status
Simulation time 1729953098 ps
CPU time 6.68 seconds
Started Nov 22 12:41:30 PM PST 23
Finished Nov 22 12:41:37 PM PST 23
Peak memory 200084 kb
Host smart-86d7763a-0afb-449a-825b-fbb49fa3b124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10883871558681597848363084032509981548750747393047938027040097930094922556579 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 38.rstmgr_reset.10883871558681597848363084032509981548750747393047938027040097930094922556579
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.33510124462642001002865447727916511786820725463453797966901286276435337200232
Short name T350
Test name
Test status
Simulation time 170065619 ps
CPU time 1.11 seconds
Started Nov 22 12:41:29 PM PST 23
Finished Nov 22 12:41:31 PM PST 23
Peak memory 199884 kb
Host smart-4ef0930e-8aad-43bd-b90e-5c0143275c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33510124462642001002865447727916511786820725463453797966901286276435337200232 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.33510124462642001002865447727916511786820725463453797966901286276435337200232
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.38983233257463034730108221926414546814987800651201273619925046364707948520166
Short name T577
Test name
Test status
Simulation time 223941050 ps
CPU time 1.41 seconds
Started Nov 22 12:41:14 PM PST 23
Finished Nov 22 12:41:17 PM PST 23
Peak memory 199920 kb
Host smart-e18750c5-97ca-462f-969a-ccf49f4fb488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38983233257463034730108221926414546814987800651201273619925046364707948520166 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 38.rstmgr_smoke.38983233257463034730108221926414546814987800651201273619925046364707948520166
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.56169133720312332675490729976356695940559134643621614768265983534675360010065
Short name T117
Test name
Test status
Simulation time 11131278308 ps
CPU time 39.32 seconds
Started Nov 22 12:41:08 PM PST 23
Finished Nov 22 12:41:49 PM PST 23
Peak memory 200104 kb
Host smart-d279c4fd-3b9d-4dcd-a80c-4a274283d273
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56169133720312332675490729976356695940559134643621614768265983534675360010065 -assert nopos
tproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.56169133720312332675490729976356695940559134643621614768265983534675360010065
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.113429312203445459453718162905299614053136293539244803550492599116383279325632
Short name T545
Test name
Test status
Simulation time 473109710 ps
CPU time 2.83 seconds
Started Nov 22 12:41:06 PM PST 23
Finished Nov 22 12:41:10 PM PST 23
Peak memory 199824 kb
Host smart-65f7c352-465c-47b4-909f-acc80a5f9ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113429312203445459453718162905299614053136293539244803550492599116383279325632 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 38.rstmgr_sw_rst.113429312203445459453718162905299614053136293539244803550492599116383279325632
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.102570506469138010358171565948592580566691423987292299177695150600002339637378
Short name T260
Test name
Test status
Simulation time 241232855 ps
CPU time 1.34 seconds
Started Nov 22 12:41:09 PM PST 23
Finished Nov 22 12:41:12 PM PST 23
Peak memory 199876 kb
Host smart-dcb151fa-1215-49b3-8bd5-943314acc43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102570506469138010358171565948592580566691423987292299177695150600002339637378 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 38.rstmgr_sw_rst_reset_race.102570506469138010358171565948592580566691423987292299177695150600002339637378
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.109175885501219152385715729365263643593702997112555665389287847002531854408724
Short name T61
Test name
Test status
Simulation time 78981557 ps
CPU time 0.75 seconds
Started Nov 22 12:41:05 PM PST 23
Finished Nov 22 12:41:08 PM PST 23
Peak memory 199624 kb
Host smart-759c1393-4199-4c2e-bdf4-8332ca284dcd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109175885501219152385715729365263643593702997112555665389287847002531854408724 -assert nopostp
roc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.109175885501219152385715729365263643593702997112555665389287847002531854408724
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.107927529524558082021991582799662180551140563878813168434645897757617767780205
Short name T306
Test name
Test status
Simulation time 2162831562 ps
CPU time 7.84 seconds
Started Nov 22 12:41:18 PM PST 23
Finished Nov 22 12:41:27 PM PST 23
Peak memory 217128 kb
Host smart-55ddcb18-3c04-4c89-9f78-ad77f90df227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107927529524558082021991582799662180551140563878813168434645897757617767780205 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 39.rstmgr_leaf_rst_cnsty.107927529524558082021991582799662180551140563878813168434645897757617767780205
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.8504150212804982466016220245659425460706100288117421815532339175027914457704
Short name T484
Test name
Test status
Simulation time 243816210 ps
CPU time 1.08 seconds
Started Nov 22 12:41:13 PM PST 23
Finished Nov 22 12:41:20 PM PST 23
Peak memory 216864 kb
Host smart-110af078-ad0a-4315-8f6f-035c72ee833c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8504150212804982466016220245659425460706100288117421815532339175027914457704 -assert nopostproc +UVM_TESTNAME=rstmgr_bas
e_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.8504150212804982466016220245659425460706100288117421815532339175027914457704
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.66600256681446430547357501289212416752300049001963995235541631996301338793144
Short name T393
Test name
Test status
Simulation time 230357768 ps
CPU time 0.97 seconds
Started Nov 22 12:41:04 PM PST 23
Finished Nov 22 12:41:07 PM PST 23
Peak memory 199652 kb
Host smart-14004797-8c0a-49dc-a065-e540e6934bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66600256681446430547357501289212416752300049001963995235541631996301338793144 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.rstmgr_por_stretcher.66600256681446430547357501289212416752300049001963995235541631996301338793144
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.59988994515870460013466647222015087788684349148902070725632488840880332734190
Short name T322
Test name
Test status
Simulation time 1729953098 ps
CPU time 6.59 seconds
Started Nov 22 12:41:14 PM PST 23
Finished Nov 22 12:41:22 PM PST 23
Peak memory 200096 kb
Host smart-39f488f2-d327-4392-b664-d1b6f7fb3ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59988994515870460013466647222015087788684349148902070725632488840880332734190 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 39.rstmgr_reset.59988994515870460013466647222015087788684349148902070725632488840880332734190
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.14719496944908490587624838549434169247221815667809354586611395244951628024975
Short name T257
Test name
Test status
Simulation time 170065619 ps
CPU time 1.21 seconds
Started Nov 22 12:41:07 PM PST 23
Finished Nov 22 12:41:10 PM PST 23
Peak memory 199780 kb
Host smart-0a0af10d-09b0-4451-ac53-87809eedce12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14719496944908490587624838549434169247221815667809354586611395244951628024975 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.14719496944908490587624838549434169247221815667809354586611395244951628024975
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.3232597133375164589275888338973162795093384746087120985957248932920205053256
Short name T617
Test name
Test status
Simulation time 223941050 ps
CPU time 1.59 seconds
Started Nov 22 12:41:10 PM PST 23
Finished Nov 22 12:41:13 PM PST 23
Peak memory 199936 kb
Host smart-192d2658-5b7e-4300-ab54-2a1b77573080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232597133375164589275888338973162795093384746087120985957248932920205053256 -assert nopostproc +UVM_TESTNAME=rstmgr_bas
e_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rstmgr_smoke.3232597133375164589275888338973162795093384746087120985957248932920205053256
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.21490792974157623502046891165481611859742959650261434885509902756516631045586
Short name T609
Test name
Test status
Simulation time 11131278308 ps
CPU time 38.81 seconds
Started Nov 22 12:41:04 PM PST 23
Finished Nov 22 12:41:45 PM PST 23
Peak memory 200024 kb
Host smart-90520971-c9d6-4703-8c3f-d6ddede40898
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21490792974157623502046891165481611859742959650261434885509902756516631045586 -assert nopos
tproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.21490792974157623502046891165481611859742959650261434885509902756516631045586
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.71641813644030299882976860412659353662543931710021979171391796530241637714679
Short name T250
Test name
Test status
Simulation time 473109710 ps
CPU time 2.62 seconds
Started Nov 22 12:41:10 PM PST 23
Finished Nov 22 12:41:14 PM PST 23
Peak memory 199800 kb
Host smart-8408d234-b1db-41ac-98ee-9e13a24a5035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71641813644030299882976860412659353662543931710021979171391796530241637714679 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 39.rstmgr_sw_rst.71641813644030299882976860412659353662543931710021979171391796530241637714679
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.48340556877216476574726185969374806453292035956306676170600867168315741186827
Short name T248
Test name
Test status
Simulation time 241232855 ps
CPU time 1.37 seconds
Started Nov 22 12:41:05 PM PST 23
Finished Nov 22 12:41:08 PM PST 23
Peak memory 199824 kb
Host smart-85b7f59f-d804-4503-97c0-4e1fc716b793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48340556877216476574726185969374806453292035956306676170600867168315741186827 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.rstmgr_sw_rst_reset_race.48340556877216476574726185969374806453292035956306676170600867168315741186827
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.98522112875405673412629983945752399651029843009824710272431849168505590937591
Short name T559
Test name
Test status
Simulation time 78981557 ps
CPU time 0.79 seconds
Started Nov 22 12:39:36 PM PST 23
Finished Nov 22 12:39:41 PM PST 23
Peak memory 199580 kb
Host smart-4e45ecf0-76f6-4a95-a63d-2fdcb7fe0d89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98522112875405673412629983945752399651029843009824710272431849168505590937591 -assert nopostpr
oc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.98522112875405673412629983945752399651029843009824710272431849168505590937591
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.14412736128024109835013416169625861567485725502399304990985114385408765248547
Short name T447
Test name
Test status
Simulation time 2162831562 ps
CPU time 8.15 seconds
Started Nov 22 12:39:37 PM PST 23
Finished Nov 22 12:39:50 PM PST 23
Peak memory 216860 kb
Host smart-41ccef2b-7a63-4243-b247-46e7a7a82f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14412736128024109835013416169625861567485725502399304990985114385408765248547 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 4.rstmgr_leaf_rst_cnsty.14412736128024109835013416169625861567485725502399304990985114385408765248547
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.110521595915991887205512639580440327928381281840181707364121774936412475303520
Short name T244
Test name
Test status
Simulation time 243816210 ps
CPU time 1.14 seconds
Started Nov 22 12:39:36 PM PST 23
Finished Nov 22 12:39:42 PM PST 23
Peak memory 216764 kb
Host smart-588e8d4f-d571-4f4a-b5ba-ea64f9cc237a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110521595915991887205512639580440327928381281840181707364121774936412475303520 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.110521595915991887205512639580440327928381281840181707364121774936412475303520
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.73498733703034248034849305216927009276606760590403792461907096388858880149681
Short name T533
Test name
Test status
Simulation time 230357768 ps
CPU time 0.96 seconds
Started Nov 22 12:39:44 PM PST 23
Finished Nov 22 12:39:47 PM PST 23
Peak memory 199572 kb
Host smart-8a75601b-276e-4151-93ac-6e91d9fc0a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73498733703034248034849305216927009276606760590403792461907096388858880149681 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.rstmgr_por_stretcher.73498733703034248034849305216927009276606760590403792461907096388858880149681
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.30665788156133653169920103679217618231757495220113602627709913860353720988429
Short name T605
Test name
Test status
Simulation time 1729953098 ps
CPU time 6.4 seconds
Started Nov 22 12:39:36 PM PST 23
Finished Nov 22 12:39:46 PM PST 23
Peak memory 200100 kb
Host smart-40aa0fd4-1bdf-4361-a1a6-1775edd2f48f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30665788156133653169920103679217618231757495220113602627709913860353720988429 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 4.rstmgr_reset.30665788156133653169920103679217618231757495220113602627709913860353720988429
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.12411825094990374471947075767300317026272652464836775013268530913064842887503
Short name T63
Test name
Test status
Simulation time 8294713949 ps
CPU time 14.17 seconds
Started Nov 22 12:39:40 PM PST 23
Finished Nov 22 12:39:58 PM PST 23
Peak memory 216536 kb
Host smart-911d733f-349a-4495-bf9b-0125cf856250
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12411825094990374471947075767300317026272652464836775013268530913064842887503 -assert nopostpro
c +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.12411825094990374471947075767300317026272652464836775013268530913064842887503
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.34416806835760254702186507864613192835210149650045679926519139510460962375735
Short name T256
Test name
Test status
Simulation time 170065619 ps
CPU time 1.17 seconds
Started Nov 22 12:39:49 PM PST 23
Finished Nov 22 12:39:51 PM PST 23
Peak memory 199780 kb
Host smart-74272d9c-a642-48ca-9912-6fa1a1881a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34416806835760254702186507864613192835210149650045679926519139510460962375735 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.34416806835760254702186507864613192835210149650045679926519139510460962375735
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.39446063492271589839073590256565614394836406950766364864611531587148906773137
Short name T575
Test name
Test status
Simulation time 223941050 ps
CPU time 1.42 seconds
Started Nov 22 12:39:36 PM PST 23
Finished Nov 22 12:39:41 PM PST 23
Peak memory 199936 kb
Host smart-4008ac56-f46c-4d38-bd2a-2fc91c18260c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39446063492271589839073590256565614394836406950766364864611531587148906773137 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 4.rstmgr_smoke.39446063492271589839073590256565614394836406950766364864611531587148906773137
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.11712276758359986955056888130507380535632733888857225980857581036244796725783
Short name T229
Test name
Test status
Simulation time 11131278308 ps
CPU time 38.61 seconds
Started Nov 22 12:39:37 PM PST 23
Finished Nov 22 12:40:20 PM PST 23
Peak memory 199836 kb
Host smart-cf9b6188-2a09-48dd-adfc-5bc07d8bae31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11712276758359986955056888130507380535632733888857225980857581036244796725783 -assert nopos
tproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.11712276758359986955056888130507380535632733888857225980857581036244796725783
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.82348162674081874634692443256362963915405456126439286016646977256110873030722
Short name T604
Test name
Test status
Simulation time 473109710 ps
CPU time 2.81 seconds
Started Nov 22 12:39:37 PM PST 23
Finished Nov 22 12:39:44 PM PST 23
Peak memory 199664 kb
Host smart-cb51f02d-4295-4e16-985b-672650d73899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82348162674081874634692443256362963915405456126439286016646977256110873030722 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 4.rstmgr_sw_rst.82348162674081874634692443256362963915405456126439286016646977256110873030722
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.22022653604328012692512081654521484528439629783759908401704776680780161234100
Short name T508
Test name
Test status
Simulation time 241232855 ps
CPU time 1.43 seconds
Started Nov 22 12:39:36 PM PST 23
Finished Nov 22 12:39:41 PM PST 23
Peak memory 199780 kb
Host smart-a8b65886-0c2b-4067-bc36-c871f2122a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22022653604328012692512081654521484528439629783759908401704776680780161234100 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.rstmgr_sw_rst_reset_race.22022653604328012692512081654521484528439629783759908401704776680780161234100
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.72066284732147393681790107831298892535785589348446610580127815999890377235996
Short name T124
Test name
Test status
Simulation time 78981557 ps
CPU time 0.81 seconds
Started Nov 22 12:41:05 PM PST 23
Finished Nov 22 12:41:08 PM PST 23
Peak memory 199696 kb
Host smart-7d2c92cd-31d3-4766-b112-c7f2f4bd9056
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72066284732147393681790107831298892535785589348446610580127815999890377235996 -assert nopostpr
oc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.72066284732147393681790107831298892535785589348446610580127815999890377235996
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.3112735287739823257535381368169958185432690933950503013634056924289073306998
Short name T349
Test name
Test status
Simulation time 2162831562 ps
CPU time 8.26 seconds
Started Nov 22 12:41:05 PM PST 23
Finished Nov 22 12:41:15 PM PST 23
Peak memory 217120 kb
Host smart-b2a1f8e3-f190-4b9b-8072-30f2f169e7c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112735287739823257535381368169958185432690933950503013634056924289073306998 -assert nopostproc +UVM_TESTNAME=rstmgr_bas
e_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.rstmgr_leaf_rst_cnsty.3112735287739823257535381368169958185432690933950503013634056924289073306998
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.88653772839091985206277395933828777669218928736270882375040556618900678146877
Short name T344
Test name
Test status
Simulation time 243816210 ps
CPU time 1.09 seconds
Started Nov 22 12:41:13 PM PST 23
Finished Nov 22 12:41:15 PM PST 23
Peak memory 216728 kb
Host smart-25913e55-83cd-4a06-a7b3-1bf06e75192f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88653772839091985206277395933828777669218928736270882375040556618900678146877 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.88653772839091985206277395933828777669218928736270882375040556618900678146877
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.21871394027259947809370540990525136859436971320838413390207983814819811297556
Short name T596
Test name
Test status
Simulation time 230357768 ps
CPU time 0.91 seconds
Started Nov 22 12:41:07 PM PST 23
Finished Nov 22 12:41:09 PM PST 23
Peak memory 199680 kb
Host smart-6c7d323b-a3e2-40ba-9ab3-f44e25ac48c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21871394027259947809370540990525136859436971320838413390207983814819811297556 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.rstmgr_por_stretcher.21871394027259947809370540990525136859436971320838413390207983814819811297556
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.4742213477017171973630053825283274872687616123263021142911495322615059297990
Short name T406
Test name
Test status
Simulation time 1729953098 ps
CPU time 6.61 seconds
Started Nov 22 12:41:08 PM PST 23
Finished Nov 22 12:41:17 PM PST 23
Peak memory 199932 kb
Host smart-d3e1a35e-cec8-48fc-8c6e-8d423ea37afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4742213477017171973630053825283274872687616123263021142911495322615059297990 -assert nopostproc +UVM_TESTNAME=rstmgr_bas
e_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rstmgr_reset.4742213477017171973630053825283274872687616123263021142911495322615059297990
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.82829784925118590959870866777032598732249580430680738722064095790661745613524
Short name T98
Test name
Test status
Simulation time 170065619 ps
CPU time 1.15 seconds
Started Nov 22 12:41:02 PM PST 23
Finished Nov 22 12:41:05 PM PST 23
Peak memory 199868 kb
Host smart-6965c938-0765-4a58-8399-a18122d339b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82829784925118590959870866777032598732249580430680738722064095790661745613524 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.82829784925118590959870866777032598732249580430680738722064095790661745613524
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.36487902259846031724902248821349224719205478344456824695165757864909519368421
Short name T439
Test name
Test status
Simulation time 223941050 ps
CPU time 1.35 seconds
Started Nov 22 12:41:03 PM PST 23
Finished Nov 22 12:41:05 PM PST 23
Peak memory 200024 kb
Host smart-ce80a1c9-6237-4f95-8d7f-5c69f5bf3c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36487902259846031724902248821349224719205478344456824695165757864909519368421 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 40.rstmgr_smoke.36487902259846031724902248821349224719205478344456824695165757864909519368421
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.62631674218957747449803196014310567958662801858094742482452883368031953055013
Short name T321
Test name
Test status
Simulation time 11131278308 ps
CPU time 40.39 seconds
Started Nov 22 12:41:06 PM PST 23
Finished Nov 22 12:41:49 PM PST 23
Peak memory 200056 kb
Host smart-778b954c-c73b-494c-a0ac-02ebc919fe27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62631674218957747449803196014310567958662801858094742482452883368031953055013 -assert nopos
tproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.62631674218957747449803196014310567958662801858094742482452883368031953055013
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.37361662276770640399914635415558648323150197151842274939646994827263288231912
Short name T130
Test name
Test status
Simulation time 473109710 ps
CPU time 2.67 seconds
Started Nov 22 12:41:23 PM PST 23
Finished Nov 22 12:41:27 PM PST 23
Peak memory 199832 kb
Host smart-0c6433fe-84ee-49fb-a25c-aaae41207f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37361662276770640399914635415558648323150197151842274939646994827263288231912 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 40.rstmgr_sw_rst.37361662276770640399914635415558648323150197151842274939646994827263288231912
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.70791257037134277209112385733716578783336065001665272725719696034306321092409
Short name T551
Test name
Test status
Simulation time 241232855 ps
CPU time 1.41 seconds
Started Nov 22 12:41:03 PM PST 23
Finished Nov 22 12:41:05 PM PST 23
Peak memory 199824 kb
Host smart-7a12c3bd-248f-497a-acb2-27c15aa74c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70791257037134277209112385733716578783336065001665272725719696034306321092409 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 40.rstmgr_sw_rst_reset_race.70791257037134277209112385733716578783336065001665272725719696034306321092409
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.32501232190897758369512493972804393897053812132521137823592219784015052651366
Short name T67
Test name
Test status
Simulation time 78981557 ps
CPU time 0.75 seconds
Started Nov 22 12:41:09 PM PST 23
Finished Nov 22 12:41:11 PM PST 23
Peak memory 199656 kb
Host smart-ae6b9d81-ac42-4014-b06b-4edf6f0f956d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32501232190897758369512493972804393897053812132521137823592219784015052651366 -assert nopostpr
oc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.32501232190897758369512493972804393897053812132521137823592219784015052651366
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.28636417076213867442644696351185586256225972215767582387562276581495362989495
Short name T578
Test name
Test status
Simulation time 2162831562 ps
CPU time 8.4 seconds
Started Nov 22 12:41:13 PM PST 23
Finished Nov 22 12:41:22 PM PST 23
Peak memory 217064 kb
Host smart-5f8b5514-9adb-4414-aced-c1f803410900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28636417076213867442644696351185586256225972215767582387562276581495362989495 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 41.rstmgr_leaf_rst_cnsty.28636417076213867442644696351185586256225972215767582387562276581495362989495
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.81078513225574625501182172576342911324743375052603715615652468570463846564414
Short name T42
Test name
Test status
Simulation time 243816210 ps
CPU time 1.1 seconds
Started Nov 22 12:41:29 PM PST 23
Finished Nov 22 12:41:31 PM PST 23
Peak memory 216732 kb
Host smart-bb3a26de-c8b0-49d6-9286-97255d9ecfb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81078513225574625501182172576342911324743375052603715615652468570463846564414 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.81078513225574625501182172576342911324743375052603715615652468570463846564414
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.60940740116139759373627417494929911952257360379654077518167109058007235532520
Short name T562
Test name
Test status
Simulation time 230357768 ps
CPU time 0.91 seconds
Started Nov 22 12:41:20 PM PST 23
Finished Nov 22 12:41:21 PM PST 23
Peak memory 199700 kb
Host smart-2df451ca-dcde-4a1f-bf5d-e446b64a17ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60940740116139759373627417494929911952257360379654077518167109058007235532520 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.rstmgr_por_stretcher.60940740116139759373627417494929911952257360379654077518167109058007235532520
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.99106848420661496686285646867260364211706385609398502388153883861275024003262
Short name T529
Test name
Test status
Simulation time 1729953098 ps
CPU time 6.73 seconds
Started Nov 22 12:41:28 PM PST 23
Finished Nov 22 12:41:36 PM PST 23
Peak memory 200104 kb
Host smart-a9118e30-2250-4d38-8e9a-3be581d1b1bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99106848420661496686285646867260364211706385609398502388153883861275024003262 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 41.rstmgr_reset.99106848420661496686285646867260364211706385609398502388153883861275024003262
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.57620764409680652043064962416364852627910363792028140135284844491839733091542
Short name T517
Test name
Test status
Simulation time 170065619 ps
CPU time 1.11 seconds
Started Nov 22 12:41:09 PM PST 23
Finished Nov 22 12:41:12 PM PST 23
Peak memory 199824 kb
Host smart-9a0b737c-ff0f-4824-9251-e248363faa4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57620764409680652043064962416364852627910363792028140135284844491839733091542 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.57620764409680652043064962416364852627910363792028140135284844491839733091542
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.30923302998394342073218652600877789179834818128620774385929741198319302805185
Short name T1
Test name
Test status
Simulation time 223941050 ps
CPU time 1.37 seconds
Started Nov 22 12:41:06 PM PST 23
Finished Nov 22 12:41:09 PM PST 23
Peak memory 199984 kb
Host smart-14e38f5b-71c7-4468-a43d-14de7c2f875e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30923302998394342073218652600877789179834818128620774385929741198319302805185 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 41.rstmgr_smoke.30923302998394342073218652600877789179834818128620774385929741198319302805185
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.50236273700682146086391177763758576732717009229829991973057301364034906046292
Short name T541
Test name
Test status
Simulation time 11131278308 ps
CPU time 39.49 seconds
Started Nov 22 12:41:10 PM PST 23
Finished Nov 22 12:41:51 PM PST 23
Peak memory 200068 kb
Host smart-f431ccbb-4267-4d96-ab02-3773d73e0839
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50236273700682146086391177763758576732717009229829991973057301364034906046292 -assert nopos
tproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.50236273700682146086391177763758576732717009229829991973057301364034906046292
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.44916909361911520338262544143801140541056398506744751972984768899657540321698
Short name T482
Test name
Test status
Simulation time 473109710 ps
CPU time 2.83 seconds
Started Nov 22 12:41:16 PM PST 23
Finished Nov 22 12:41:20 PM PST 23
Peak memory 199748 kb
Host smart-e6a32b22-8c4e-49e9-8d81-85fa8e3300b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44916909361911520338262544143801140541056398506744751972984768899657540321698 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 41.rstmgr_sw_rst.44916909361911520338262544143801140541056398506744751972984768899657540321698
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.104775233670514506617968805908774411965668579908050480569877197909036580711009
Short name T570
Test name
Test status
Simulation time 241232855 ps
CPU time 1.33 seconds
Started Nov 22 12:41:14 PM PST 23
Finished Nov 22 12:41:17 PM PST 23
Peak memory 199764 kb
Host smart-21e170ff-be77-41bb-9c07-39b878c5503e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104775233670514506617968805908774411965668579908050480569877197909036580711009 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.rstmgr_sw_rst_reset_race.104775233670514506617968805908774411965668579908050480569877197909036580711009
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.34300254151608682007856737003350245754457179330230939628498368505475084265984
Short name T60
Test name
Test status
Simulation time 78981557 ps
CPU time 0.75 seconds
Started Nov 22 12:41:22 PM PST 23
Finished Nov 22 12:41:24 PM PST 23
Peak memory 199600 kb
Host smart-52194525-07cc-44f4-a6c2-f4e2494dc312
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34300254151608682007856737003350245754457179330230939628498368505475084265984 -assert nopostpr
oc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.34300254151608682007856737003350245754457179330230939628498368505475084265984
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.55105035971949029132718380834343460227330834611103538716315322365240836389187
Short name T324
Test name
Test status
Simulation time 2162831562 ps
CPU time 8.19 seconds
Started Nov 22 12:41:37 PM PST 23
Finished Nov 22 12:41:46 PM PST 23
Peak memory 217100 kb
Host smart-3ad79f7e-f6b2-41b2-a2ba-c4dec858a26b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55105035971949029132718380834343460227330834611103538716315322365240836389187 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 42.rstmgr_leaf_rst_cnsty.55105035971949029132718380834343460227330834611103538716315322365240836389187
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.59815778448042634865966118313124995377743470133485823105288685164426570098648
Short name T451
Test name
Test status
Simulation time 243816210 ps
CPU time 1.13 seconds
Started Nov 22 12:41:20 PM PST 23
Finished Nov 22 12:41:22 PM PST 23
Peak memory 216724 kb
Host smart-f1763153-7d39-42d4-90b4-344bb161e379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59815778448042634865966118313124995377743470133485823105288685164426570098648 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.59815778448042634865966118313124995377743470133485823105288685164426570098648
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.49814625429586938469642239053344671121896306213844071825405302681353898429211
Short name T478
Test name
Test status
Simulation time 230357768 ps
CPU time 0.92 seconds
Started Nov 22 12:41:13 PM PST 23
Finished Nov 22 12:41:15 PM PST 23
Peak memory 199644 kb
Host smart-5356dd88-e8e4-43c7-88d7-bfa00203da22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49814625429586938469642239053344671121896306213844071825405302681353898429211 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.rstmgr_por_stretcher.49814625429586938469642239053344671121896306213844071825405302681353898429211
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.42292222431534175050443416260892429228726569202264674287295934232430875554974
Short name T371
Test name
Test status
Simulation time 1729953098 ps
CPU time 6.73 seconds
Started Nov 22 12:41:31 PM PST 23
Finished Nov 22 12:41:39 PM PST 23
Peak memory 199984 kb
Host smart-4d81d1ec-1b8c-4597-9a52-4e2338ff6d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42292222431534175050443416260892429228726569202264674287295934232430875554974 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 42.rstmgr_reset.42292222431534175050443416260892429228726569202264674287295934232430875554974
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.21086066186815824992407648115496952864419543184935453018188722578680860606499
Short name T70
Test name
Test status
Simulation time 170065619 ps
CPU time 1.21 seconds
Started Nov 22 12:41:17 PM PST 23
Finished Nov 22 12:41:19 PM PST 23
Peak memory 199884 kb
Host smart-002884f6-aff5-4463-914b-f370cbfc6740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21086066186815824992407648115496952864419543184935453018188722578680860606499 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.21086066186815824992407648115496952864419543184935453018188722578680860606499
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.24727462900886778351078283406156252404751441214348022266084025291370099682417
Short name T360
Test name
Test status
Simulation time 223941050 ps
CPU time 1.48 seconds
Started Nov 22 12:41:41 PM PST 23
Finished Nov 22 12:41:43 PM PST 23
Peak memory 200000 kb
Host smart-fb6c7039-ada7-4236-88df-e2c6dc9b3351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24727462900886778351078283406156252404751441214348022266084025291370099682417 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 42.rstmgr_smoke.24727462900886778351078283406156252404751441214348022266084025291370099682417
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.104330113998392802272037445817073407852467890431149077811479061159854790719772
Short name T294
Test name
Test status
Simulation time 11131278308 ps
CPU time 39.15 seconds
Started Nov 22 12:41:21 PM PST 23
Finished Nov 22 12:42:01 PM PST 23
Peak memory 200000 kb
Host smart-ed561382-4d1a-4aeb-acef-ca439a4e0332
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104330113998392802272037445817073407852467890431149077811479061159854790719772 -assert nopo
stproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.104330113998392802272037445817073407852467890431149077811479061159854790719772
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.35625198773910785174750628782770174890486929857959917611290616072490843781537
Short name T44
Test name
Test status
Simulation time 473109710 ps
CPU time 2.83 seconds
Started Nov 22 12:41:31 PM PST 23
Finished Nov 22 12:41:35 PM PST 23
Peak memory 199740 kb
Host smart-d30dc0e6-5eea-40d8-83cb-31da00d9c49f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35625198773910785174750628782770174890486929857959917611290616072490843781537 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 42.rstmgr_sw_rst.35625198773910785174750628782770174890486929857959917611290616072490843781537
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.31184459602768173761259888381888340940133782773398206962336978637192194660698
Short name T37
Test name
Test status
Simulation time 241232855 ps
CPU time 1.41 seconds
Started Nov 22 12:41:39 PM PST 23
Finished Nov 22 12:41:43 PM PST 23
Peak memory 199888 kb
Host smart-016f0a91-dc45-4299-9d97-845a7c0e0fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31184459602768173761259888381888340940133782773398206962336978637192194660698 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.rstmgr_sw_rst_reset_race.31184459602768173761259888381888340940133782773398206962336978637192194660698
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.82527572171738285629257058390070649067174219387752934627067257382623741706457
Short name T326
Test name
Test status
Simulation time 78981557 ps
CPU time 0.77 seconds
Started Nov 22 12:41:51 PM PST 23
Finished Nov 22 12:42:03 PM PST 23
Peak memory 199588 kb
Host smart-c111ed64-edde-4fee-8fb0-9cd22c852d5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82527572171738285629257058390070649067174219387752934627067257382623741706457 -assert nopostpr
oc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.82527572171738285629257058390070649067174219387752934627067257382623741706457
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.77858708381321416972283375114987533796995684799836722998628528471881865349349
Short name T544
Test name
Test status
Simulation time 2162831562 ps
CPU time 8.56 seconds
Started Nov 22 12:41:36 PM PST 23
Finished Nov 22 12:41:46 PM PST 23
Peak memory 217068 kb
Host smart-5e7ab43a-1080-4677-b7b4-1a9536477fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77858708381321416972283375114987533796995684799836722998628528471881865349349 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 43.rstmgr_leaf_rst_cnsty.77858708381321416972283375114987533796995684799836722998628528471881865349349
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.20110495940622510734061347997441744182205331584412766028631354134351837765507
Short name T467
Test name
Test status
Simulation time 243816210 ps
CPU time 1.04 seconds
Started Nov 22 12:41:35 PM PST 23
Finished Nov 22 12:41:37 PM PST 23
Peak memory 216848 kb
Host smart-ec50e38b-3690-4fd7-b472-e925d557fa22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20110495940622510734061347997441744182205331584412766028631354134351837765507 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.20110495940622510734061347997441744182205331584412766028631354134351837765507
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.9206412019374119483732778709478942266714508109874422637201859725074350506069
Short name T420
Test name
Test status
Simulation time 230357768 ps
CPU time 0.98 seconds
Started Nov 22 12:41:48 PM PST 23
Finished Nov 22 12:41:52 PM PST 23
Peak memory 199684 kb
Host smart-076d8a7d-f460-4d41-9bd4-e771a7aa3683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9206412019374119483732778709478942266714508109874422637201859725074350506069 -assert nopostproc +UVM_TESTNAME=rstmgr_bas
e_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 43.rstmgr_por_stretcher.9206412019374119483732778709478942266714508109874422637201859725074350506069
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.105321249251564621057910413919952826478447204823274804346211035063200052415463
Short name T603
Test name
Test status
Simulation time 1729953098 ps
CPU time 6.42 seconds
Started Nov 22 12:42:08 PM PST 23
Finished Nov 22 12:42:19 PM PST 23
Peak memory 200080 kb
Host smart-185e6fdb-9d0a-427e-955b-db17ff58fa2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105321249251564621057910413919952826478447204823274804346211035063200052415463 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 43.rstmgr_reset.105321249251564621057910413919952826478447204823274804346211035063200052415463
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.36582867738507054896934555047342561003691480184743344384381968755342633666025
Short name T332
Test name
Test status
Simulation time 170065619 ps
CPU time 1.18 seconds
Started Nov 22 12:41:38 PM PST 23
Finished Nov 22 12:41:40 PM PST 23
Peak memory 199740 kb
Host smart-b896b10c-b346-4457-8fc6-af4d785f2493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36582867738507054896934555047342561003691480184743344384381968755342633666025 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.36582867738507054896934555047342561003691480184743344384381968755342633666025
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.101503665667867108286300496194854918925633702368569250357121400689811136320255
Short name T303
Test name
Test status
Simulation time 223941050 ps
CPU time 1.39 seconds
Started Nov 22 12:41:50 PM PST 23
Finished Nov 22 12:42:01 PM PST 23
Peak memory 200000 kb
Host smart-86ab8a95-36e6-4aec-b704-d06d56acd463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101503665667867108286300496194854918925633702368569250357121400689811136320255 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 43.rstmgr_smoke.101503665667867108286300496194854918925633702368569250357121400689811136320255
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.46592490858953877460128453280032146500853550049525184968628259177998901194059
Short name T71
Test name
Test status
Simulation time 11131278308 ps
CPU time 38.04 seconds
Started Nov 22 12:41:35 PM PST 23
Finished Nov 22 12:42:14 PM PST 23
Peak memory 200052 kb
Host smart-f4bc9a0c-64f0-4125-92c1-1440baa7d48b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46592490858953877460128453280032146500853550049525184968628259177998901194059 -assert nopos
tproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.46592490858953877460128453280032146500853550049525184968628259177998901194059
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.106988084802237545151390000000850778665012864579035815746299479636277979201227
Short name T8
Test name
Test status
Simulation time 473109710 ps
CPU time 2.67 seconds
Started Nov 22 12:41:31 PM PST 23
Finished Nov 22 12:41:34 PM PST 23
Peak memory 199872 kb
Host smart-80f27ffb-fc18-46fa-9361-46466a35c8ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106988084802237545151390000000850778665012864579035815746299479636277979201227 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 43.rstmgr_sw_rst.106988084802237545151390000000850778665012864579035815746299479636277979201227
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.92375989861853701660361407477589609456121519048874308401837040694137926624962
Short name T446
Test name
Test status
Simulation time 241232855 ps
CPU time 1.43 seconds
Started Nov 22 12:41:39 PM PST 23
Finished Nov 22 12:41:41 PM PST 23
Peak memory 199736 kb
Host smart-d2d39516-baa5-4493-8d93-74173cca8b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92375989861853701660361407477589609456121519048874308401837040694137926624962 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.rstmgr_sw_rst_reset_race.92375989861853701660361407477589609456121519048874308401837040694137926624962
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.44257029915041764337697847535613571558444106752903877907320305509494611809959
Short name T595
Test name
Test status
Simulation time 78981557 ps
CPU time 0.77 seconds
Started Nov 22 12:41:58 PM PST 23
Finished Nov 22 12:42:05 PM PST 23
Peak memory 199672 kb
Host smart-ed0c9d95-4aae-4231-8a63-fca94f2663e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44257029915041764337697847535613571558444106752903877907320305509494611809959 -assert nopostpr
oc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.44257029915041764337697847535613571558444106752903877907320305509494611809959
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.78204861811671390068269931898188821280683171511659184643264507562169081178868
Short name T525
Test name
Test status
Simulation time 2162831562 ps
CPU time 8.16 seconds
Started Nov 22 12:41:42 PM PST 23
Finished Nov 22 12:41:52 PM PST 23
Peak memory 217100 kb
Host smart-cc359303-9a7c-4ea3-8f13-68da0c746f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78204861811671390068269931898188821280683171511659184643264507562169081178868 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 44.rstmgr_leaf_rst_cnsty.78204861811671390068269931898188821280683171511659184643264507562169081178868
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.64080040230818744302770054480464484188983148811833931029202555123448739927275
Short name T571
Test name
Test status
Simulation time 243816210 ps
CPU time 1.11 seconds
Started Nov 22 12:41:41 PM PST 23
Finished Nov 22 12:41:43 PM PST 23
Peak memory 216784 kb
Host smart-d5766a72-a280-454f-a530-bf2b06704867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64080040230818744302770054480464484188983148811833931029202555123448739927275 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.64080040230818744302770054480464484188983148811833931029202555123448739927275
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.49636078916278257463373533317566454303931615735859556109201099731399397227168
Short name T14
Test name
Test status
Simulation time 230357768 ps
CPU time 0.93 seconds
Started Nov 22 12:41:53 PM PST 23
Finished Nov 22 12:42:05 PM PST 23
Peak memory 199664 kb
Host smart-e5ef1d6c-8371-442e-820f-cc85c588b514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49636078916278257463373533317566454303931615735859556109201099731399397227168 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.rstmgr_por_stretcher.49636078916278257463373533317566454303931615735859556109201099731399397227168
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.112154677891942189340306647001372724228769397642447537315288608590893295504782
Short name T65
Test name
Test status
Simulation time 1729953098 ps
CPU time 6.56 seconds
Started Nov 22 12:41:58 PM PST 23
Finished Nov 22 12:42:12 PM PST 23
Peak memory 200088 kb
Host smart-afa8d55d-b678-4acf-a700-7f7f5f86c102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112154677891942189340306647001372724228769397642447537315288608590893295504782 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 44.rstmgr_reset.112154677891942189340306647001372724228769397642447537315288608590893295504782
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.95134344820014344429254346351715429707758300974574879511809050961077681400593
Short name T408
Test name
Test status
Simulation time 170065619 ps
CPU time 1.13 seconds
Started Nov 22 12:41:51 PM PST 23
Finished Nov 22 12:42:03 PM PST 23
Peak memory 199840 kb
Host smart-fac9c0cb-13d9-4834-b070-c16b8c0071d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95134344820014344429254346351715429707758300974574879511809050961077681400593 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.95134344820014344429254346351715429707758300974574879511809050961077681400593
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.99847650677250112126901142483883643520677476635804516680026387468106585076257
Short name T348
Test name
Test status
Simulation time 223941050 ps
CPU time 1.39 seconds
Started Nov 22 12:41:50 PM PST 23
Finished Nov 22 12:42:01 PM PST 23
Peak memory 200004 kb
Host smart-7e165dbd-659d-453a-bf50-fc8d02b71f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99847650677250112126901142483883643520677476635804516680026387468106585076257 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 44.rstmgr_smoke.99847650677250112126901142483883643520677476635804516680026387468106585076257
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.85827827423079812404433127585626919167606313834819213142448865943768531210098
Short name T122
Test name
Test status
Simulation time 11131278308 ps
CPU time 38.23 seconds
Started Nov 22 12:41:47 PM PST 23
Finished Nov 22 12:42:29 PM PST 23
Peak memory 200120 kb
Host smart-67f79a22-32a3-4965-90d1-ee9eebe5af2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85827827423079812404433127585626919167606313834819213142448865943768531210098 -assert nopos
tproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.85827827423079812404433127585626919167606313834819213142448865943768531210098
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.47424099848804820208856981386169192479955797995093077660581650213284493447654
Short name T409
Test name
Test status
Simulation time 473109710 ps
CPU time 2.5 seconds
Started Nov 22 12:41:45 PM PST 23
Finished Nov 22 12:41:51 PM PST 23
Peak memory 199788 kb
Host smart-a2809583-4db5-43d5-9c57-b4d2dd1c7ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47424099848804820208856981386169192479955797995093077660581650213284493447654 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 44.rstmgr_sw_rst.47424099848804820208856981386169192479955797995093077660581650213284493447654
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.29181066472415314767028654981188079037892100658750937597197753025159531885507
Short name T269
Test name
Test status
Simulation time 241232855 ps
CPU time 1.41 seconds
Started Nov 22 12:41:42 PM PST 23
Finished Nov 22 12:41:45 PM PST 23
Peak memory 199888 kb
Host smart-f1f162ab-bddd-4a6a-a59b-b6238a9f5d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29181066472415314767028654981188079037892100658750937597197753025159531885507 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 44.rstmgr_sw_rst_reset_race.29181066472415314767028654981188079037892100658750937597197753025159531885507
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.111666656192521560050291729326013085383360182717099403024365295832947135635916
Short name T95
Test name
Test status
Simulation time 78981557 ps
CPU time 0.77 seconds
Started Nov 22 12:41:44 PM PST 23
Finished Nov 22 12:41:49 PM PST 23
Peak memory 199660 kb
Host smart-22b006c3-8da5-4a52-a89a-27b6335ce2c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111666656192521560050291729326013085383360182717099403024365295832947135635916 -assert nopostp
roc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.111666656192521560050291729326013085383360182717099403024365295832947135635916
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.92808286813451217954899659818305301980278383633473898113963680553295609155810
Short name T26
Test name
Test status
Simulation time 2162831562 ps
CPU time 8.15 seconds
Started Nov 22 12:42:21 PM PST 23
Finished Nov 22 12:42:32 PM PST 23
Peak memory 217012 kb
Host smart-9c43ecbf-b1d1-4ae1-a0f7-73235d5b6b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92808286813451217954899659818305301980278383633473898113963680553295609155810 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 45.rstmgr_leaf_rst_cnsty.92808286813451217954899659818305301980278383633473898113963680553295609155810
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.32547178142540135819126038861464585119813733541580044643937794344248706091511
Short name T524
Test name
Test status
Simulation time 243816210 ps
CPU time 1.08 seconds
Started Nov 22 12:41:47 PM PST 23
Finished Nov 22 12:41:52 PM PST 23
Peak memory 216856 kb
Host smart-0a592618-0990-4afc-82a7-627a2963e690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32547178142540135819126038861464585119813733541580044643937794344248706091511 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.32547178142540135819126038861464585119813733541580044643937794344248706091511
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.75030348258308288618002592063229464558058187998446231987951100237462808701097
Short name T271
Test name
Test status
Simulation time 230357768 ps
CPU time 0.94 seconds
Started Nov 22 12:41:44 PM PST 23
Finished Nov 22 12:41:47 PM PST 23
Peak memory 199648 kb
Host smart-14a23e02-28b0-4a1d-9cf8-3c6738dc1d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75030348258308288618002592063229464558058187998446231987951100237462808701097 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.rstmgr_por_stretcher.75030348258308288618002592063229464558058187998446231987951100237462808701097
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.97465407230222987000456606360761253425764113811441556472476648995071485366801
Short name T144
Test name
Test status
Simulation time 1729953098 ps
CPU time 6.57 seconds
Started Nov 22 12:41:51 PM PST 23
Finished Nov 22 12:42:08 PM PST 23
Peak memory 199992 kb
Host smart-bc3f208d-02a1-449f-a405-7fa1799b0ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97465407230222987000456606360761253425764113811441556472476648995071485366801 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 45.rstmgr_reset.97465407230222987000456606360761253425764113811441556472476648995071485366801
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.40611241616630836168746204491520263814426196736580684452880541222453275599182
Short name T449
Test name
Test status
Simulation time 170065619 ps
CPU time 1.15 seconds
Started Nov 22 12:41:53 PM PST 23
Finished Nov 22 12:42:05 PM PST 23
Peak memory 199908 kb
Host smart-23b2c5fb-7064-46b0-a60c-e41dacc776ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40611241616630836168746204491520263814426196736580684452880541222453275599182 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.40611241616630836168746204491520263814426196736580684452880541222453275599182
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.74921545679555377842791247836825300265112509097137342874510387432903757042670
Short name T433
Test name
Test status
Simulation time 223941050 ps
CPU time 1.33 seconds
Started Nov 22 12:41:45 PM PST 23
Finished Nov 22 12:41:50 PM PST 23
Peak memory 199984 kb
Host smart-8814fa0b-94d0-47eb-b6b0-3044f199c2db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74921545679555377842791247836825300265112509097137342874510387432903757042670 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 45.rstmgr_smoke.74921545679555377842791247836825300265112509097137342874510387432903757042670
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.96084671991014788135749486885884804978972253819789761312736434583114446771674
Short name T298
Test name
Test status
Simulation time 11131278308 ps
CPU time 40.36 seconds
Started Nov 22 12:41:49 PM PST 23
Finished Nov 22 12:42:39 PM PST 23
Peak memory 200052 kb
Host smart-ec971062-053a-443f-bfaf-409309f00b75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96084671991014788135749486885884804978972253819789761312736434583114446771674 -assert nopos
tproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.96084671991014788135749486885884804978972253819789761312736434583114446771674
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.55863505307639860615646381302472173181088594988121196723541657178410053224208
Short name T499
Test name
Test status
Simulation time 473109710 ps
CPU time 2.66 seconds
Started Nov 22 12:41:57 PM PST 23
Finished Nov 22 12:42:07 PM PST 23
Peak memory 199852 kb
Host smart-733ebd2c-0ba8-4d08-b259-7213978ae412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55863505307639860615646381302472173181088594988121196723541657178410053224208 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 45.rstmgr_sw_rst.55863505307639860615646381302472173181088594988121196723541657178410053224208
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.7878562896592166395897932049848622054079660744419275658049577181185196959516
Short name T437
Test name
Test status
Simulation time 241232855 ps
CPU time 1.47 seconds
Started Nov 22 12:41:47 PM PST 23
Finished Nov 22 12:41:52 PM PST 23
Peak memory 199800 kb
Host smart-d9cca201-e845-4aea-a7db-f95f0d015658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7878562896592166395897932049848622054079660744419275658049577181185196959516 -assert nopostproc +UVM_TESTNAME=rstmgr_bas
e_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 45.rstmgr_sw_rst_reset_race.7878562896592166395897932049848622054079660744419275658049577181185196959516
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.2445523424006323347671824075167268196540768271698406049224910415166157205993
Short name T36
Test name
Test status
Simulation time 78981557 ps
CPU time 0.76 seconds
Started Nov 22 12:42:05 PM PST 23
Finished Nov 22 12:42:13 PM PST 23
Peak memory 199720 kb
Host smart-178e5e4f-2370-41c1-bd2c-c0c890411774
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445523424006323347671824075167268196540768271698406049224910415166157205993 -assert nopostpro
c +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.2445523424006323347671824075167268196540768271698406049224910415166157205993
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.10195858899341507668676286461351212086386230525064192763945453440665708252965
Short name T493
Test name
Test status
Simulation time 2162831562 ps
CPU time 8.06 seconds
Started Nov 22 12:41:58 PM PST 23
Finished Nov 22 12:42:13 PM PST 23
Peak memory 217060 kb
Host smart-5b38fda4-9049-41b4-ab07-25f8d0c72291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10195858899341507668676286461351212086386230525064192763945453440665708252965 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 46.rstmgr_leaf_rst_cnsty.10195858899341507668676286461351212086386230525064192763945453440665708252965
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.72659924324440075156508958200657675683701946199458743692179092407248325814333
Short name T442
Test name
Test status
Simulation time 243816210 ps
CPU time 1.11 seconds
Started Nov 22 12:41:51 PM PST 23
Finished Nov 22 12:42:03 PM PST 23
Peak memory 216744 kb
Host smart-1b8b9708-9736-416c-8949-13cd66198288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72659924324440075156508958200657675683701946199458743692179092407248325814333 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.72659924324440075156508958200657675683701946199458743692179092407248325814333
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.50512788548498564785521761743338760230161187133619842792217571235720113695694
Short name T280
Test name
Test status
Simulation time 230357768 ps
CPU time 0.92 seconds
Started Nov 22 12:41:49 PM PST 23
Finished Nov 22 12:42:00 PM PST 23
Peak memory 199616 kb
Host smart-49c0c612-38ee-4bcc-b0cb-dc1528359279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50512788548498564785521761743338760230161187133619842792217571235720113695694 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.rstmgr_por_stretcher.50512788548498564785521761743338760230161187133619842792217571235720113695694
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.102645715328709991441950502483247748382537053687764898112006249270719434306528
Short name T364
Test name
Test status
Simulation time 1729953098 ps
CPU time 6.79 seconds
Started Nov 22 12:41:46 PM PST 23
Finished Nov 22 12:41:57 PM PST 23
Peak memory 199960 kb
Host smart-d2e33742-023a-40c3-8dd8-dd8b9268624d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102645715328709991441950502483247748382537053687764898112006249270719434306528 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 46.rstmgr_reset.102645715328709991441950502483247748382537053687764898112006249270719434306528
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.107019048210359161789388760154509486184858639321013680943214178743344039393193
Short name T24
Test name
Test status
Simulation time 170065619 ps
CPU time 1.14 seconds
Started Nov 22 12:41:59 PM PST 23
Finished Nov 22 12:42:09 PM PST 23
Peak memory 199908 kb
Host smart-e7b134d1-5886-4ef2-82db-09dc7cf7bd35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107019048210359161789388760154509486184858639321013680943214178743344039393193 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.107019048210359161789388760154509486184858639321013680943214178743344039393193
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.77817898440181697251529015970279574687564870928027431674317517197674778119458
Short name T470
Test name
Test status
Simulation time 223941050 ps
CPU time 1.4 seconds
Started Nov 22 12:41:43 PM PST 23
Finished Nov 22 12:41:46 PM PST 23
Peak memory 200016 kb
Host smart-e1a95211-ef0b-4d80-a2e6-f75b0e183f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77817898440181697251529015970279574687564870928027431674317517197674778119458 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 46.rstmgr_smoke.77817898440181697251529015970279574687564870928027431674317517197674778119458
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.83349435717307701347045771561485425826545173939153695423346101803251635133856
Short name T234
Test name
Test status
Simulation time 11131278308 ps
CPU time 37.69 seconds
Started Nov 22 12:41:46 PM PST 23
Finished Nov 22 12:42:28 PM PST 23
Peak memory 200024 kb
Host smart-68967fdb-c544-4af7-ba78-b27a0cbc8eb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83349435717307701347045771561485425826545173939153695423346101803251635133856 -assert nopos
tproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.83349435717307701347045771561485425826545173939153695423346101803251635133856
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.14356922605017817347360147334476947762312500251461607661266441700943929802300
Short name T561
Test name
Test status
Simulation time 473109710 ps
CPU time 2.64 seconds
Started Nov 22 12:41:58 PM PST 23
Finished Nov 22 12:42:07 PM PST 23
Peak memory 199804 kb
Host smart-6f188b79-7ee8-48f0-8af4-517672e572c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14356922605017817347360147334476947762312500251461607661266441700943929802300 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 46.rstmgr_sw_rst.14356922605017817347360147334476947762312500251461607661266441700943929802300
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.82234456064734567945071570019943794167770375725817132694210421934278868195524
Short name T352
Test name
Test status
Simulation time 241232855 ps
CPU time 1.37 seconds
Started Nov 22 12:41:48 PM PST 23
Finished Nov 22 12:41:52 PM PST 23
Peak memory 199888 kb
Host smart-d2546541-1ea0-4589-87c5-27dbdb65c351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82234456064734567945071570019943794167770375725817132694210421934278868195524 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 46.rstmgr_sw_rst_reset_race.82234456064734567945071570019943794167770375725817132694210421934278868195524
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.41159033091696994961873320265745432265041468909509808822916643595092315846646
Short name T253
Test name
Test status
Simulation time 78981557 ps
CPU time 0.84 seconds
Started Nov 22 12:41:55 PM PST 23
Finished Nov 22 12:42:05 PM PST 23
Peak memory 199616 kb
Host smart-941cf99d-f081-4829-ae7b-478001744234
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41159033091696994961873320265745432265041468909509808822916643595092315846646 -assert nopostpr
oc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.41159033091696994961873320265745432265041468909509808822916643595092315846646
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.85204422088905103703814564416082123003600093443996262404835970662641775523836
Short name T585
Test name
Test status
Simulation time 2162831562 ps
CPU time 7.81 seconds
Started Nov 22 12:42:12 PM PST 23
Finished Nov 22 12:42:25 PM PST 23
Peak memory 217000 kb
Host smart-b8283d51-4e8c-4ccb-9245-34bd6bd63d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85204422088905103703814564416082123003600093443996262404835970662641775523836 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 47.rstmgr_leaf_rst_cnsty.85204422088905103703814564416082123003600093443996262404835970662641775523836
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.87192020612822397357431058547862748744293333145614035788242728220086409742372
Short name T458
Test name
Test status
Simulation time 243816210 ps
CPU time 1.17 seconds
Started Nov 22 12:41:55 PM PST 23
Finished Nov 22 12:42:05 PM PST 23
Peak memory 216736 kb
Host smart-9db2bb30-d027-43d7-88c1-dff1c5dea98e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87192020612822397357431058547862748744293333145614035788242728220086409742372 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.87192020612822397357431058547862748744293333145614035788242728220086409742372
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.13016728060929597281638858757031526422857963551796090717009728885996371009563
Short name T601
Test name
Test status
Simulation time 230357768 ps
CPU time 0.91 seconds
Started Nov 22 12:41:49 PM PST 23
Finished Nov 22 12:41:59 PM PST 23
Peak memory 199680 kb
Host smart-59f6c944-75f1-401d-bdd2-17e3eed322e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13016728060929597281638858757031526422857963551796090717009728885996371009563 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.rstmgr_por_stretcher.13016728060929597281638858757031526422857963551796090717009728885996371009563
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.75321377976045882942237047739919906780826479490761344788484134741942846595970
Short name T131
Test name
Test status
Simulation time 1729953098 ps
CPU time 6.75 seconds
Started Nov 22 12:41:47 PM PST 23
Finished Nov 22 12:41:57 PM PST 23
Peak memory 200032 kb
Host smart-dfb83f44-3691-495b-8bc6-c95b199f59db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75321377976045882942237047739919906780826479490761344788484134741942846595970 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 47.rstmgr_reset.75321377976045882942237047739919906780826479490761344788484134741942846595970
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.47182594495070911754780634135194734299911196191159019885953181140058613932903
Short name T506
Test name
Test status
Simulation time 170065619 ps
CPU time 1.15 seconds
Started Nov 22 12:42:07 PM PST 23
Finished Nov 22 12:42:14 PM PST 23
Peak memory 199784 kb
Host smart-10556b40-5a4b-4947-bfa1-94ce21727f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47182594495070911754780634135194734299911196191159019885953181140058613932903 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.47182594495070911754780634135194734299911196191159019885953181140058613932903
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.98032793522134060007511783262641100298575062255434310277662692128305346106974
Short name T547
Test name
Test status
Simulation time 223941050 ps
CPU time 1.44 seconds
Started Nov 22 12:41:59 PM PST 23
Finished Nov 22 12:42:11 PM PST 23
Peak memory 200004 kb
Host smart-364ef17b-e4f3-44d6-9b5b-ed429584862c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98032793522134060007511783262641100298575062255434310277662692128305346106974 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 47.rstmgr_smoke.98032793522134060007511783262641100298575062255434310277662692128305346106974
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.64212557613962523857557753741751214102252143367661037226470447425249876319466
Short name T501
Test name
Test status
Simulation time 11131278308 ps
CPU time 40.12 seconds
Started Nov 22 12:41:55 PM PST 23
Finished Nov 22 12:42:44 PM PST 23
Peak memory 199952 kb
Host smart-d3d3c9f5-b6a9-4124-8e6e-e27e8a422040
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64212557613962523857557753741751214102252143367661037226470447425249876319466 -assert nopos
tproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.64212557613962523857557753741751214102252143367661037226470447425249876319466
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.60044853735206142176487830574891266070873455767754824472383186046668497152292
Short name T329
Test name
Test status
Simulation time 473109710 ps
CPU time 2.71 seconds
Started Nov 22 12:41:48 PM PST 23
Finished Nov 22 12:41:54 PM PST 23
Peak memory 199828 kb
Host smart-9815372e-2cfe-441d-8480-ba7bd8234606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60044853735206142176487830574891266070873455767754824472383186046668497152292 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 47.rstmgr_sw_rst.60044853735206142176487830574891266070873455767754824472383186046668497152292
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.5402923885153783570364303538628669776839563666989473389170603542518181420219
Short name T356
Test name
Test status
Simulation time 241232855 ps
CPU time 1.41 seconds
Started Nov 22 12:41:57 PM PST 23
Finished Nov 22 12:42:06 PM PST 23
Peak memory 199784 kb
Host smart-a3af80f4-4575-4220-9dce-2136547645c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5402923885153783570364303538628669776839563666989473389170603542518181420219 -assert nopostproc +UVM_TESTNAME=rstmgr_bas
e_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 47.rstmgr_sw_rst_reset_race.5402923885153783570364303538628669776839563666989473389170603542518181420219
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.81189433874981047741340059188642835949696918176548469827644842083941013332684
Short name T491
Test name
Test status
Simulation time 78981557 ps
CPU time 0.76 seconds
Started Nov 22 12:42:02 PM PST 23
Finished Nov 22 12:42:12 PM PST 23
Peak memory 199592 kb
Host smart-3ef9b7ed-7721-408c-a343-944bb32f9f46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81189433874981047741340059188642835949696918176548469827644842083941013332684 -assert nopostpr
oc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.81189433874981047741340059188642835949696918176548469827644842083941013332684
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.57862492641561642660986597080846378655857830223765764642154339590145097468200
Short name T486
Test name
Test status
Simulation time 2162831562 ps
CPU time 7.83 seconds
Started Nov 22 12:42:10 PM PST 23
Finished Nov 22 12:42:21 PM PST 23
Peak memory 216992 kb
Host smart-d9c80283-f511-47ba-adf0-93a76c2b36ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57862492641561642660986597080846378655857830223765764642154339590145097468200 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 48.rstmgr_leaf_rst_cnsty.57862492641561642660986597080846378655857830223765764642154339590145097468200
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.83372081503624950679875372553738159527870775694415180846470304734268414502637
Short name T134
Test name
Test status
Simulation time 243816210 ps
CPU time 1.08 seconds
Started Nov 22 12:41:57 PM PST 23
Finished Nov 22 12:42:05 PM PST 23
Peak memory 216784 kb
Host smart-52e12120-1469-4bc9-9bbc-68629cb645e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83372081503624950679875372553738159527870775694415180846470304734268414502637 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.83372081503624950679875372553738159527870775694415180846470304734268414502637
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.92814443710600754444367524208783058217038463336811496386811925852287783285662
Short name T590
Test name
Test status
Simulation time 230357768 ps
CPU time 0.93 seconds
Started Nov 22 12:42:12 PM PST 23
Finished Nov 22 12:42:19 PM PST 23
Peak memory 199592 kb
Host smart-66ef9cf5-2730-46db-859f-bc31b53ca4e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92814443710600754444367524208783058217038463336811496386811925852287783285662 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.rstmgr_por_stretcher.92814443710600754444367524208783058217038463336811496386811925852287783285662
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.68737745859426891945565716898637994408579869559705352823218403592335088515029
Short name T38
Test name
Test status
Simulation time 1729953098 ps
CPU time 6.55 seconds
Started Nov 22 12:41:56 PM PST 23
Finished Nov 22 12:42:11 PM PST 23
Peak memory 199960 kb
Host smart-631f4c50-c741-4254-94d4-715d8c707c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68737745859426891945565716898637994408579869559705352823218403592335088515029 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 48.rstmgr_reset.68737745859426891945565716898637994408579869559705352823218403592335088515029
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.70325586607510668366778614014271479973936038365711677073575416461881883864056
Short name T139
Test name
Test status
Simulation time 170065619 ps
CPU time 1.17 seconds
Started Nov 22 12:42:05 PM PST 23
Finished Nov 22 12:42:13 PM PST 23
Peak memory 199776 kb
Host smart-bbd13d43-dd24-4a1a-82d0-82b7e5a62197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70325586607510668366778614014271479973936038365711677073575416461881883864056 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.70325586607510668366778614014271479973936038365711677073575416461881883864056
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.16051016890488580522004079835863763051913131474911589077350685975669487725986
Short name T121
Test name
Test status
Simulation time 223941050 ps
CPU time 1.39 seconds
Started Nov 22 12:41:56 PM PST 23
Finished Nov 22 12:42:06 PM PST 23
Peak memory 199912 kb
Host smart-822708cd-d16c-4d36-9cdb-40ca21ef295d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16051016890488580522004079835863763051913131474911589077350685975669487725986 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 48.rstmgr_smoke.16051016890488580522004079835863763051913131474911589077350685975669487725986
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.65012269132302751221710350948950409624427873848576444818582366564189333508857
Short name T136
Test name
Test status
Simulation time 11131278308 ps
CPU time 38.63 seconds
Started Nov 22 12:42:04 PM PST 23
Finished Nov 22 12:42:50 PM PST 23
Peak memory 199996 kb
Host smart-7e8295e9-caca-46c7-b48f-3f7379720baf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65012269132302751221710350948950409624427873848576444818582366564189333508857 -assert nopos
tproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.65012269132302751221710350948950409624427873848576444818582366564189333508857
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.109642330758581899204250366506052833429821525004931015275705893323462155539358
Short name T41
Test name
Test status
Simulation time 473109710 ps
CPU time 2.73 seconds
Started Nov 22 12:41:50 PM PST 23
Finished Nov 22 12:42:03 PM PST 23
Peak memory 199832 kb
Host smart-c490e687-fa0d-4664-8890-b633fadbb5dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109642330758581899204250366506052833429821525004931015275705893323462155539358 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 48.rstmgr_sw_rst.109642330758581899204250366506052833429821525004931015275705893323462155539358
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.37914996747951840633324279819125281737385040111516554611651161690276434532134
Short name T327
Test name
Test status
Simulation time 241232855 ps
CPU time 1.38 seconds
Started Nov 22 12:41:53 PM PST 23
Finished Nov 22 12:42:05 PM PST 23
Peak memory 199856 kb
Host smart-4529f3f8-06b1-48de-b793-f954f37ae636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37914996747951840633324279819125281737385040111516554611651161690276434532134 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 48.rstmgr_sw_rst_reset_race.37914996747951840633324279819125281737385040111516554611651161690276434532134
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.61682229023679848626536594062703534377572496394817518349367650642028358575950
Short name T504
Test name
Test status
Simulation time 78981557 ps
CPU time 0.77 seconds
Started Nov 22 12:42:06 PM PST 23
Finished Nov 22 12:42:13 PM PST 23
Peak memory 199676 kb
Host smart-3459443e-886a-4a12-999d-fedd5205671e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61682229023679848626536594062703534377572496394817518349367650642028358575950 -assert nopostpr
oc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.61682229023679848626536594062703534377572496394817518349367650642028358575950
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.55858553275873381987924402439606771262617570307951745631533943149054296333751
Short name T459
Test name
Test status
Simulation time 2162831562 ps
CPU time 7.69 seconds
Started Nov 22 12:41:55 PM PST 23
Finished Nov 22 12:42:12 PM PST 23
Peak memory 217100 kb
Host smart-0c44876e-5382-492a-b86f-a1615d2fcbb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55858553275873381987924402439606771262617570307951745631533943149054296333751 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 49.rstmgr_leaf_rst_cnsty.55858553275873381987924402439606771262617570307951745631533943149054296333751
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.37538980723589320389577023881346212833681296851598395445197081480379823364192
Short name T468
Test name
Test status
Simulation time 243816210 ps
CPU time 1.07 seconds
Started Nov 22 12:42:02 PM PST 23
Finished Nov 22 12:42:13 PM PST 23
Peak memory 216836 kb
Host smart-b94524a5-11c8-4507-9e51-891d33c66bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37538980723589320389577023881346212833681296851598395445197081480379823364192 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.37538980723589320389577023881346212833681296851598395445197081480379823364192
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.105697779769145668506781713316333959692588556861614996629024074976929606376594
Short name T285
Test name
Test status
Simulation time 230357768 ps
CPU time 0.92 seconds
Started Nov 22 12:42:11 PM PST 23
Finished Nov 22 12:42:17 PM PST 23
Peak memory 199684 kb
Host smart-32e5cbe1-f339-49df-94fb-d4e1859c07cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105697779769145668506781713316333959692588556861614996629024074976929606376594 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 49.rstmgr_por_stretcher.105697779769145668506781713316333959692588556861614996629024074976929606376594
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.30336561818868025430992546569707840622459218659932403861318200267696537392452
Short name T267
Test name
Test status
Simulation time 1729953098 ps
CPU time 6.56 seconds
Started Nov 22 12:42:13 PM PST 23
Finished Nov 22 12:42:24 PM PST 23
Peak memory 200088 kb
Host smart-2baec98f-a157-4458-b6ec-bc90ca538372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30336561818868025430992546569707840622459218659932403861318200267696537392452 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 49.rstmgr_reset.30336561818868025430992546569707840622459218659932403861318200267696537392452
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.112400341884505345622751154097548190842874762146945979728668599516887452121783
Short name T341
Test name
Test status
Simulation time 170065619 ps
CPU time 1.12 seconds
Started Nov 22 12:42:11 PM PST 23
Finished Nov 22 12:42:18 PM PST 23
Peak memory 199896 kb
Host smart-1f34b2df-5c91-48f3-b0cf-0d62444f1591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112400341884505345622751154097548190842874762146945979728668599516887452121783 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.112400341884505345622751154097548190842874762146945979728668599516887452121783
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.98254953779903394880439730532838859205386561521235298057995143220705197121566
Short name T597
Test name
Test status
Simulation time 223941050 ps
CPU time 1.42 seconds
Started Nov 22 12:42:02 PM PST 23
Finished Nov 22 12:42:13 PM PST 23
Peak memory 200012 kb
Host smart-17a84450-b62b-4fef-ad7d-06d60c08cb33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98254953779903394880439730532838859205386561521235298057995143220705197121566 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 49.rstmgr_smoke.98254953779903394880439730532838859205386561521235298057995143220705197121566
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.103315505305052167620077199522781644661574717600835367694299241824626811006678
Short name T419
Test name
Test status
Simulation time 11131278308 ps
CPU time 41.5 seconds
Started Nov 22 12:41:57 PM PST 23
Finished Nov 22 12:42:46 PM PST 23
Peak memory 200076 kb
Host smart-bfddc2bf-1a32-462f-9bfe-d0e32a059834
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103315505305052167620077199522781644661574717600835367694299241824626811006678 -assert nopo
stproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.103315505305052167620077199522781644661574717600835367694299241824626811006678
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.61941550479100258971122643918104835524164774500431724696190816596221567542317
Short name T273
Test name
Test status
Simulation time 473109710 ps
CPU time 2.63 seconds
Started Nov 22 12:42:07 PM PST 23
Finished Nov 22 12:42:15 PM PST 23
Peak memory 199828 kb
Host smart-bee27afa-01a5-4732-a170-10838039550a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61941550479100258971122643918104835524164774500431724696190816596221567542317 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 49.rstmgr_sw_rst.61941550479100258971122643918104835524164774500431724696190816596221567542317
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.84333070572240046062114391096020536909892171034267587351298392577874747836355
Short name T374
Test name
Test status
Simulation time 241232855 ps
CPU time 1.38 seconds
Started Nov 22 12:41:55 PM PST 23
Finished Nov 22 12:42:06 PM PST 23
Peak memory 199868 kb
Host smart-06c9ff69-2e5c-4e9c-b5e6-8a23f08f6421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84333070572240046062114391096020536909892171034267587351298392577874747836355 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.rstmgr_sw_rst_reset_race.84333070572240046062114391096020536909892171034267587351298392577874747836355
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.7900841295317064272455122549880644279997107693270922980104666940897269806801
Short name T382
Test name
Test status
Simulation time 78981557 ps
CPU time 0.77 seconds
Started Nov 22 12:39:34 PM PST 23
Finished Nov 22 12:39:38 PM PST 23
Peak memory 199580 kb
Host smart-e8a3b727-9a5e-4cd1-aae5-6a4e78273e70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7900841295317064272455122549880644279997107693270922980104666940897269806801 -assert nopostpro
c +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.7900841295317064272455122549880644279997107693270922980104666940897269806801
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.12766964743783256123998931598368193725091206008218834320329843600944873284690
Short name T430
Test name
Test status
Simulation time 2162831562 ps
CPU time 8.3 seconds
Started Nov 22 12:39:37 PM PST 23
Finished Nov 22 12:39:49 PM PST 23
Peak memory 216928 kb
Host smart-d525fc4f-2005-4a39-b3cd-17ef19095144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12766964743783256123998931598368193725091206008218834320329843600944873284690 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 5.rstmgr_leaf_rst_cnsty.12766964743783256123998931598368193725091206008218834320329843600944873284690
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.28275291789407911956662332738341445567988655628108654932808169358029556341653
Short name T264
Test name
Test status
Simulation time 243816210 ps
CPU time 1.1 seconds
Started Nov 22 12:39:41 PM PST 23
Finished Nov 22 12:39:46 PM PST 23
Peak memory 216768 kb
Host smart-172834d3-92d5-48a5-9ba1-dc4f54e9da90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28275291789407911956662332738341445567988655628108654932808169358029556341653 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.28275291789407911956662332738341445567988655628108654932808169358029556341653
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.58702234216160003631666145047020050394356764006444465512957512276867837490796
Short name T602
Test name
Test status
Simulation time 230357768 ps
CPU time 0.91 seconds
Started Nov 22 12:39:38 PM PST 23
Finished Nov 22 12:39:43 PM PST 23
Peak memory 199616 kb
Host smart-ac6adada-24a9-4bf0-82ec-d042cd121e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58702234216160003631666145047020050394356764006444465512957512276867837490796 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.rstmgr_por_stretcher.58702234216160003631666145047020050394356764006444465512957512276867837490796
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.20352044829222842297927601307032827532473960246502653371923493024048065413122
Short name T572
Test name
Test status
Simulation time 1729953098 ps
CPU time 6.67 seconds
Started Nov 22 12:39:54 PM PST 23
Finished Nov 22 12:40:02 PM PST 23
Peak memory 200052 kb
Host smart-3fcf0a1e-565f-4b8f-93e1-04b8cdbe40c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20352044829222842297927601307032827532473960246502653371923493024048065413122 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 5.rstmgr_reset.20352044829222842297927601307032827532473960246502653371923493024048065413122
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.113454705611976167909142093495648402079229280841226222480491167141306934250993
Short name T266
Test name
Test status
Simulation time 170065619 ps
CPU time 1.14 seconds
Started Nov 22 12:40:05 PM PST 23
Finished Nov 22 12:40:08 PM PST 23
Peak memory 199720 kb
Host smart-17aa933d-dad5-477e-853e-717965a8faf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113454705611976167909142093495648402079229280841226222480491167141306934250993 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.113454705611976167909142093495648402079229280841226222480491167141306934250993
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.74079388760899206158493173953908236765048914041117415428857455206023303934586
Short name T412
Test name
Test status
Simulation time 223941050 ps
CPU time 1.43 seconds
Started Nov 22 12:39:54 PM PST 23
Finished Nov 22 12:39:57 PM PST 23
Peak memory 200008 kb
Host smart-5d5881ca-11ad-4d63-b856-67259a8cd388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74079388760899206158493173953908236765048914041117415428857455206023303934586 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 5.rstmgr_smoke.74079388760899206158493173953908236765048914041117415428857455206023303934586
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.39326778832046492213039056126556775843286016737556725628656713328679793910783
Short name T440
Test name
Test status
Simulation time 11131278308 ps
CPU time 39.22 seconds
Started Nov 22 12:39:32 PM PST 23
Finished Nov 22 12:40:14 PM PST 23
Peak memory 199952 kb
Host smart-e39363d9-deb0-4b27-91aa-87bfa7fa3e24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39326778832046492213039056126556775843286016737556725628656713328679793910783 -assert nopos
tproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.39326778832046492213039056126556775843286016737556725628656713328679793910783
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.4528992659971202670899493642542613776273517060849942244058307775395038299262
Short name T600
Test name
Test status
Simulation time 473109710 ps
CPU time 2.63 seconds
Started Nov 22 12:39:54 PM PST 23
Finished Nov 22 12:39:58 PM PST 23
Peak memory 199812 kb
Host smart-fbd06822-fccc-40d9-8e3f-36c17129da34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4528992659971202670899493642542613776273517060849942244058307775395038299262 -assert nopostproc +UVM_TESTNAME=rstmgr_bas
e_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 5.rstmgr_sw_rst.4528992659971202670899493642542613776273517060849942244058307775395038299262
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.16432342876176309708828716937036788491934143701024247456244718885988781499714
Short name T523
Test name
Test status
Simulation time 241232855 ps
CPU time 1.48 seconds
Started Nov 22 12:39:53 PM PST 23
Finished Nov 22 12:39:55 PM PST 23
Peak memory 199860 kb
Host smart-217dd82b-9433-4ac3-b582-7df6e31641e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16432342876176309708828716937036788491934143701024247456244718885988781499714 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.rstmgr_sw_rst_reset_race.16432342876176309708828716937036788491934143701024247456244718885988781499714
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.109140721247657807298236305515010091673797778889677076969714097706230485707277
Short name T104
Test name
Test status
Simulation time 78981557 ps
CPU time 0.76 seconds
Started Nov 22 12:39:55 PM PST 23
Finished Nov 22 12:39:57 PM PST 23
Peak memory 199472 kb
Host smart-bc7b4f9a-1673-4643-85b1-dc6b5c4b8044
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109140721247657807298236305515010091673797778889677076969714097706230485707277 -assert nopostp
roc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.109140721247657807298236305515010091673797778889677076969714097706230485707277
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.27892381399616596507009482030834798555063214588466058737781368906016461977877
Short name T32
Test name
Test status
Simulation time 2162831562 ps
CPU time 8.08 seconds
Started Nov 22 12:39:57 PM PST 23
Finished Nov 22 12:40:06 PM PST 23
Peak memory 216980 kb
Host smart-e94c27a5-f6e4-4bd6-b8de-3727bd01421a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27892381399616596507009482030834798555063214588466058737781368906016461977877 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 6.rstmgr_leaf_rst_cnsty.27892381399616596507009482030834798555063214588466058737781368906016461977877
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.56700381063956545557861251347882089187289656521188044174710455198300899576732
Short name T251
Test name
Test status
Simulation time 243816210 ps
CPU time 1.09 seconds
Started Nov 22 12:40:11 PM PST 23
Finished Nov 22 12:40:13 PM PST 23
Peak memory 216772 kb
Host smart-efb49746-2447-4fc2-872b-fc5488488add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56700381063956545557861251347882089187289656521188044174710455198300899576732 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.56700381063956545557861251347882089187289656521188044174710455198300899576732
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.28735228424940282936879555765496875762226584845160602393689626782413474955668
Short name T302
Test name
Test status
Simulation time 230357768 ps
CPU time 0.95 seconds
Started Nov 22 12:39:37 PM PST 23
Finished Nov 22 12:39:43 PM PST 23
Peak memory 199504 kb
Host smart-b96ea734-46f6-4404-b9e2-55b77a5afd18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28735228424940282936879555765496875762226584845160602393689626782413474955668 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.rstmgr_por_stretcher.28735228424940282936879555765496875762226584845160602393689626782413474955668
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.3116414666500700235215717212134773607544632999620334354596894032540905369992
Short name T612
Test name
Test status
Simulation time 1729953098 ps
CPU time 6.88 seconds
Started Nov 22 12:39:55 PM PST 23
Finished Nov 22 12:40:03 PM PST 23
Peak memory 199988 kb
Host smart-b3bb8baf-b8d4-442a-b1fc-64916f2b125d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116414666500700235215717212134773607544632999620334354596894032540905369992 -assert nopostproc +UVM_TESTNAME=rstmgr_bas
e_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rstmgr_reset.3116414666500700235215717212134773607544632999620334354596894032540905369992
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.44555044130077122722878087834409022424900503161999851430544090000586320818796
Short name T233
Test name
Test status
Simulation time 170065619 ps
CPU time 1.27 seconds
Started Nov 22 12:40:03 PM PST 23
Finished Nov 22 12:40:06 PM PST 23
Peak memory 199852 kb
Host smart-004df397-8e53-43be-858f-403a3bd61b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44555044130077122722878087834409022424900503161999851430544090000586320818796 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.44555044130077122722878087834409022424900503161999851430544090000586320818796
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.33549285716795678371314360247212389505425884365657804647936407094413347129097
Short name T288
Test name
Test status
Simulation time 223941050 ps
CPU time 1.52 seconds
Started Nov 22 12:39:37 PM PST 23
Finished Nov 22 12:39:43 PM PST 23
Peak memory 199956 kb
Host smart-02a6a9ba-7895-4f1f-8d86-692a307ff8c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33549285716795678371314360247212389505425884365657804647936407094413347129097 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 6.rstmgr_smoke.33549285716795678371314360247212389505425884365657804647936407094413347129097
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.58287815535377212049891051994768242627113279931000728747706084461001704992185
Short name T530
Test name
Test status
Simulation time 11131278308 ps
CPU time 37.74 seconds
Started Nov 22 12:40:00 PM PST 23
Finished Nov 22 12:40:40 PM PST 23
Peak memory 199940 kb
Host smart-f5519525-a83d-480f-a234-c47372698659
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58287815535377212049891051994768242627113279931000728747706084461001704992185 -assert nopos
tproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.58287815535377212049891051994768242627113279931000728747706084461001704992185
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.24561113628928775016583238765576343698831959516073059416412543689272341937532
Short name T23
Test name
Test status
Simulation time 473109710 ps
CPU time 2.61 seconds
Started Nov 22 12:39:57 PM PST 23
Finished Nov 22 12:40:01 PM PST 23
Peak memory 199640 kb
Host smart-d20b9201-3b1b-4349-8b77-d64946d73def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24561113628928775016583238765576343698831959516073059416412543689272341937532 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 6.rstmgr_sw_rst.24561113628928775016583238765576343698831959516073059416412543689272341937532
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.112202835141403375437090781238197885346009795893827000933447029158007368516196
Short name T231
Test name
Test status
Simulation time 241232855 ps
CPU time 1.43 seconds
Started Nov 22 12:39:54 PM PST 23
Finished Nov 22 12:39:57 PM PST 23
Peak memory 199908 kb
Host smart-4d369bd3-59be-407b-b260-a4a8ef9973c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112202835141403375437090781238197885346009795893827000933447029158007368516196 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.rstmgr_sw_rst_reset_race.112202835141403375437090781238197885346009795893827000933447029158007368516196
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.36719795892569328246207301496620192591163356422579912741220700319088518662586
Short name T495
Test name
Test status
Simulation time 78981557 ps
CPU time 0.77 seconds
Started Nov 22 12:39:58 PM PST 23
Finished Nov 22 12:40:00 PM PST 23
Peak memory 199696 kb
Host smart-b3160a39-a8ee-4e63-b993-94bf2f08f1eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36719795892569328246207301496620192591163356422579912741220700319088518662586 -assert nopostpr
oc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.36719795892569328246207301496620192591163356422579912741220700319088518662586
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.20738601761882565254308652135888548552785070581709645231402231714420649252790
Short name T29
Test name
Test status
Simulation time 2162831562 ps
CPU time 7.86 seconds
Started Nov 22 12:40:04 PM PST 23
Finished Nov 22 12:40:15 PM PST 23
Peak memory 217016 kb
Host smart-a264c4f0-7e1c-4279-9501-cea75184c90c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20738601761882565254308652135888548552785070581709645231402231714420649252790 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 7.rstmgr_leaf_rst_cnsty.20738601761882565254308652135888548552785070581709645231402231714420649252790
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.623872006372502754262450868520408826860052693866063355970748073780814321760
Short name T380
Test name
Test status
Simulation time 243816210 ps
CPU time 1.09 seconds
Started Nov 22 12:39:55 PM PST 23
Finished Nov 22 12:39:57 PM PST 23
Peak memory 216764 kb
Host smart-5d1e1438-67dc-4567-8f33-a86c09c40951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623872006372502754262450868520408826860052693866063355970748073780814321760 -assert nopostproc +UVM_TESTNAME=rstmgr_base
_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.623872006372502754262450868520408826860052693866063355970748073780814321760
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.58620419281605624437167874981073990519494408794437624581639697224567705157353
Short name T396
Test name
Test status
Simulation time 230357768 ps
CPU time 0.95 seconds
Started Nov 22 12:40:39 PM PST 23
Finished Nov 22 12:40:42 PM PST 23
Peak memory 199068 kb
Host smart-7b88de9b-9296-4ab5-9ced-db90662d7f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58620419281605624437167874981073990519494408794437624581639697224567705157353 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.rstmgr_por_stretcher.58620419281605624437167874981073990519494408794437624581639697224567705157353
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.22704096614437110460212219199745171099452375401665773494491713744007492400500
Short name T133
Test name
Test status
Simulation time 1729953098 ps
CPU time 6.49 seconds
Started Nov 22 12:40:04 PM PST 23
Finished Nov 22 12:40:12 PM PST 23
Peak memory 200080 kb
Host smart-144889e5-daa0-4fa6-8aa1-abba20014b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22704096614437110460212219199745171099452375401665773494491713744007492400500 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 7.rstmgr_reset.22704096614437110460212219199745171099452375401665773494491713744007492400500
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.71366429206993207413469056380209457102249698097365205130987117239222096269060
Short name T464
Test name
Test status
Simulation time 170065619 ps
CPU time 1.13 seconds
Started Nov 22 12:39:57 PM PST 23
Finished Nov 22 12:39:59 PM PST 23
Peak memory 199632 kb
Host smart-96d3adb7-461c-4be3-b32e-fb927eb75ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71366429206993207413469056380209457102249698097365205130987117239222096269060 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.71366429206993207413469056380209457102249698097365205130987117239222096269060
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.58631366182869657901010906574941299797582505037378083549931952303391255150412
Short name T390
Test name
Test status
Simulation time 223941050 ps
CPU time 1.37 seconds
Started Nov 22 12:40:04 PM PST 23
Finished Nov 22 12:40:08 PM PST 23
Peak memory 200024 kb
Host smart-d1d49c23-f94a-481b-88e5-226aaa1c6519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58631366182869657901010906574941299797582505037378083549931952303391255150412 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 7.rstmgr_smoke.58631366182869657901010906574941299797582505037378083549931952303391255150412
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.99084506658117552244553929220868808552213878521005345228483103016328260473295
Short name T527
Test name
Test status
Simulation time 11131278308 ps
CPU time 39.33 seconds
Started Nov 22 12:40:03 PM PST 23
Finished Nov 22 12:40:45 PM PST 23
Peak memory 199996 kb
Host smart-bc3f2ceb-b762-460c-a9ec-5e566dd3fea1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99084506658117552244553929220868808552213878521005345228483103016328260473295 -assert nopos
tproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.99084506658117552244553929220868808552213878521005345228483103016328260473295
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.82627243800315264849887808019930276212222314807297939653556022842798239328366
Short name T293
Test name
Test status
Simulation time 473109710 ps
CPU time 2.78 seconds
Started Nov 22 12:40:03 PM PST 23
Finished Nov 22 12:40:08 PM PST 23
Peak memory 199740 kb
Host smart-26f9fa2d-e170-472c-b48f-9daa32066ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82627243800315264849887808019930276212222314807297939653556022842798239328366 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 7.rstmgr_sw_rst.82627243800315264849887808019930276212222314807297939653556022842798239328366
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.49628921332842781875577997886838865061022980336531065057229825883028394894231
Short name T268
Test name
Test status
Simulation time 241232855 ps
CPU time 1.33 seconds
Started Nov 22 12:40:00 PM PST 23
Finished Nov 22 12:40:03 PM PST 23
Peak memory 199828 kb
Host smart-75e9ba6e-ea64-44b2-b933-b4ef56bb378c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49628921332842781875577997886838865061022980336531065057229825883028394894231 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.rstmgr_sw_rst_reset_race.49628921332842781875577997886838865061022980336531065057229825883028394894231
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.85257270639127373876751324717882770140323354544613067777664390281718584082697
Short name T429
Test name
Test status
Simulation time 78981557 ps
CPU time 0.79 seconds
Started Nov 22 12:40:06 PM PST 23
Finished Nov 22 12:40:10 PM PST 23
Peak memory 199720 kb
Host smart-29a5b3d4-6fe6-4931-9001-a66a4aa9221c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85257270639127373876751324717882770140323354544613067777664390281718584082697 -assert nopostpr
oc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.85257270639127373876751324717882770140323354544613067777664390281718584082697
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.57348083141668066425533988418342338402785666389855735190309837436837040226038
Short name T28
Test name
Test status
Simulation time 2162831562 ps
CPU time 8.26 seconds
Started Nov 22 12:39:57 PM PST 23
Finished Nov 22 12:40:06 PM PST 23
Peak memory 216496 kb
Host smart-9a52539c-52c3-4ca0-a779-1fa700196c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57348083141668066425533988418342338402785666389855735190309837436837040226038 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 8.rstmgr_leaf_rst_cnsty.57348083141668066425533988418342338402785666389855735190309837436837040226038
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.106053583607379943513115748955083046043193600449993273752518344800993001889638
Short name T103
Test name
Test status
Simulation time 243816210 ps
CPU time 1.12 seconds
Started Nov 22 12:40:01 PM PST 23
Finished Nov 22 12:40:04 PM PST 23
Peak memory 216844 kb
Host smart-585c1841-2cfa-4580-8867-fc12b18d294e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106053583607379943513115748955083046043193600449993273752518344800993001889638 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.106053583607379943513115748955083046043193600449993273752518344800993001889638
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.98919851269281797492662962084276663849365269301827017577919760378182153945843
Short name T474
Test name
Test status
Simulation time 230357768 ps
CPU time 0.91 seconds
Started Nov 22 12:40:11 PM PST 23
Finished Nov 22 12:40:14 PM PST 23
Peak memory 199688 kb
Host smart-73a799e5-f099-4c1f-900e-2cb88887658d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98919851269281797492662962084276663849365269301827017577919760378182153945843 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.rstmgr_por_stretcher.98919851269281797492662962084276663849365269301827017577919760378182153945843
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.68329320511639559892600136441498744938706022610038373373532291022989915204914
Short name T255
Test name
Test status
Simulation time 1729953098 ps
CPU time 7.05 seconds
Started Nov 22 12:39:55 PM PST 23
Finished Nov 22 12:40:03 PM PST 23
Peak memory 199984 kb
Host smart-c6d3fd11-da4f-4f32-a9ad-7256f24ec572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68329320511639559892600136441498744938706022610038373373532291022989915204914 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 8.rstmgr_reset.68329320511639559892600136441498744938706022610038373373532291022989915204914
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.93489563721404463044118984044492107077897868139837561157764739365248068709808
Short name T535
Test name
Test status
Simulation time 170065619 ps
CPU time 1.14 seconds
Started Nov 22 12:40:05 PM PST 23
Finished Nov 22 12:40:09 PM PST 23
Peak memory 199900 kb
Host smart-d8f51fe9-b17f-46e4-b3a4-674b7bff74e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93489563721404463044118984044492107077897868139837561157764739365248068709808 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.93489563721404463044118984044492107077897868139837561157764739365248068709808
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.99964274652396582207228036010405121411206048412296121444856500238904293907665
Short name T444
Test name
Test status
Simulation time 223941050 ps
CPU time 1.39 seconds
Started Nov 22 12:39:59 PM PST 23
Finished Nov 22 12:40:02 PM PST 23
Peak memory 199900 kb
Host smart-89137b02-6f32-41c3-8b85-e35d2efc18eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99964274652396582207228036010405121411206048412296121444856500238904293907665 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 8.rstmgr_smoke.99964274652396582207228036010405121411206048412296121444856500238904293907665
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.10192040495738683881012511522589038171148583913705441678517808747751589177353
Short name T113
Test name
Test status
Simulation time 11131278308 ps
CPU time 37.77 seconds
Started Nov 22 12:39:50 PM PST 23
Finished Nov 22 12:40:29 PM PST 23
Peak memory 199872 kb
Host smart-da652f4c-8de3-4494-967e-e6dafda72f59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10192040495738683881012511522589038171148583913705441678517808747751589177353 -assert nopos
tproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.10192040495738683881012511522589038171148583913705441678517808747751589177353
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.87569318150528002739305586702980483012681355239396104480449626765052716303727
Short name T469
Test name
Test status
Simulation time 473109710 ps
CPU time 2.63 seconds
Started Nov 22 12:39:59 PM PST 23
Finished Nov 22 12:40:03 PM PST 23
Peak memory 199636 kb
Host smart-ac1a0c66-2a40-4025-a541-acf7bb325744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87569318150528002739305586702980483012681355239396104480449626765052716303727 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 8.rstmgr_sw_rst.87569318150528002739305586702980483012681355239396104480449626765052716303727
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.44711718156482788757255262220910204748853595107265461974940584976314908307254
Short name T308
Test name
Test status
Simulation time 241232855 ps
CPU time 1.37 seconds
Started Nov 22 12:40:05 PM PST 23
Finished Nov 22 12:40:09 PM PST 23
Peak memory 199908 kb
Host smart-ee9e6ae4-87f3-425e-b2f0-1ab6c32a4c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44711718156482788757255262220910204748853595107265461974940584976314908307254 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.rstmgr_sw_rst_reset_race.44711718156482788757255262220910204748853595107265461974940584976314908307254
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.39039312889241545520829121809536524901322953557289681480563853438125075435306
Short name T557
Test name
Test status
Simulation time 78981557 ps
CPU time 0.76 seconds
Started Nov 22 12:40:07 PM PST 23
Finished Nov 22 12:40:10 PM PST 23
Peak memory 199684 kb
Host smart-10c715c5-1ccf-4ff9-b1f3-ec0ff60d67f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39039312889241545520829121809536524901322953557289681480563853438125075435306 -assert nopostpr
oc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.39039312889241545520829121809536524901322953557289681480563853438125075435306
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.71126830077120204621052607278730121214565960338076123369142241774460941463160
Short name T591
Test name
Test status
Simulation time 2162831562 ps
CPU time 8.1 seconds
Started Nov 22 12:40:38 PM PST 23
Finished Nov 22 12:40:49 PM PST 23
Peak memory 215588 kb
Host smart-0ee0ee57-ea9b-4bbf-ba4f-dfc2b0112e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71126830077120204621052607278730121214565960338076123369142241774460941463160 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 9.rstmgr_leaf_rst_cnsty.71126830077120204621052607278730121214565960338076123369142241774460941463160
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.77176941029372037152630290840778140335612401457522186426380607696225675083287
Short name T479
Test name
Test status
Simulation time 243816210 ps
CPU time 1.11 seconds
Started Nov 22 12:39:59 PM PST 23
Finished Nov 22 12:40:01 PM PST 23
Peak memory 216780 kb
Host smart-12df1b58-7f06-433d-a88f-19e84338d701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77176941029372037152630290840778140335612401457522186426380607696225675083287 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.77176941029372037152630290840778140335612401457522186426380607696225675083287
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.74394098680447078809345736442011737814848894156015293508870305494081558782520
Short name T528
Test name
Test status
Simulation time 230357768 ps
CPU time 0.93 seconds
Started Nov 22 12:39:53 PM PST 23
Finished Nov 22 12:39:54 PM PST 23
Peak memory 199700 kb
Host smart-c5886d16-7ac8-44a4-83df-bea6348c0781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74394098680447078809345736442011737814848894156015293508870305494081558782520 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.rstmgr_por_stretcher.74394098680447078809345736442011737814848894156015293508870305494081558782520
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.88707115984653799964080671028662087978559573948091907514186137840867924770906
Short name T611
Test name
Test status
Simulation time 1729953098 ps
CPU time 6.44 seconds
Started Nov 22 12:40:00 PM PST 23
Finished Nov 22 12:40:09 PM PST 23
Peak memory 199944 kb
Host smart-af77c163-305a-4208-9b70-0ecd4a4c2c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88707115984653799964080671028662087978559573948091907514186137840867924770906 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 9.rstmgr_reset.88707115984653799964080671028662087978559573948091907514186137840867924770906
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.71581604622951945834688352909984418043092927985798223428731272264987603316012
Short name T307
Test name
Test status
Simulation time 170065619 ps
CPU time 1.21 seconds
Started Nov 22 12:39:55 PM PST 23
Finished Nov 22 12:39:58 PM PST 23
Peak memory 199888 kb
Host smart-bdd1b262-28b1-4b76-a9f4-06bd419ba3fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71581604622951945834688352909984418043092927985798223428731272264987603316012 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.71581604622951945834688352909984418043092927985798223428731272264987603316012
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.23123443186871016631827999464006228737730385229201651529845542852104882076162
Short name T471
Test name
Test status
Simulation time 223941050 ps
CPU time 1.43 seconds
Started Nov 22 12:39:57 PM PST 23
Finished Nov 22 12:39:59 PM PST 23
Peak memory 199308 kb
Host smart-337e987a-83e0-4f07-8335-b9e4d7ac529a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23123443186871016631827999464006228737730385229201651529845542852104882076162 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 9.rstmgr_smoke.23123443186871016631827999464006228737730385229201651529845542852104882076162
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.33551936911587286999794037128362627548594603616842161503698312672756637516817
Short name T64
Test name
Test status
Simulation time 11131278308 ps
CPU time 38.88 seconds
Started Nov 22 12:39:51 PM PST 23
Finished Nov 22 12:40:31 PM PST 23
Peak memory 199952 kb
Host smart-ccdef63b-f843-43cc-970d-e6bdacbe6db6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33551936911587286999794037128362627548594603616842161503698312672756637516817 -assert nopos
tproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.33551936911587286999794037128362627548594603616842161503698312672756637516817
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.18560490730569809051754882509207342802963068560418199823335480419535379212112
Short name T402
Test name
Test status
Simulation time 473109710 ps
CPU time 2.53 seconds
Started Nov 22 12:39:59 PM PST 23
Finished Nov 22 12:40:03 PM PST 23
Peak memory 199636 kb
Host smart-c6cb8329-049a-4c33-87b5-e5cc8f0dc895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18560490730569809051754882509207342802963068560418199823335480419535379212112 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 9.rstmgr_sw_rst.18560490730569809051754882509207342802963068560418199823335480419535379212112
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.62956803768148656479910738162004123870221809285884881686017827921621254672513
Short name T392
Test name
Test status
Simulation time 241232855 ps
CPU time 1.43 seconds
Started Nov 22 12:39:47 PM PST 23
Finished Nov 22 12:39:51 PM PST 23
Peak memory 199868 kb
Host smart-7cf657b7-3b2f-4a54-a8bb-0c0166d7d373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62956803768148656479910738162004123870221809285884881686017827921621254672513 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 9.rstmgr_sw_rst_reset_race.62956803768148656479910738162004123870221809285884881686017827921621254672513
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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