Summary for Variable enable
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1600 |
1 |
|
|
T10 |
32 |
|
T62 |
32 |
|
T56 |
32 |
auto[1] |
5039 |
1 |
|
|
T1 |
18 |
|
T2 |
45 |
|
T3 |
48 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1600 |
1 |
|
|
T10 |
32 |
|
T62 |
32 |
|
T56 |
32 |
auto[1] |
5039 |
1 |
|
|
T1 |
18 |
|
T2 |
45 |
|
T3 |
48 |
Summary for Variable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1902 |
1 |
|
|
T1 |
6 |
|
T2 |
19 |
|
T3 |
21 |
auto[1] |
4737 |
1 |
|
|
T1 |
12 |
|
T2 |
26 |
|
T3 |
27 |
Summary for Variable rst_n_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1902 |
1 |
|
|
T1 |
6 |
|
T2 |
19 |
|
T3 |
21 |
auto[1] |
4737 |
1 |
|
|
T1 |
12 |
|
T2 |
26 |
|
T3 |
27 |
Summary for Cross sw_rst_cross
Samples crossed: enable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for sw_rst_cross
Bins
enable | rst_n | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
400 |
1 |
|
|
T10 |
8 |
|
T62 |
8 |
|
T56 |
8 |
auto[0] |
auto[1] |
1200 |
1 |
|
|
T10 |
24 |
|
T62 |
24 |
|
T56 |
24 |
auto[1] |
auto[0] |
1502 |
1 |
|
|
T1 |
6 |
|
T2 |
19 |
|
T3 |
21 |
auto[1] |
auto[1] |
3537 |
1 |
|
|
T1 |
12 |
|
T2 |
26 |
|
T3 |
27 |
Summary for Variable enable
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1475 |
1 |
|
|
T10 |
28 |
|
T62 |
28 |
|
T45 |
3 |
auto[1] |
4941 |
1 |
|
|
T1 |
14 |
|
T2 |
45 |
|
T3 |
48 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1475 |
1 |
|
|
T10 |
28 |
|
T62 |
28 |
|
T45 |
3 |
auto[1] |
4941 |
1 |
|
|
T1 |
14 |
|
T2 |
45 |
|
T3 |
48 |
Summary for Variable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1842 |
1 |
|
|
T1 |
2 |
|
T2 |
16 |
|
T3 |
19 |
auto[1] |
4574 |
1 |
|
|
T1 |
12 |
|
T2 |
29 |
|
T3 |
29 |
Summary for Variable rst_n_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1842 |
1 |
|
|
T1 |
2 |
|
T2 |
16 |
|
T3 |
19 |
auto[1] |
4574 |
1 |
|
|
T1 |
12 |
|
T2 |
29 |
|
T3 |
29 |
Summary for Cross sw_rst_cross
Samples crossed: enable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for sw_rst_cross
Bins
enable | rst_n | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
387 |
1 |
|
|
T10 |
7 |
|
T62 |
7 |
|
T45 |
2 |
auto[0] |
auto[1] |
1088 |
1 |
|
|
T10 |
21 |
|
T62 |
21 |
|
T45 |
1 |
auto[1] |
auto[0] |
1455 |
1 |
|
|
T1 |
2 |
|
T2 |
16 |
|
T3 |
19 |
auto[1] |
auto[1] |
3486 |
1 |
|
|
T1 |
12 |
|
T2 |
29 |
|
T3 |
29 |
Summary for Variable enable
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1284 |
1 |
|
|
T9 |
3 |
|
T10 |
24 |
|
T62 |
24 |
auto[1] |
5046 |
1 |
|
|
T1 |
9 |
|
T2 |
45 |
|
T3 |
48 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1284 |
1 |
|
|
T9 |
3 |
|
T10 |
24 |
|
T62 |
24 |
auto[1] |
5046 |
1 |
|
|
T1 |
9 |
|
T2 |
45 |
|
T3 |
48 |
Summary for Variable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1792 |
1 |
|
|
T2 |
14 |
|
T3 |
13 |
|
T6 |
3 |
auto[1] |
4538 |
1 |
|
|
T1 |
9 |
|
T2 |
31 |
|
T3 |
35 |
Summary for Variable rst_n_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1792 |
1 |
|
|
T2 |
14 |
|
T3 |
13 |
|
T6 |
3 |
auto[1] |
4538 |
1 |
|
|
T1 |
9 |
|
T2 |
31 |
|
T3 |
35 |
Summary for Cross sw_rst_cross
Samples crossed: enable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for sw_rst_cross
Bins
enable | rst_n | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
342 |
1 |
|
|
T9 |
2 |
|
T10 |
6 |
|
T62 |
6 |
auto[0] |
auto[1] |
942 |
1 |
|
|
T9 |
1 |
|
T10 |
18 |
|
T62 |
18 |
auto[1] |
auto[0] |
1450 |
1 |
|
|
T2 |
14 |
|
T3 |
13 |
|
T6 |
3 |
auto[1] |
auto[1] |
3596 |
1 |
|
|
T1 |
9 |
|
T2 |
31 |
|
T3 |
35 |
Summary for Variable enable
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1066 |
1 |
|
|
T10 |
20 |
|
T62 |
20 |
|
T56 |
20 |
auto[1] |
5260 |
1 |
|
|
T1 |
9 |
|
T2 |
45 |
|
T3 |
48 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1066 |
1 |
|
|
T10 |
20 |
|
T62 |
20 |
|
T56 |
20 |
auto[1] |
5260 |
1 |
|
|
T1 |
9 |
|
T2 |
45 |
|
T3 |
48 |
Summary for Variable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1766 |
1 |
|
|
T2 |
14 |
|
T3 |
16 |
|
T6 |
3 |
auto[1] |
4560 |
1 |
|
|
T1 |
9 |
|
T2 |
31 |
|
T3 |
32 |
Summary for Variable rst_n_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1766 |
1 |
|
|
T2 |
14 |
|
T3 |
16 |
|
T6 |
3 |
auto[1] |
4560 |
1 |
|
|
T1 |
9 |
|
T2 |
31 |
|
T3 |
32 |
Summary for Cross sw_rst_cross
Samples crossed: enable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for sw_rst_cross
Bins
enable | rst_n | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
279 |
1 |
|
|
T10 |
5 |
|
T62 |
5 |
|
T56 |
5 |
auto[0] |
auto[1] |
787 |
1 |
|
|
T10 |
15 |
|
T62 |
15 |
|
T56 |
15 |
auto[1] |
auto[0] |
1487 |
1 |
|
|
T2 |
14 |
|
T3 |
16 |
|
T6 |
3 |
auto[1] |
auto[1] |
3773 |
1 |
|
|
T1 |
9 |
|
T2 |
31 |
|
T3 |
32 |
Summary for Variable enable
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
860 |
1 |
|
|
T9 |
3 |
|
T10 |
16 |
|
T62 |
16 |
auto[1] |
5466 |
1 |
|
|
T1 |
9 |
|
T2 |
45 |
|
T3 |
48 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
860 |
1 |
|
|
T9 |
3 |
|
T10 |
16 |
|
T62 |
16 |
auto[1] |
5466 |
1 |
|
|
T1 |
9 |
|
T2 |
45 |
|
T3 |
48 |
Summary for Variable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1776 |
1 |
|
|
T2 |
12 |
|
T3 |
17 |
|
T6 |
4 |
auto[1] |
4550 |
1 |
|
|
T1 |
9 |
|
T2 |
33 |
|
T3 |
31 |
Summary for Variable rst_n_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1776 |
1 |
|
|
T2 |
12 |
|
T3 |
17 |
|
T6 |
4 |
auto[1] |
4550 |
1 |
|
|
T1 |
9 |
|
T2 |
33 |
|
T3 |
31 |
Summary for Cross sw_rst_cross
Samples crossed: enable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for sw_rst_cross
Bins
enable | rst_n | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
227 |
1 |
|
|
T9 |
1 |
|
T10 |
4 |
|
T62 |
4 |
auto[0] |
auto[1] |
633 |
1 |
|
|
T9 |
2 |
|
T10 |
12 |
|
T62 |
12 |
auto[1] |
auto[0] |
1549 |
1 |
|
|
T2 |
12 |
|
T3 |
17 |
|
T6 |
4 |
auto[1] |
auto[1] |
3917 |
1 |
|
|
T1 |
9 |
|
T2 |
33 |
|
T3 |
31 |
Summary for Variable enable
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
678 |
1 |
|
|
T10 |
12 |
|
T62 |
12 |
|
T56 |
12 |
auto[1] |
5648 |
1 |
|
|
T1 |
9 |
|
T2 |
45 |
|
T3 |
48 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
678 |
1 |
|
|
T10 |
12 |
|
T62 |
12 |
|
T56 |
12 |
auto[1] |
5648 |
1 |
|
|
T1 |
9 |
|
T2 |
45 |
|
T3 |
48 |
Summary for Variable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1782 |
1 |
|
|
T2 |
17 |
|
T3 |
14 |
|
T6 |
6 |
auto[1] |
4544 |
1 |
|
|
T1 |
9 |
|
T2 |
28 |
|
T3 |
34 |
Summary for Variable rst_n_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1782 |
1 |
|
|
T2 |
17 |
|
T3 |
14 |
|
T6 |
6 |
auto[1] |
4544 |
1 |
|
|
T1 |
9 |
|
T2 |
28 |
|
T3 |
34 |
Summary for Cross sw_rst_cross
Samples crossed: enable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for sw_rst_cross
Bins
enable | rst_n | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
190 |
1 |
|
|
T10 |
3 |
|
T62 |
3 |
|
T56 |
3 |
auto[0] |
auto[1] |
488 |
1 |
|
|
T10 |
9 |
|
T62 |
9 |
|
T56 |
9 |
auto[1] |
auto[0] |
1592 |
1 |
|
|
T2 |
17 |
|
T3 |
14 |
|
T6 |
6 |
auto[1] |
auto[1] |
4056 |
1 |
|
|
T1 |
9 |
|
T2 |
28 |
|
T3 |
34 |
Summary for Variable enable
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
466 |
1 |
|
|
T9 |
3 |
|
T10 |
8 |
|
T62 |
8 |
auto[1] |
5860 |
1 |
|
|
T1 |
9 |
|
T2 |
45 |
|
T3 |
48 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
466 |
1 |
|
|
T9 |
3 |
|
T10 |
8 |
|
T62 |
8 |
auto[1] |
5860 |
1 |
|
|
T1 |
9 |
|
T2 |
45 |
|
T3 |
48 |
Summary for Variable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1796 |
1 |
|
|
T2 |
15 |
|
T3 |
21 |
|
T6 |
5 |
auto[1] |
4530 |
1 |
|
|
T1 |
9 |
|
T2 |
30 |
|
T3 |
27 |
Summary for Variable rst_n_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1796 |
1 |
|
|
T2 |
15 |
|
T3 |
21 |
|
T6 |
5 |
auto[1] |
4530 |
1 |
|
|
T1 |
9 |
|
T2 |
30 |
|
T3 |
27 |
Summary for Cross sw_rst_cross
Samples crossed: enable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for sw_rst_cross
Bins
enable | rst_n | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
133 |
1 |
|
|
T9 |
1 |
|
T10 |
2 |
|
T62 |
2 |
auto[0] |
auto[1] |
333 |
1 |
|
|
T9 |
2 |
|
T10 |
6 |
|
T62 |
6 |
auto[1] |
auto[0] |
1663 |
1 |
|
|
T2 |
15 |
|
T3 |
21 |
|
T6 |
5 |
auto[1] |
auto[1] |
4197 |
1 |
|
|
T1 |
9 |
|
T2 |
30 |
|
T3 |
27 |
Summary for Variable enable
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
296 |
1 |
|
|
T10 |
4 |
|
T62 |
4 |
|
T45 |
3 |
auto[1] |
6030 |
1 |
|
|
T1 |
9 |
|
T2 |
45 |
|
T3 |
48 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
296 |
1 |
|
|
T10 |
4 |
|
T62 |
4 |
|
T45 |
3 |
auto[1] |
6030 |
1 |
|
|
T1 |
9 |
|
T2 |
45 |
|
T3 |
48 |
Summary for Variable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1823 |
1 |
|
|
T2 |
13 |
|
T3 |
16 |
|
T6 |
4 |
auto[1] |
4503 |
1 |
|
|
T1 |
9 |
|
T2 |
32 |
|
T3 |
32 |
Summary for Variable rst_n_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1823 |
1 |
|
|
T2 |
13 |
|
T3 |
16 |
|
T6 |
4 |
auto[1] |
4503 |
1 |
|
|
T1 |
9 |
|
T2 |
32 |
|
T3 |
32 |
Summary for Cross sw_rst_cross
Samples crossed: enable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for sw_rst_cross
Bins
enable | rst_n | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
98 |
1 |
|
|
T10 |
1 |
|
T62 |
1 |
|
T45 |
2 |
auto[0] |
auto[1] |
198 |
1 |
|
|
T10 |
3 |
|
T62 |
3 |
|
T45 |
1 |
auto[1] |
auto[0] |
1725 |
1 |
|
|
T2 |
13 |
|
T3 |
16 |
|
T6 |
4 |
auto[1] |
auto[1] |
4305 |
1 |
|
|
T1 |
9 |
|
T2 |
32 |
|
T3 |
32 |