Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	679205	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

407588

1

T1

66

T2

7133

T3

8144

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	581928	1			T1	89		T2	10740		T3	12234
values[0x0]	251799	1			T1	53		T2	4250		T3	4929
values[0x1]	253066	1			T1	43		T2	4139		T3	4960

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	569745	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

517048

1

T1

84

T2

9142

T3

10403

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3674	1			T2	71		T3	86		T6	11
valid_sources[0x01]	5377	1			T2	86		T3	70		T6	21
valid_sources[0x02]	4769	1			T2	74		T3	80		T6	10
valid_sources[0x03]	3616	1			T2	79		T3	50		T6	15
valid_sources[0x04]	4016	1			T2	76		T3	58		T6	14
valid_sources[0x05]	3470	1			T2	74		T3	44		T6	16
valid_sources[0x06]	3342	1			T2	86		T3	112		T6	13
valid_sources[0x07]	3990	1			T2	68		T3	86		T6	12
valid_sources[0x08]	3774	1			T2	89		T3	65		T6	11
valid_sources[0x09]	4787	1			T2	70		T3	71		T6	11
valid_sources[0x0a]	3710	1			T2	73		T3	100		T6	22
valid_sources[0x0b]	3627	1			T2	94		T3	62		T6	14
valid_sources[0x0c]	7318	1			T2	69		T3	65		T6	10
valid_sources[0x0d]	4508	1			T2	57		T3	57		T6	18
valid_sources[0x0e]	4465	1			T2	80		T3	126		T6	12
valid_sources[0x0f]	3926	1			T2	74		T3	112		T6	9
valid_sources[0x10]	3643	1			T2	87		T3	67		T6	21
valid_sources[0x11]	3672	1			T2	70		T3	55		T6	9
valid_sources[0x12]	3929	1			T2	76		T3	64		T6	9
valid_sources[0x13]	3131	1			T2	75		T3	55		T6	14
valid_sources[0x14]	3778	1			T2	92		T3	110		T6	17
valid_sources[0x15]	4020	1			T2	88		T3	40		T6	7
valid_sources[0x16]	4168	1			T2	74		T3	69		T6	9
valid_sources[0x17]	4855	1			T2	78		T3	90		T6	10
valid_sources[0x18]	4936	1			T2	92		T3	133		T4	8
valid_sources[0x19]	3644	1			T2	76		T3	48		T6	19
valid_sources[0x1a]	3761	1			T2	88		T3	136		T6	12
valid_sources[0x1b]	3525	1			T2	104		T3	138		T6	7
valid_sources[0x1c]	3553	1			T2	73		T3	168		T6	17
valid_sources[0x1d]	3711	1			T2	84		T3	67		T6	11
valid_sources[0x1e]	4709	1			T2	89		T3	69		T6	21
valid_sources[0x1f]	4999	1			T2	80		T3	47		T6	16
valid_sources[0x20]	5771	1			T2	78		T3	129		T6	8
valid_sources[0x21]	3720	1			T2	67		T3	46		T6	18
valid_sources[0x22]	3526	1			T2	72		T3	80		T6	19
valid_sources[0x23]	6813	1			T2	67		T3	96		T6	11
valid_sources[0x24]	4180	1			T2	94		T3	105		T6	13
valid_sources[0x25]	4203	1			T2	63		T3	92		T6	11
valid_sources[0x26]	4633	1			T2	75		T3	99		T6	8
valid_sources[0x27]	3867	1			T2	76		T3	103		T6	29
valid_sources[0x28]	3833	1			T2	75		T3	152		T6	9
valid_sources[0x29]	4255	1			T2	59		T3	89		T6	14
valid_sources[0x2a]	3408	1			T2	85		T3	97		T6	5
valid_sources[0x2b]	4657	1			T2	74		T3	76		T6	12
valid_sources[0x2c]	4102	1			T2	84		T3	82		T6	11
valid_sources[0x2d]	3409	1			T2	84		T3	93		T6	12
valid_sources[0x2e]	3563	1			T2	75		T3	117		T6	26
valid_sources[0x2f]	4030	1			T2	67		T3	82		T6	9
valid_sources[0x30]	4397	1			T2	69		T3	157		T6	28
valid_sources[0x31]	7006	1			T2	86		T3	81		T6	17
valid_sources[0x32]	4219	1			T2	72		T3	34		T6	19
valid_sources[0x33]	7038	1			T2	69		T3	81		T4	3
valid_sources[0x34]	4241	1			T2	75		T3	100		T6	10
valid_sources[0x35]	4181	1			T2	64		T3	118		T6	23
valid_sources[0x36]	4296	1			T2	54		T3	167		T6	16
valid_sources[0x37]	4160	1			T2	67		T3	175		T6	10
valid_sources[0x38]	5989	1			T2	85		T3	81		T6	4
valid_sources[0x39]	4944	1			T2	90		T3	117		T6	11
valid_sources[0x3a]	4449	1			T2	72		T3	38		T6	16
valid_sources[0x3b]	4114	1			T2	58		T3	51		T6	11
valid_sources[0x3c]	4477	1			T2	70		T3	44		T6	16
valid_sources[0x3d]	4232	1			T2	81		T3	72		T6	9
valid_sources[0x3e]	4663	1			T2	78		T3	116		T6	21
valid_sources[0x3f]	3987	1			T2	98		T3	98		T6	4
valid_sources[0x40]	4052	1			T2	93		T3	159		T6	10
valid_sources[0x41]	3982	1			T2	72		T3	89		T6	14
valid_sources[0x42]	5082	1			T2	83		T3	129		T6	16
valid_sources[0x43]	4369	1			T2	74		T3	83		T6	22
valid_sources[0x44]	5225	1			T2	77		T3	104		T6	15
valid_sources[0x45]	4196	1			T2	74		T3	54		T6	14
valid_sources[0x46]	5317	1			T2	89		T3	57		T6	25
valid_sources[0x47]	4409	1			T2	96		T3	161		T6	10
valid_sources[0x48]	3599	1			T2	78		T3	47		T6	23
valid_sources[0x49]	5690	1			T2	59		T3	98		T6	10
valid_sources[0x4a]	5289	1			T2	75		T3	97		T6	16
valid_sources[0x4b]	4935	1			T2	76		T3	74		T6	20
valid_sources[0x4c]	4535	1			T2	89		T3	96		T4	17
valid_sources[0x4d]	4733	1			T2	70		T3	125		T6	14
valid_sources[0x4e]	4207	1			T2	71		T3	73		T6	15
valid_sources[0x4f]	3464	1			T2	60		T3	40		T6	7
valid_sources[0x50]	5028	1			T2	50		T3	85		T6	20
valid_sources[0x51]	4967	1			T2	74		T3	60		T6	16
valid_sources[0x52]	5961	1			T2	73		T3	61		T6	10
valid_sources[0x53]	4551	1			T2	89		T3	103		T6	9
valid_sources[0x54]	3564	1			T2	75		T3	79		T6	12
valid_sources[0x55]	3831	1			T2	78		T3	216		T6	16
valid_sources[0x56]	4130	1			T2	79		T3	79		T6	26
valid_sources[0x57]	4450	1			T2	84		T3	58		T6	20
valid_sources[0x58]	3417	1			T2	74		T3	139		T6	17
valid_sources[0x59]	3511	1			T2	78		T3	88		T6	19
valid_sources[0x5a]	4299	1			T2	66		T3	112		T6	16
valid_sources[0x5b]	4410	1			T2	55		T3	13		T6	20
valid_sources[0x5c]	7563	1			T2	73		T3	65		T6	13
valid_sources[0x5d]	4458	1			T2	73		T3	76		T6	14
valid_sources[0x5e]	6820	1			T2	68		T3	104		T6	23
valid_sources[0x5f]	4421	1			T2	75		T3	50		T6	6
valid_sources[0x60]	4658	1			T2	79		T3	42		T6	6
valid_sources[0x61]	4287	1			T2	101		T3	78		T6	9
valid_sources[0x62]	3760	1			T2	84		T3	116		T6	19
valid_sources[0x63]	3375	1			T2	92		T3	65		T6	19
valid_sources[0x64]	4372	1			T2	66		T3	171		T6	16
valid_sources[0x65]	4347	1			T2	69		T3	72		T6	12
valid_sources[0x66]	3837	1			T2	78		T3	82		T6	11
valid_sources[0x67]	3834	1			T2	87		T3	98		T6	11
valid_sources[0x68]	4541	1			T2	76		T3	57		T6	7
valid_sources[0x69]	3802	1			T2	80		T3	77		T6	14
valid_sources[0x6a]	3907	1			T2	68		T3	89		T6	12
valid_sources[0x6b]	3846	1			T2	64		T3	105		T6	12
valid_sources[0x6c]	3881	1			T2	67		T3	50		T6	8
valid_sources[0x6d]	4021	1			T2	73		T3	91		T6	11
valid_sources[0x6e]	3689	1			T2	76		T3	134		T6	14
valid_sources[0x6f]	3684	1			T2	66		T3	88		T6	11
valid_sources[0x70]	3982	1			T2	61		T3	44		T6	15
valid_sources[0x71]	4202	1			T2	65		T3	65		T4	2
valid_sources[0x72]	4951	1			T2	86		T3	132		T6	22
valid_sources[0x73]	5002	1			T2	82		T3	160		T6	33
valid_sources[0x74]	4800	1			T2	70		T3	65		T6	12
valid_sources[0x75]	4738	1			T2	87		T3	120		T6	14
valid_sources[0x76]	3427	1			T2	77		T3	50		T6	16
valid_sources[0x77]	5097	1			T2	79		T3	94		T6	14
valid_sources[0x78]	4923	1			T2	80		T3	120		T6	19
valid_sources[0x79]	7302	1			T2	74		T3	94		T6	12
valid_sources[0x7a]	3610	1			T2	84		T3	45		T6	20
valid_sources[0x7b]	3927	1			T2	76		T3	56		T4	14
valid_sources[0x7c]	3767	1			T2	65		T3	140		T6	17
valid_sources[0x7d]	4153	1			T2	78		T3	103		T6	12
valid_sources[0x7e]	4748	1			T2	70		T3	66		T6	13
valid_sources[0x7f]	3750	1			T2	68		T3	58		T6	8
valid_sources[0x80]	3891	1			T2	76		T3	41		T6	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

272716

1

T1

46

T2

5016

T3

5654

values[0x0]

all_enables

biggest_size

87864

1

T1

14

T2

1445

T3

1663

values[0x1]

all_enables

biggest_size

47008

1

T1

6

T2

672

T3

827