SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.55 | 100.00 | 98.21 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_por |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_por_io |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_por_io_div2 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_por_io_div4 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_por_usb |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_lc |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_d0_lc |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_lc_shadowed |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_d0_lc_shadowed |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_lc_aon |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_lc_io |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_d0_lc_io |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_lc_io_div2 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_d0_lc_io_div2 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_daon_lc_io_div4 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_d0_lc_io_div4 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_daon_lc_io_div4_shadowed |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_d0_lc_io_div4_shadowed |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_lc_usb |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_d0_lc_usb |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_d0_sys |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_sys_io_div4 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_spi_device |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_spi_host0 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_spi_host1 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_usb |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | u_d0_usb_aon |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_i2c0 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_i2c1 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_i2c2 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.55 | 100.00 | 98.21 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.55 | 100.00 | 98.21 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 16665 | 16665 | 0 | 0 |
OutputsKnown_A | 390737195 | 231928609 | 0 | 0 |
gen_no_flops.OutputDelay_A | 390737195 | 231928609 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 16665 | 16665 | 0 | 0 |
T1 | 33 | 33 | 0 | 0 |
T2 | 33 | 33 | 0 | 0 |
T3 | 33 | 33 | 0 | 0 |
T4 | 33 | 33 | 0 | 0 |
T5 | 33 | 33 | 0 | 0 |
T6 | 33 | 33 | 0 | 0 |
T7 | 33 | 33 | 0 | 0 |
T8 | 33 | 33 | 0 | 0 |
T9 | 33 | 33 | 0 | 0 |
T10 | 33 | 33 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 390737195 | 231928609 | 0 | 0 |
T1 | 66787 | 41658 | 0 | 0 |
T2 | 7110184 | 5029611 | 0 | 0 |
T3 | 4451918 | 2190872 | 0 | 0 |
T4 | 55594 | 33128 | 0 | 0 |
T5 | 175245 | 17612 | 0 | 0 |
T6 | 1721721 | 1349562 | 0 | 0 |
T7 | 58642 | 38761 | 0 | 0 |
T8 | 121166 | 94465 | 0 | 0 |
T9 | 149088 | 115421 | 0 | 0 |
T10 | 109313 | 87832 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 390737195 | 231928609 | 0 | 0 |
T1 | 66787 | 41658 | 0 | 0 |
T2 | 7110184 | 5029611 | 0 | 0 |
T3 | 4451918 | 2190872 | 0 | 0 |
T4 | 55594 | 33128 | 0 | 0 |
T5 | 175245 | 17612 | 0 | 0 |
T6 | 1721721 | 1349562 | 0 | 0 |
T7 | 58642 | 38761 | 0 | 0 |
T8 | 121166 | 94465 | 0 | 0 |
T9 | 149088 | 115421 | 0 | 0 |
T10 | 109313 | 87832 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 13426987 | 8216769 | 0 | 0 |
gen_no_flops.OutputDelay_A | 13426987 | 8216769 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 13426987 | 8216769 | 0 | 0 |
T1 | 2595 | 1946 | 0 | 0 |
T2 | 245768 | 173707 | 0 | 0 |
T3 | 170382 | 93720 | 0 | 0 |
T4 | 2026 | 1384 | 0 | 0 |
T5 | 5837 | 684 | 0 | 0 |
T6 | 58137 | 45690 | 0 | 0 |
T7 | 1842 | 1193 | 0 | 0 |
T8 | 4654 | 4001 | 0 | 0 |
T9 | 4608 | 3645 | 0 | 0 |
T10 | 3329 | 2680 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 13426987 | 8216769 | 0 | 0 |
T1 | 2595 | 1946 | 0 | 0 |
T2 | 245768 | 173707 | 0 | 0 |
T3 | 170382 | 93720 | 0 | 0 |
T4 | 2026 | 1384 | 0 | 0 |
T5 | 5837 | 684 | 0 | 0 |
T6 | 58137 | 45690 | 0 | 0 |
T7 | 1842 | 1193 | 0 | 0 |
T8 | 4654 | 4001 | 0 | 0 |
T9 | 4608 | 3645 | 0 | 0 |
T10 | 3329 | 2680 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 11790944 | 6990995 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11790944 | 6990995 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11790944 | 6990995 | 0 | 0 |
T1 | 2006 | 1241 | 0 | 0 |
T2 | 214513 | 151747 | 0 | 0 |
T3 | 133798 | 65536 | 0 | 0 |
T4 | 1674 | 992 | 0 | 0 |
T5 | 5294 | 529 | 0 | 0 |
T6 | 51987 | 40746 | 0 | 0 |
T7 | 1775 | 1174 | 0 | 0 |
T8 | 3641 | 2827 | 0 | 0 |
T9 | 4515 | 3493 | 0 | 0 |
T10 | 3312 | 2661 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11790944 | 6990995 | 0 | 0 |
T1 | 2006 | 1241 | 0 | 0 |
T2 | 214513 | 151747 | 0 | 0 |
T3 | 133798 | 65536 | 0 | 0 |
T4 | 1674 | 992 | 0 | 0 |
T5 | 5294 | 529 | 0 | 0 |
T6 | 51987 | 40746 | 0 | 0 |
T7 | 1775 | 1174 | 0 | 0 |
T8 | 3641 | 2827 | 0 | 0 |
T9 | 4515 | 3493 | 0 | 0 |
T10 | 3312 | 2661 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 11790944 | 6990995 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11790944 | 6990995 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11790944 | 6990995 | 0 | 0 |
T1 | 2006 | 1241 | 0 | 0 |
T2 | 214513 | 151747 | 0 | 0 |
T3 | 133798 | 65536 | 0 | 0 |
T4 | 1674 | 992 | 0 | 0 |
T5 | 5294 | 529 | 0 | 0 |
T6 | 51987 | 40746 | 0 | 0 |
T7 | 1775 | 1174 | 0 | 0 |
T8 | 3641 | 2827 | 0 | 0 |
T9 | 4515 | 3493 | 0 | 0 |
T10 | 3312 | 2661 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11790944 | 6990995 | 0 | 0 |
T1 | 2006 | 1241 | 0 | 0 |
T2 | 214513 | 151747 | 0 | 0 |
T3 | 133798 | 65536 | 0 | 0 |
T4 | 1674 | 992 | 0 | 0 |
T5 | 5294 | 529 | 0 | 0 |
T6 | 51987 | 40746 | 0 | 0 |
T7 | 1775 | 1174 | 0 | 0 |
T8 | 3641 | 2827 | 0 | 0 |
T9 | 4515 | 3493 | 0 | 0 |
T10 | 3312 | 2661 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 11790944 | 6990995 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11790944 | 6990995 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11790944 | 6990995 | 0 | 0 |
T1 | 2006 | 1241 | 0 | 0 |
T2 | 214513 | 151747 | 0 | 0 |
T3 | 133798 | 65536 | 0 | 0 |
T4 | 1674 | 992 | 0 | 0 |
T5 | 5294 | 529 | 0 | 0 |
T6 | 51987 | 40746 | 0 | 0 |
T7 | 1775 | 1174 | 0 | 0 |
T8 | 3641 | 2827 | 0 | 0 |
T9 | 4515 | 3493 | 0 | 0 |
T10 | 3312 | 2661 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11790944 | 6990995 | 0 | 0 |
T1 | 2006 | 1241 | 0 | 0 |
T2 | 214513 | 151747 | 0 | 0 |
T3 | 133798 | 65536 | 0 | 0 |
T4 | 1674 | 992 | 0 | 0 |
T5 | 5294 | 529 | 0 | 0 |
T6 | 51987 | 40746 | 0 | 0 |
T7 | 1775 | 1174 | 0 | 0 |
T8 | 3641 | 2827 | 0 | 0 |
T9 | 4515 | 3493 | 0 | 0 |
T10 | 3312 | 2661 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 11790944 | 6990995 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11790944 | 6990995 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11790944 | 6990995 | 0 | 0 |
T1 | 2006 | 1241 | 0 | 0 |
T2 | 214513 | 151747 | 0 | 0 |
T3 | 133798 | 65536 | 0 | 0 |
T4 | 1674 | 992 | 0 | 0 |
T5 | 5294 | 529 | 0 | 0 |
T6 | 51987 | 40746 | 0 | 0 |
T7 | 1775 | 1174 | 0 | 0 |
T8 | 3641 | 2827 | 0 | 0 |
T9 | 4515 | 3493 | 0 | 0 |
T10 | 3312 | 2661 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11790944 | 6990995 | 0 | 0 |
T1 | 2006 | 1241 | 0 | 0 |
T2 | 214513 | 151747 | 0 | 0 |
T3 | 133798 | 65536 | 0 | 0 |
T4 | 1674 | 992 | 0 | 0 |
T5 | 5294 | 529 | 0 | 0 |
T6 | 51987 | 40746 | 0 | 0 |
T7 | 1775 | 1174 | 0 | 0 |
T8 | 3641 | 2827 | 0 | 0 |
T9 | 4515 | 3493 | 0 | 0 |
T10 | 3312 | 2661 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 11790944 | 6990995 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11790944 | 6990995 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11790944 | 6990995 | 0 | 0 |
T1 | 2006 | 1241 | 0 | 0 |
T2 | 214513 | 151747 | 0 | 0 |
T3 | 133798 | 65536 | 0 | 0 |
T4 | 1674 | 992 | 0 | 0 |
T5 | 5294 | 529 | 0 | 0 |
T6 | 51987 | 40746 | 0 | 0 |
T7 | 1775 | 1174 | 0 | 0 |
T8 | 3641 | 2827 | 0 | 0 |
T9 | 4515 | 3493 | 0 | 0 |
T10 | 3312 | 2661 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11790944 | 6990995 | 0 | 0 |
T1 | 2006 | 1241 | 0 | 0 |
T2 | 214513 | 151747 | 0 | 0 |
T3 | 133798 | 65536 | 0 | 0 |
T4 | 1674 | 992 | 0 | 0 |
T5 | 5294 | 529 | 0 | 0 |
T6 | 51987 | 40746 | 0 | 0 |
T7 | 1775 | 1174 | 0 | 0 |
T8 | 3641 | 2827 | 0 | 0 |
T9 | 4515 | 3493 | 0 | 0 |
T10 | 3312 | 2661 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 11790944 | 6990995 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11790944 | 6990995 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11790944 | 6990995 | 0 | 0 |
T1 | 2006 | 1241 | 0 | 0 |
T2 | 214513 | 151747 | 0 | 0 |
T3 | 133798 | 65536 | 0 | 0 |
T4 | 1674 | 992 | 0 | 0 |
T5 | 5294 | 529 | 0 | 0 |
T6 | 51987 | 40746 | 0 | 0 |
T7 | 1775 | 1174 | 0 | 0 |
T8 | 3641 | 2827 | 0 | 0 |
T9 | 4515 | 3493 | 0 | 0 |
T10 | 3312 | 2661 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11790944 | 6990995 | 0 | 0 |
T1 | 2006 | 1241 | 0 | 0 |
T2 | 214513 | 151747 | 0 | 0 |
T3 | 133798 | 65536 | 0 | 0 |
T4 | 1674 | 992 | 0 | 0 |
T5 | 5294 | 529 | 0 | 0 |
T6 | 51987 | 40746 | 0 | 0 |
T7 | 1775 | 1174 | 0 | 0 |
T8 | 3641 | 2827 | 0 | 0 |
T9 | 4515 | 3493 | 0 | 0 |
T10 | 3312 | 2661 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 11790944 | 6990995 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11790944 | 6990995 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11790944 | 6990995 | 0 | 0 |
T1 | 2006 | 1241 | 0 | 0 |
T2 | 214513 | 151747 | 0 | 0 |
T3 | 133798 | 65536 | 0 | 0 |
T4 | 1674 | 992 | 0 | 0 |
T5 | 5294 | 529 | 0 | 0 |
T6 | 51987 | 40746 | 0 | 0 |
T7 | 1775 | 1174 | 0 | 0 |
T8 | 3641 | 2827 | 0 | 0 |
T9 | 4515 | 3493 | 0 | 0 |
T10 | 3312 | 2661 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11790944 | 6990995 | 0 | 0 |
T1 | 2006 | 1241 | 0 | 0 |
T2 | 214513 | 151747 | 0 | 0 |
T3 | 133798 | 65536 | 0 | 0 |
T4 | 1674 | 992 | 0 | 0 |
T5 | 5294 | 529 | 0 | 0 |
T6 | 51987 | 40746 | 0 | 0 |
T7 | 1775 | 1174 | 0 | 0 |
T8 | 3641 | 2827 | 0 | 0 |
T9 | 4515 | 3493 | 0 | 0 |
T10 | 3312 | 2661 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 11790944 | 6990995 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11790944 | 6990995 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11790944 | 6990995 | 0 | 0 |
T1 | 2006 | 1241 | 0 | 0 |
T2 | 214513 | 151747 | 0 | 0 |
T3 | 133798 | 65536 | 0 | 0 |
T4 | 1674 | 992 | 0 | 0 |
T5 | 5294 | 529 | 0 | 0 |
T6 | 51987 | 40746 | 0 | 0 |
T7 | 1775 | 1174 | 0 | 0 |
T8 | 3641 | 2827 | 0 | 0 |
T9 | 4515 | 3493 | 0 | 0 |
T10 | 3312 | 2661 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11790944 | 6990995 | 0 | 0 |
T1 | 2006 | 1241 | 0 | 0 |
T2 | 214513 | 151747 | 0 | 0 |
T3 | 133798 | 65536 | 0 | 0 |
T4 | 1674 | 992 | 0 | 0 |
T5 | 5294 | 529 | 0 | 0 |
T6 | 51987 | 40746 | 0 | 0 |
T7 | 1775 | 1174 | 0 | 0 |
T8 | 3641 | 2827 | 0 | 0 |
T9 | 4515 | 3493 | 0 | 0 |
T10 | 3312 | 2661 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 11790944 | 6990995 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11790944 | 6990995 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11790944 | 6990995 | 0 | 0 |
T1 | 2006 | 1241 | 0 | 0 |
T2 | 214513 | 151747 | 0 | 0 |
T3 | 133798 | 65536 | 0 | 0 |
T4 | 1674 | 992 | 0 | 0 |
T5 | 5294 | 529 | 0 | 0 |
T6 | 51987 | 40746 | 0 | 0 |
T7 | 1775 | 1174 | 0 | 0 |
T8 | 3641 | 2827 | 0 | 0 |
T9 | 4515 | 3493 | 0 | 0 |
T10 | 3312 | 2661 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11790944 | 6990995 | 0 | 0 |
T1 | 2006 | 1241 | 0 | 0 |
T2 | 214513 | 151747 | 0 | 0 |
T3 | 133798 | 65536 | 0 | 0 |
T4 | 1674 | 992 | 0 | 0 |
T5 | 5294 | 529 | 0 | 0 |
T6 | 51987 | 40746 | 0 | 0 |
T7 | 1775 | 1174 | 0 | 0 |
T8 | 3641 | 2827 | 0 | 0 |
T9 | 4515 | 3493 | 0 | 0 |
T10 | 3312 | 2661 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 11790944 | 6990995 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11790944 | 6990995 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11790944 | 6990995 | 0 | 0 |
T1 | 2006 | 1241 | 0 | 0 |
T2 | 214513 | 151747 | 0 | 0 |
T3 | 133798 | 65536 | 0 | 0 |
T4 | 1674 | 992 | 0 | 0 |
T5 | 5294 | 529 | 0 | 0 |
T6 | 51987 | 40746 | 0 | 0 |
T7 | 1775 | 1174 | 0 | 0 |
T8 | 3641 | 2827 | 0 | 0 |
T9 | 4515 | 3493 | 0 | 0 |
T10 | 3312 | 2661 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11790944 | 6990995 | 0 | 0 |
T1 | 2006 | 1241 | 0 | 0 |
T2 | 214513 | 151747 | 0 | 0 |
T3 | 133798 | 65536 | 0 | 0 |
T4 | 1674 | 992 | 0 | 0 |
T5 | 5294 | 529 | 0 | 0 |
T6 | 51987 | 40746 | 0 | 0 |
T7 | 1775 | 1174 | 0 | 0 |
T8 | 3641 | 2827 | 0 | 0 |
T9 | 4515 | 3493 | 0 | 0 |
T10 | 3312 | 2661 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 11790944 | 6990995 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11790944 | 6990995 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11790944 | 6990995 | 0 | 0 |
T1 | 2006 | 1241 | 0 | 0 |
T2 | 214513 | 151747 | 0 | 0 |
T3 | 133798 | 65536 | 0 | 0 |
T4 | 1674 | 992 | 0 | 0 |
T5 | 5294 | 529 | 0 | 0 |
T6 | 51987 | 40746 | 0 | 0 |
T7 | 1775 | 1174 | 0 | 0 |
T8 | 3641 | 2827 | 0 | 0 |
T9 | 4515 | 3493 | 0 | 0 |
T10 | 3312 | 2661 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11790944 | 6990995 | 0 | 0 |
T1 | 2006 | 1241 | 0 | 0 |
T2 | 214513 | 151747 | 0 | 0 |
T3 | 133798 | 65536 | 0 | 0 |
T4 | 1674 | 992 | 0 | 0 |
T5 | 5294 | 529 | 0 | 0 |
T6 | 51987 | 40746 | 0 | 0 |
T7 | 1775 | 1174 | 0 | 0 |
T8 | 3641 | 2827 | 0 | 0 |
T9 | 4515 | 3493 | 0 | 0 |
T10 | 3312 | 2661 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 11790944 | 6990995 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11790944 | 6990995 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11790944 | 6990995 | 0 | 0 |
T1 | 2006 | 1241 | 0 | 0 |
T2 | 214513 | 151747 | 0 | 0 |
T3 | 133798 | 65536 | 0 | 0 |
T4 | 1674 | 992 | 0 | 0 |
T5 | 5294 | 529 | 0 | 0 |
T6 | 51987 | 40746 | 0 | 0 |
T7 | 1775 | 1174 | 0 | 0 |
T8 | 3641 | 2827 | 0 | 0 |
T9 | 4515 | 3493 | 0 | 0 |
T10 | 3312 | 2661 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11790944 | 6990995 | 0 | 0 |
T1 | 2006 | 1241 | 0 | 0 |
T2 | 214513 | 151747 | 0 | 0 |
T3 | 133798 | 65536 | 0 | 0 |
T4 | 1674 | 992 | 0 | 0 |
T5 | 5294 | 529 | 0 | 0 |
T6 | 51987 | 40746 | 0 | 0 |
T7 | 1775 | 1174 | 0 | 0 |
T8 | 3641 | 2827 | 0 | 0 |
T9 | 4515 | 3493 | 0 | 0 |
T10 | 3312 | 2661 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 11790944 | 6990995 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11790944 | 6990995 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11790944 | 6990995 | 0 | 0 |
T1 | 2006 | 1241 | 0 | 0 |
T2 | 214513 | 151747 | 0 | 0 |
T3 | 133798 | 65536 | 0 | 0 |
T4 | 1674 | 992 | 0 | 0 |
T5 | 5294 | 529 | 0 | 0 |
T6 | 51987 | 40746 | 0 | 0 |
T7 | 1775 | 1174 | 0 | 0 |
T8 | 3641 | 2827 | 0 | 0 |
T9 | 4515 | 3493 | 0 | 0 |
T10 | 3312 | 2661 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11790944 | 6990995 | 0 | 0 |
T1 | 2006 | 1241 | 0 | 0 |
T2 | 214513 | 151747 | 0 | 0 |
T3 | 133798 | 65536 | 0 | 0 |
T4 | 1674 | 992 | 0 | 0 |
T5 | 5294 | 529 | 0 | 0 |
T6 | 51987 | 40746 | 0 | 0 |
T7 | 1775 | 1174 | 0 | 0 |
T8 | 3641 | 2827 | 0 | 0 |
T9 | 4515 | 3493 | 0 | 0 |
T10 | 3312 | 2661 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 11790944 | 6990995 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11790944 | 6990995 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11790944 | 6990995 | 0 | 0 |
T1 | 2006 | 1241 | 0 | 0 |
T2 | 214513 | 151747 | 0 | 0 |
T3 | 133798 | 65536 | 0 | 0 |
T4 | 1674 | 992 | 0 | 0 |
T5 | 5294 | 529 | 0 | 0 |
T6 | 51987 | 40746 | 0 | 0 |
T7 | 1775 | 1174 | 0 | 0 |
T8 | 3641 | 2827 | 0 | 0 |
T9 | 4515 | 3493 | 0 | 0 |
T10 | 3312 | 2661 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11790944 | 6990995 | 0 | 0 |
T1 | 2006 | 1241 | 0 | 0 |
T2 | 214513 | 151747 | 0 | 0 |
T3 | 133798 | 65536 | 0 | 0 |
T4 | 1674 | 992 | 0 | 0 |
T5 | 5294 | 529 | 0 | 0 |
T6 | 51987 | 40746 | 0 | 0 |
T7 | 1775 | 1174 | 0 | 0 |
T8 | 3641 | 2827 | 0 | 0 |
T9 | 4515 | 3493 | 0 | 0 |
T10 | 3312 | 2661 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 11790944 | 6990995 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11790944 | 6990995 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11790944 | 6990995 | 0 | 0 |
T1 | 2006 | 1241 | 0 | 0 |
T2 | 214513 | 151747 | 0 | 0 |
T3 | 133798 | 65536 | 0 | 0 |
T4 | 1674 | 992 | 0 | 0 |
T5 | 5294 | 529 | 0 | 0 |
T6 | 51987 | 40746 | 0 | 0 |
T7 | 1775 | 1174 | 0 | 0 |
T8 | 3641 | 2827 | 0 | 0 |
T9 | 4515 | 3493 | 0 | 0 |
T10 | 3312 | 2661 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11790944 | 6990995 | 0 | 0 |
T1 | 2006 | 1241 | 0 | 0 |
T2 | 214513 | 151747 | 0 | 0 |
T3 | 133798 | 65536 | 0 | 0 |
T4 | 1674 | 992 | 0 | 0 |
T5 | 5294 | 529 | 0 | 0 |
T6 | 51987 | 40746 | 0 | 0 |
T7 | 1775 | 1174 | 0 | 0 |
T8 | 3641 | 2827 | 0 | 0 |
T9 | 4515 | 3493 | 0 | 0 |
T10 | 3312 | 2661 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 11790944 | 6990995 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11790944 | 6990995 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11790944 | 6990995 | 0 | 0 |
T1 | 2006 | 1241 | 0 | 0 |
T2 | 214513 | 151747 | 0 | 0 |
T3 | 133798 | 65536 | 0 | 0 |
T4 | 1674 | 992 | 0 | 0 |
T5 | 5294 | 529 | 0 | 0 |
T6 | 51987 | 40746 | 0 | 0 |
T7 | 1775 | 1174 | 0 | 0 |
T8 | 3641 | 2827 | 0 | 0 |
T9 | 4515 | 3493 | 0 | 0 |
T10 | 3312 | 2661 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11790944 | 6990995 | 0 | 0 |
T1 | 2006 | 1241 | 0 | 0 |
T2 | 214513 | 151747 | 0 | 0 |
T3 | 133798 | 65536 | 0 | 0 |
T4 | 1674 | 992 | 0 | 0 |
T5 | 5294 | 529 | 0 | 0 |
T6 | 51987 | 40746 | 0 | 0 |
T7 | 1775 | 1174 | 0 | 0 |
T8 | 3641 | 2827 | 0 | 0 |
T9 | 4515 | 3493 | 0 | 0 |
T10 | 3312 | 2661 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 11790944 | 6990995 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11790944 | 6990995 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11790944 | 6990995 | 0 | 0 |
T1 | 2006 | 1241 | 0 | 0 |
T2 | 214513 | 151747 | 0 | 0 |
T3 | 133798 | 65536 | 0 | 0 |
T4 | 1674 | 992 | 0 | 0 |
T5 | 5294 | 529 | 0 | 0 |
T6 | 51987 | 40746 | 0 | 0 |
T7 | 1775 | 1174 | 0 | 0 |
T8 | 3641 | 2827 | 0 | 0 |
T9 | 4515 | 3493 | 0 | 0 |
T10 | 3312 | 2661 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11790944 | 6990995 | 0 | 0 |
T1 | 2006 | 1241 | 0 | 0 |
T2 | 214513 | 151747 | 0 | 0 |
T3 | 133798 | 65536 | 0 | 0 |
T4 | 1674 | 992 | 0 | 0 |
T5 | 5294 | 529 | 0 | 0 |
T6 | 51987 | 40746 | 0 | 0 |
T7 | 1775 | 1174 | 0 | 0 |
T8 | 3641 | 2827 | 0 | 0 |
T9 | 4515 | 3493 | 0 | 0 |
T10 | 3312 | 2661 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 11790944 | 6990995 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11790944 | 6990995 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11790944 | 6990995 | 0 | 0 |
T1 | 2006 | 1241 | 0 | 0 |
T2 | 214513 | 151747 | 0 | 0 |
T3 | 133798 | 65536 | 0 | 0 |
T4 | 1674 | 992 | 0 | 0 |
T5 | 5294 | 529 | 0 | 0 |
T6 | 51987 | 40746 | 0 | 0 |
T7 | 1775 | 1174 | 0 | 0 |
T8 | 3641 | 2827 | 0 | 0 |
T9 | 4515 | 3493 | 0 | 0 |
T10 | 3312 | 2661 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11790944 | 6990995 | 0 | 0 |
T1 | 2006 | 1241 | 0 | 0 |
T2 | 214513 | 151747 | 0 | 0 |
T3 | 133798 | 65536 | 0 | 0 |
T4 | 1674 | 992 | 0 | 0 |
T5 | 5294 | 529 | 0 | 0 |
T6 | 51987 | 40746 | 0 | 0 |
T7 | 1775 | 1174 | 0 | 0 |
T8 | 3641 | 2827 | 0 | 0 |
T9 | 4515 | 3493 | 0 | 0 |
T10 | 3312 | 2661 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 11790944 | 6990995 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11790944 | 6990995 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11790944 | 6990995 | 0 | 0 |
T1 | 2006 | 1241 | 0 | 0 |
T2 | 214513 | 151747 | 0 | 0 |
T3 | 133798 | 65536 | 0 | 0 |
T4 | 1674 | 992 | 0 | 0 |
T5 | 5294 | 529 | 0 | 0 |
T6 | 51987 | 40746 | 0 | 0 |
T7 | 1775 | 1174 | 0 | 0 |
T8 | 3641 | 2827 | 0 | 0 |
T9 | 4515 | 3493 | 0 | 0 |
T10 | 3312 | 2661 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11790944 | 6990995 | 0 | 0 |
T1 | 2006 | 1241 | 0 | 0 |
T2 | 214513 | 151747 | 0 | 0 |
T3 | 133798 | 65536 | 0 | 0 |
T4 | 1674 | 992 | 0 | 0 |
T5 | 5294 | 529 | 0 | 0 |
T6 | 51987 | 40746 | 0 | 0 |
T7 | 1775 | 1174 | 0 | 0 |
T8 | 3641 | 2827 | 0 | 0 |
T9 | 4515 | 3493 | 0 | 0 |
T10 | 3312 | 2661 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 11790944 | 6990995 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11790944 | 6990995 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11790944 | 6990995 | 0 | 0 |
T1 | 2006 | 1241 | 0 | 0 |
T2 | 214513 | 151747 | 0 | 0 |
T3 | 133798 | 65536 | 0 | 0 |
T4 | 1674 | 992 | 0 | 0 |
T5 | 5294 | 529 | 0 | 0 |
T6 | 51987 | 40746 | 0 | 0 |
T7 | 1775 | 1174 | 0 | 0 |
T8 | 3641 | 2827 | 0 | 0 |
T9 | 4515 | 3493 | 0 | 0 |
T10 | 3312 | 2661 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11790944 | 6990995 | 0 | 0 |
T1 | 2006 | 1241 | 0 | 0 |
T2 | 214513 | 151747 | 0 | 0 |
T3 | 133798 | 65536 | 0 | 0 |
T4 | 1674 | 992 | 0 | 0 |
T5 | 5294 | 529 | 0 | 0 |
T6 | 51987 | 40746 | 0 | 0 |
T7 | 1775 | 1174 | 0 | 0 |
T8 | 3641 | 2827 | 0 | 0 |
T9 | 4515 | 3493 | 0 | 0 |
T10 | 3312 | 2661 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 11790944 | 6990995 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11790944 | 6990995 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11790944 | 6990995 | 0 | 0 |
T1 | 2006 | 1241 | 0 | 0 |
T2 | 214513 | 151747 | 0 | 0 |
T3 | 133798 | 65536 | 0 | 0 |
T4 | 1674 | 992 | 0 | 0 |
T5 | 5294 | 529 | 0 | 0 |
T6 | 51987 | 40746 | 0 | 0 |
T7 | 1775 | 1174 | 0 | 0 |
T8 | 3641 | 2827 | 0 | 0 |
T9 | 4515 | 3493 | 0 | 0 |
T10 | 3312 | 2661 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11790944 | 6990995 | 0 | 0 |
T1 | 2006 | 1241 | 0 | 0 |
T2 | 214513 | 151747 | 0 | 0 |
T3 | 133798 | 65536 | 0 | 0 |
T4 | 1674 | 992 | 0 | 0 |
T5 | 5294 | 529 | 0 | 0 |
T6 | 51987 | 40746 | 0 | 0 |
T7 | 1775 | 1174 | 0 | 0 |
T8 | 3641 | 2827 | 0 | 0 |
T9 | 4515 | 3493 | 0 | 0 |
T10 | 3312 | 2661 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 11790944 | 6990995 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11790944 | 6990995 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11790944 | 6990995 | 0 | 0 |
T1 | 2006 | 1241 | 0 | 0 |
T2 | 214513 | 151747 | 0 | 0 |
T3 | 133798 | 65536 | 0 | 0 |
T4 | 1674 | 992 | 0 | 0 |
T5 | 5294 | 529 | 0 | 0 |
T6 | 51987 | 40746 | 0 | 0 |
T7 | 1775 | 1174 | 0 | 0 |
T8 | 3641 | 2827 | 0 | 0 |
T9 | 4515 | 3493 | 0 | 0 |
T10 | 3312 | 2661 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11790944 | 6990995 | 0 | 0 |
T1 | 2006 | 1241 | 0 | 0 |
T2 | 214513 | 151747 | 0 | 0 |
T3 | 133798 | 65536 | 0 | 0 |
T4 | 1674 | 992 | 0 | 0 |
T5 | 5294 | 529 | 0 | 0 |
T6 | 51987 | 40746 | 0 | 0 |
T7 | 1775 | 1174 | 0 | 0 |
T8 | 3641 | 2827 | 0 | 0 |
T9 | 4515 | 3493 | 0 | 0 |
T10 | 3312 | 2661 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 11790944 | 6990995 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11790944 | 6990995 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11790944 | 6990995 | 0 | 0 |
T1 | 2006 | 1241 | 0 | 0 |
T2 | 214513 | 151747 | 0 | 0 |
T3 | 133798 | 65536 | 0 | 0 |
T4 | 1674 | 992 | 0 | 0 |
T5 | 5294 | 529 | 0 | 0 |
T6 | 51987 | 40746 | 0 | 0 |
T7 | 1775 | 1174 | 0 | 0 |
T8 | 3641 | 2827 | 0 | 0 |
T9 | 4515 | 3493 | 0 | 0 |
T10 | 3312 | 2661 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11790944 | 6990995 | 0 | 0 |
T1 | 2006 | 1241 | 0 | 0 |
T2 | 214513 | 151747 | 0 | 0 |
T3 | 133798 | 65536 | 0 | 0 |
T4 | 1674 | 992 | 0 | 0 |
T5 | 5294 | 529 | 0 | 0 |
T6 | 51987 | 40746 | 0 | 0 |
T7 | 1775 | 1174 | 0 | 0 |
T8 | 3641 | 2827 | 0 | 0 |
T9 | 4515 | 3493 | 0 | 0 |
T10 | 3312 | 2661 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 11790944 | 6990995 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11790944 | 6990995 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11790944 | 6990995 | 0 | 0 |
T1 | 2006 | 1241 | 0 | 0 |
T2 | 214513 | 151747 | 0 | 0 |
T3 | 133798 | 65536 | 0 | 0 |
T4 | 1674 | 992 | 0 | 0 |
T5 | 5294 | 529 | 0 | 0 |
T6 | 51987 | 40746 | 0 | 0 |
T7 | 1775 | 1174 | 0 | 0 |
T8 | 3641 | 2827 | 0 | 0 |
T9 | 4515 | 3493 | 0 | 0 |
T10 | 3312 | 2661 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11790944 | 6990995 | 0 | 0 |
T1 | 2006 | 1241 | 0 | 0 |
T2 | 214513 | 151747 | 0 | 0 |
T3 | 133798 | 65536 | 0 | 0 |
T4 | 1674 | 992 | 0 | 0 |
T5 | 5294 | 529 | 0 | 0 |
T6 | 51987 | 40746 | 0 | 0 |
T7 | 1775 | 1174 | 0 | 0 |
T8 | 3641 | 2827 | 0 | 0 |
T9 | 4515 | 3493 | 0 | 0 |
T10 | 3312 | 2661 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 11790944 | 6990995 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11790944 | 6990995 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11790944 | 6990995 | 0 | 0 |
T1 | 2006 | 1241 | 0 | 0 |
T2 | 214513 | 151747 | 0 | 0 |
T3 | 133798 | 65536 | 0 | 0 |
T4 | 1674 | 992 | 0 | 0 |
T5 | 5294 | 529 | 0 | 0 |
T6 | 51987 | 40746 | 0 | 0 |
T7 | 1775 | 1174 | 0 | 0 |
T8 | 3641 | 2827 | 0 | 0 |
T9 | 4515 | 3493 | 0 | 0 |
T10 | 3312 | 2661 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11790944 | 6990995 | 0 | 0 |
T1 | 2006 | 1241 | 0 | 0 |
T2 | 214513 | 151747 | 0 | 0 |
T3 | 133798 | 65536 | 0 | 0 |
T4 | 1674 | 992 | 0 | 0 |
T5 | 5294 | 529 | 0 | 0 |
T6 | 51987 | 40746 | 0 | 0 |
T7 | 1775 | 1174 | 0 | 0 |
T8 | 3641 | 2827 | 0 | 0 |
T9 | 4515 | 3493 | 0 | 0 |
T10 | 3312 | 2661 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 11790944 | 6990995 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11790944 | 6990995 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11790944 | 6990995 | 0 | 0 |
T1 | 2006 | 1241 | 0 | 0 |
T2 | 214513 | 151747 | 0 | 0 |
T3 | 133798 | 65536 | 0 | 0 |
T4 | 1674 | 992 | 0 | 0 |
T5 | 5294 | 529 | 0 | 0 |
T6 | 51987 | 40746 | 0 | 0 |
T7 | 1775 | 1174 | 0 | 0 |
T8 | 3641 | 2827 | 0 | 0 |
T9 | 4515 | 3493 | 0 | 0 |
T10 | 3312 | 2661 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11790944 | 6990995 | 0 | 0 |
T1 | 2006 | 1241 | 0 | 0 |
T2 | 214513 | 151747 | 0 | 0 |
T3 | 133798 | 65536 | 0 | 0 |
T4 | 1674 | 992 | 0 | 0 |
T5 | 5294 | 529 | 0 | 0 |
T6 | 51987 | 40746 | 0 | 0 |
T7 | 1775 | 1174 | 0 | 0 |
T8 | 3641 | 2827 | 0 | 0 |
T9 | 4515 | 3493 | 0 | 0 |
T10 | 3312 | 2661 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 11790944 | 6990995 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11790944 | 6990995 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11790944 | 6990995 | 0 | 0 |
T1 | 2006 | 1241 | 0 | 0 |
T2 | 214513 | 151747 | 0 | 0 |
T3 | 133798 | 65536 | 0 | 0 |
T4 | 1674 | 992 | 0 | 0 |
T5 | 5294 | 529 | 0 | 0 |
T6 | 51987 | 40746 | 0 | 0 |
T7 | 1775 | 1174 | 0 | 0 |
T8 | 3641 | 2827 | 0 | 0 |
T9 | 4515 | 3493 | 0 | 0 |
T10 | 3312 | 2661 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11790944 | 6990995 | 0 | 0 |
T1 | 2006 | 1241 | 0 | 0 |
T2 | 214513 | 151747 | 0 | 0 |
T3 | 133798 | 65536 | 0 | 0 |
T4 | 1674 | 992 | 0 | 0 |
T5 | 5294 | 529 | 0 | 0 |
T6 | 51987 | 40746 | 0 | 0 |
T7 | 1775 | 1174 | 0 | 0 |
T8 | 3641 | 2827 | 0 | 0 |
T9 | 4515 | 3493 | 0 | 0 |
T10 | 3312 | 2661 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 11790944 | 6990995 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11790944 | 6990995 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11790944 | 6990995 | 0 | 0 |
T1 | 2006 | 1241 | 0 | 0 |
T2 | 214513 | 151747 | 0 | 0 |
T3 | 133798 | 65536 | 0 | 0 |
T4 | 1674 | 992 | 0 | 0 |
T5 | 5294 | 529 | 0 | 0 |
T6 | 51987 | 40746 | 0 | 0 |
T7 | 1775 | 1174 | 0 | 0 |
T8 | 3641 | 2827 | 0 | 0 |
T9 | 4515 | 3493 | 0 | 0 |
T10 | 3312 | 2661 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11790944 | 6990995 | 0 | 0 |
T1 | 2006 | 1241 | 0 | 0 |
T2 | 214513 | 151747 | 0 | 0 |
T3 | 133798 | 65536 | 0 | 0 |
T4 | 1674 | 992 | 0 | 0 |
T5 | 5294 | 529 | 0 | 0 |
T6 | 51987 | 40746 | 0 | 0 |
T7 | 1775 | 1174 | 0 | 0 |
T8 | 3641 | 2827 | 0 | 0 |
T9 | 4515 | 3493 | 0 | 0 |
T10 | 3312 | 2661 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 11790944 | 6990995 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11790944 | 6990995 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11790944 | 6990995 | 0 | 0 |
T1 | 2006 | 1241 | 0 | 0 |
T2 | 214513 | 151747 | 0 | 0 |
T3 | 133798 | 65536 | 0 | 0 |
T4 | 1674 | 992 | 0 | 0 |
T5 | 5294 | 529 | 0 | 0 |
T6 | 51987 | 40746 | 0 | 0 |
T7 | 1775 | 1174 | 0 | 0 |
T8 | 3641 | 2827 | 0 | 0 |
T9 | 4515 | 3493 | 0 | 0 |
T10 | 3312 | 2661 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11790944 | 6990995 | 0 | 0 |
T1 | 2006 | 1241 | 0 | 0 |
T2 | 214513 | 151747 | 0 | 0 |
T3 | 133798 | 65536 | 0 | 0 |
T4 | 1674 | 992 | 0 | 0 |
T5 | 5294 | 529 | 0 | 0 |
T6 | 51987 | 40746 | 0 | 0 |
T7 | 1775 | 1174 | 0 | 0 |
T8 | 3641 | 2827 | 0 | 0 |
T9 | 4515 | 3493 | 0 | 0 |
T10 | 3312 | 2661 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 11790944 | 6990995 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11790944 | 6990995 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11790944 | 6990995 | 0 | 0 |
T1 | 2006 | 1241 | 0 | 0 |
T2 | 214513 | 151747 | 0 | 0 |
T3 | 133798 | 65536 | 0 | 0 |
T4 | 1674 | 992 | 0 | 0 |
T5 | 5294 | 529 | 0 | 0 |
T6 | 51987 | 40746 | 0 | 0 |
T7 | 1775 | 1174 | 0 | 0 |
T8 | 3641 | 2827 | 0 | 0 |
T9 | 4515 | 3493 | 0 | 0 |
T10 | 3312 | 2661 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11790944 | 6990995 | 0 | 0 |
T1 | 2006 | 1241 | 0 | 0 |
T2 | 214513 | 151747 | 0 | 0 |
T3 | 133798 | 65536 | 0 | 0 |
T4 | 1674 | 992 | 0 | 0 |
T5 | 5294 | 529 | 0 | 0 |
T6 | 51987 | 40746 | 0 | 0 |
T7 | 1775 | 1174 | 0 | 0 |
T8 | 3641 | 2827 | 0 | 0 |
T9 | 4515 | 3493 | 0 | 0 |
T10 | 3312 | 2661 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 11790944 | 6990995 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11790944 | 6990995 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11790944 | 6990995 | 0 | 0 |
T1 | 2006 | 1241 | 0 | 0 |
T2 | 214513 | 151747 | 0 | 0 |
T3 | 133798 | 65536 | 0 | 0 |
T4 | 1674 | 992 | 0 | 0 |
T5 | 5294 | 529 | 0 | 0 |
T6 | 51987 | 40746 | 0 | 0 |
T7 | 1775 | 1174 | 0 | 0 |
T8 | 3641 | 2827 | 0 | 0 |
T9 | 4515 | 3493 | 0 | 0 |
T10 | 3312 | 2661 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11790944 | 6990995 | 0 | 0 |
T1 | 2006 | 1241 | 0 | 0 |
T2 | 214513 | 151747 | 0 | 0 |
T3 | 133798 | 65536 | 0 | 0 |
T4 | 1674 | 992 | 0 | 0 |
T5 | 5294 | 529 | 0 | 0 |
T6 | 51987 | 40746 | 0 | 0 |
T7 | 1775 | 1174 | 0 | 0 |
T8 | 3641 | 2827 | 0 | 0 |
T9 | 4515 | 3493 | 0 | 0 |
T10 | 3312 | 2661 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 11790944 | 6990995 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11790944 | 6990995 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11790944 | 6990995 | 0 | 0 |
T1 | 2006 | 1241 | 0 | 0 |
T2 | 214513 | 151747 | 0 | 0 |
T3 | 133798 | 65536 | 0 | 0 |
T4 | 1674 | 992 | 0 | 0 |
T5 | 5294 | 529 | 0 | 0 |
T6 | 51987 | 40746 | 0 | 0 |
T7 | 1775 | 1174 | 0 | 0 |
T8 | 3641 | 2827 | 0 | 0 |
T9 | 4515 | 3493 | 0 | 0 |
T10 | 3312 | 2661 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11790944 | 6990995 | 0 | 0 |
T1 | 2006 | 1241 | 0 | 0 |
T2 | 214513 | 151747 | 0 | 0 |
T3 | 133798 | 65536 | 0 | 0 |
T4 | 1674 | 992 | 0 | 0 |
T5 | 5294 | 529 | 0 | 0 |
T6 | 51987 | 40746 | 0 | 0 |
T7 | 1775 | 1174 | 0 | 0 |
T8 | 3641 | 2827 | 0 | 0 |
T9 | 4515 | 3493 | 0 | 0 |
T10 | 3312 | 2661 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |