Module Definition
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Module : prim_generic_clock_mux2
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_lc_src.u_rst_aon_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_lc_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_sys_src.u_rst_aon_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_sys_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_daon_por.u_rst_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_daon_por_io.u_rst_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_daon_por_io_div2.u_rst_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_daon_por_io_div4.u_rst_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_daon_por_usb.u_rst_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_daon_lc.u_rst_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_d0_lc.u_rst_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_daon_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_d0_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_daon_lc_aon.u_rst_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_daon_lc_io.u_rst_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_d0_lc_io.u_rst_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_daon_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_d0_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_daon_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_d0_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_daon_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_d0_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_daon_lc_usb.u_rst_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_d0_lc_usb.u_rst_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_d0_sys.u_rst_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_daon_sys_io_div4.u_rst_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_d0_spi_device.u_rst_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_d0_spi_host0.u_rst_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_d0_spi_host1.u_rst_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_d0_usb.u_rst_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_d0_usb_aon.u_rst_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_d0_i2c0.u_rst_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_d0_i2c1.u_rst_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_d0_i2c1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_d0_i2c2.u_rst_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_root_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_clean_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_out_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_lc_src.u_rst_aon_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_aon_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_lc_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_rst_pd_n[0].u_rst_pd_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_sys_src.u_rst_aon_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_aon_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_sys_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_rst_pd_n[0].u_rst_pd_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_daon_por.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
g_scan_mux.u_scan_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_daon_por_io.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
g_scan_mux.u_scan_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_daon_por_io_div2.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
g_scan_mux.u_scan_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_daon_por_io_div4.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
g_scan_mux.u_scan_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_daon_por_usb.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
g_scan_mux.u_scan_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_daon_lc.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
g_scan_mux.u_scan_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_d0_lc.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
g_scan_mux.u_scan_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_daon_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
g_scan_mux.u_scan_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_d0_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
g_scan_mux.u_scan_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_daon_lc_aon.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
g_scan_mux.u_scan_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_daon_lc_io.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
g_scan_mux.u_scan_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_d0_lc_io.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
g_scan_mux.u_scan_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_daon_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
g_scan_mux.u_scan_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_d0_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
g_scan_mux.u_scan_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_daon_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_d0_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_daon_lc_usb.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
g_scan_mux.u_scan_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_d0_lc_usb.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
g_scan_mux.u_scan_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_d0_sys.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
g_scan_mux.u_scan_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_daon_sys_io_div4.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
g_scan_mux.u_scan_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_d0_spi_device.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
g_scan_mux.u_scan_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_d0_spi_host0.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
g_scan_mux.u_scan_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_d0_spi_host1.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
g_scan_mux.u_scan_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_d0_usb.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
g_scan_mux.u_scan_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_d0_usb_aon.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
g_scan_mux.u_scan_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_d0_i2c0.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
g_scan_mux.u_scan_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_d0_i2c1.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_d0_i2c1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
g_scan_mux.u_scan_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_d0_i2c2.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
g_scan_mux.u_scan_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_root_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_root_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_clean_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_clean_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_out_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_out_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T6
11CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT2,T3,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 1371719 1339399 0 0
selKnown1 197248 164928 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 1371719 1339399 0 0
T1 550 495 0 0
T2 21684 21620 0 0
T3 25146 25082 0 0
T4 284 220 0 0
T5 534 470 0 0
T6 3976 3912 0 0
T7 64 0 0 0
T8 889 825 0 0
T9 348 284 0 0
T10 138 74 0 0
T11 0 243 0 0
T12 0 791 0 0
T13 0 765 0 0
T14 72 470 0 0
T70 0 63 0 0
T84 0 7 0 0
T85 0 7 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 197248 164928 0 0
T2 4864 4800 0 0
T3 4288 4224 0 0
T4 64 0 0 0
T5 64 0 0 0
T6 960 896 0 0
T7 64 0 0 0
T8 64 0 0 0
T9 128 64 0 0
T10 64 0 0 0
T11 0 64 0 0
T12 0 2944 0 0
T13 0 2880 0 0
T14 64 0 0 0
T42 0 768 0 0
T43 0 64 0 0
T45 0 64 0 0

Line Coverage for Instance : tb.dut.u_lc_src.u_rst_aon_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_lc_src.u_rst_aon_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T6
11CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT2,T3,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_lc_src.u_rst_aon_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 23314 22809 0 0
selKnown1 3082 2577 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 23314 22809 0 0
T1 10 9 0 0
T2 371 370 0 0
T3 433 432 0 0
T4 5 4 0 0
T5 8 7 0 0
T6 68 67 0 0
T7 1 0 0 0
T8 16 15 0 0
T9 6 5 0 0
T10 1 0 0 0
T11 0 5 0 0
T14 0 7 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 3082 2577 0 0
T2 76 75 0 0
T3 67 66 0 0
T4 1 0 0 0
T5 1 0 0 0
T6 15 14 0 0
T7 1 0 0 0
T8 1 0 0 0
T9 2 1 0 0
T10 1 0 0 0
T11 0 1 0 0
T12 0 46 0 0
T13 0 45 0 0
T14 1 0 0 0
T42 0 12 0 0
T43 0 1 0 0
T45 0 1 0 0

Line Coverage for Instance : tb.dut.u_lc_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_lc_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T6
11CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT2,T3,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_lc_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 23314 22809 0 0
selKnown1 3082 2577 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 23314 22809 0 0
T1 10 9 0 0
T2 371 370 0 0
T3 433 432 0 0
T4 5 4 0 0
T5 8 7 0 0
T6 68 67 0 0
T7 1 0 0 0
T8 16 15 0 0
T9 6 5 0 0
T10 1 0 0 0
T11 0 5 0 0
T14 0 7 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 3082 2577 0 0
T2 76 75 0 0
T3 67 66 0 0
T4 1 0 0 0
T5 1 0 0 0
T6 15 14 0 0
T7 1 0 0 0
T8 1 0 0 0
T9 2 1 0 0
T10 1 0 0 0
T11 0 1 0 0
T12 0 46 0 0
T13 0 45 0 0
T14 1 0 0 0
T42 0 12 0 0
T43 0 1 0 0
T45 0 1 0 0

Line Coverage for Instance : tb.dut.u_sys_src.u_rst_aon_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_sys_src.u_rst_aon_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T6
11CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT2,T3,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sys_src.u_rst_aon_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 23314 22809 0 0
selKnown1 3082 2577 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 23314 22809 0 0
T1 10 9 0 0
T2 371 370 0 0
T3 433 432 0 0
T4 5 4 0 0
T5 8 7 0 0
T6 68 67 0 0
T7 1 0 0 0
T8 16 15 0 0
T9 6 5 0 0
T10 1 0 0 0
T11 0 5 0 0
T14 0 7 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 3082 2577 0 0
T2 76 75 0 0
T3 67 66 0 0
T4 1 0 0 0
T5 1 0 0 0
T6 15 14 0 0
T7 1 0 0 0
T8 1 0 0 0
T9 2 1 0 0
T10 1 0 0 0
T11 0 1 0 0
T12 0 46 0 0
T13 0 45 0 0
T14 1 0 0 0
T42 0 12 0 0
T43 0 1 0 0
T45 0 1 0 0

Line Coverage for Instance : tb.dut.u_sys_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_sys_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T6
11CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT2,T3,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sys_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 23314 22809 0 0
selKnown1 3082 2577 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 23314 22809 0 0
T1 10 9 0 0
T2 371 370 0 0
T3 433 432 0 0
T4 5 4 0 0
T5 8 7 0 0
T6 68 67 0 0
T7 1 0 0 0
T8 16 15 0 0
T9 6 5 0 0
T10 1 0 0 0
T11 0 5 0 0
T14 0 7 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 3082 2577 0 0
T2 76 75 0 0
T3 67 66 0 0
T4 1 0 0 0
T5 1 0 0 0
T6 15 14 0 0
T7 1 0 0 0
T8 1 0 0 0
T9 2 1 0 0
T10 1 0 0 0
T11 0 1 0 0
T12 0 46 0 0
T13 0 45 0 0
T14 1 0 0 0
T42 0 12 0 0
T43 0 1 0 0
T45 0 1 0 0

Line Coverage for Instance : tb.dut.u_daon_por.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_daon_por.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T6
11CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT2,T3,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_daon_por.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 8967 8462 0 0
selKnown1 3082 2577 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 8967 8462 0 0
T2 141 140 0 0
T3 145 144 0 0
T4 1 0 0 0
T5 8 7 0 0
T6 25 24 0 0
T7 1 0 0 0
T8 1 0 0 0
T9 2 1 0 0
T10 1 0 0 0
T11 0 1 0 0
T12 0 93 0 0
T13 0 90 0 0
T14 8 7 0 0
T70 0 7 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 3082 2577 0 0
T2 76 75 0 0
T3 67 66 0 0
T4 1 0 0 0
T5 1 0 0 0
T6 15 14 0 0
T7 1 0 0 0
T8 1 0 0 0
T9 2 1 0 0
T10 1 0 0 0
T11 0 1 0 0
T12 0 46 0 0
T13 0 45 0 0
T14 1 0 0 0
T42 0 12 0 0
T43 0 1 0 0
T45 0 1 0 0

Line Coverage for Instance : tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T6
11CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT2,T3,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 23364 22859 0 0
selKnown1 3082 2577 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 23364 22859 0 0
T1 10 9 0 0
T2 371 370 0 0
T3 433 432 0 0
T4 5 4 0 0
T5 9 8 0 0
T6 68 67 0 0
T7 1 0 0 0
T8 16 15 0 0
T9 6 5 0 0
T10 1 0 0 0
T11 0 5 0 0
T14 0 8 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 3082 2577 0 0
T2 76 75 0 0
T3 67 66 0 0
T4 1 0 0 0
T5 1 0 0 0
T6 15 14 0 0
T7 1 0 0 0
T8 1 0 0 0
T9 2 1 0 0
T10 1 0 0 0
T11 0 1 0 0
T12 0 46 0 0
T13 0 45 0 0
T14 1 0 0 0
T42 0 12 0 0
T43 0 1 0 0
T45 0 1 0 0

Line Coverage for Instance : tb.dut.u_daon_por_io.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_daon_por_io.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T6
11CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT2,T3,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_daon_por_io.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 8967 8462 0 0
selKnown1 3082 2577 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 8967 8462 0 0
T2 141 140 0 0
T3 145 144 0 0
T4 1 0 0 0
T5 8 7 0 0
T6 25 24 0 0
T7 1 0 0 0
T8 1 0 0 0
T9 2 1 0 0
T10 1 0 0 0
T11 0 1 0 0
T12 0 93 0 0
T13 0 90 0 0
T14 8 7 0 0
T70 0 7 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 3082 2577 0 0
T2 76 75 0 0
T3 67 66 0 0
T4 1 0 0 0
T5 1 0 0 0
T6 15 14 0 0
T7 1 0 0 0
T8 1 0 0 0
T9 2 1 0 0
T10 1 0 0 0
T11 0 1 0 0
T12 0 46 0 0
T13 0 45 0 0
T14 1 0 0 0
T42 0 12 0 0
T43 0 1 0 0
T45 0 1 0 0

Line Coverage for Instance : tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T6
11CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT2,T3,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 23364 22859 0 0
selKnown1 3082 2577 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 23364 22859 0 0
T1 10 9 0 0
T2 371 370 0 0
T3 433 432 0 0
T4 5 4 0 0
T5 9 8 0 0
T6 68 67 0 0
T7 1 0 0 0
T8 16 15 0 0
T9 6 5 0 0
T10 1 0 0 0
T11 0 5 0 0
T14 0 8 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 3082 2577 0 0
T2 76 75 0 0
T3 67 66 0 0
T4 1 0 0 0
T5 1 0 0 0
T6 15 14 0 0
T7 1 0 0 0
T8 1 0 0 0
T9 2 1 0 0
T10 1 0 0 0
T11 0 1 0 0
T12 0 46 0 0
T13 0 45 0 0
T14 1 0 0 0
T42 0 12 0 0
T43 0 1 0 0
T45 0 1 0 0

Line Coverage for Instance : tb.dut.u_daon_por_io_div2.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_daon_por_io_div2.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T6
11CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT2,T3,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_daon_por_io_div2.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 8967 8462 0 0
selKnown1 3082 2577 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 8967 8462 0 0
T2 141 140 0 0
T3 145 144 0 0
T4 1 0 0 0
T5 8 7 0 0
T6 25 24 0 0
T7 1 0 0 0
T8 1 0 0 0
T9 2 1 0 0
T10 1 0 0 0
T11 0 1 0 0
T12 0 93 0 0
T13 0 90 0 0
T14 8 7 0 0
T70 0 7 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 3082 2577 0 0
T2 76 75 0 0
T3 67 66 0 0
T4 1 0 0 0
T5 1 0 0 0
T6 15 14 0 0
T7 1 0 0 0
T8 1 0 0 0
T9 2 1 0 0
T10 1 0 0 0
T11 0 1 0 0
T12 0 46 0 0
T13 0 45 0 0
T14 1 0 0 0
T42 0 12 0 0
T43 0 1 0 0
T45 0 1 0 0

Line Coverage for Instance : tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T6
11CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT2,T3,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 23364 22859 0 0
selKnown1 3082 2577 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 23364 22859 0 0
T1 10 9 0 0
T2 371 370 0 0
T3 433 432 0 0
T4 5 4 0 0
T5 9 8 0 0
T6 68 67 0 0
T7 1 0 0 0
T8 16 15 0 0
T9 6 5 0 0
T10 1 0 0 0
T11 0 5 0 0
T14 0 8 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 3082 2577 0 0
T2 76 75 0 0
T3 67 66 0 0
T4 1 0 0 0
T5 1 0 0 0
T6 15 14 0 0
T7 1 0 0 0
T8 1 0 0 0
T9 2 1 0 0
T10 1 0 0 0
T11 0 1 0 0
T12 0 46 0 0
T13 0 45 0 0
T14 1 0 0 0
T42 0 12 0 0
T43 0 1 0 0
T45 0 1 0 0

Line Coverage for Instance : tb.dut.u_daon_por_io_div4.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_daon_por_io_div4.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T6
11CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT2,T3,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_daon_por_io_div4.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 8967 8462 0 0
selKnown1 3082 2577 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 8967 8462 0 0
T2 141 140 0 0
T3 145 144 0 0
T4 1 0 0 0
T5 8 7 0 0
T6 25 24 0 0
T7 1 0 0 0
T8 1 0 0 0
T9 2 1 0 0
T10 1 0 0 0
T11 0 1 0 0
T12 0 93 0 0
T13 0 90 0 0
T14 8 7 0 0
T70 0 7 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 3082 2577 0 0
T2 76 75 0 0
T3 67 66 0 0
T4 1 0 0 0
T5 1 0 0 0
T6 15 14 0 0
T7 1 0 0 0
T8 1 0 0 0
T9 2 1 0 0
T10 1 0 0 0
T11 0 1 0 0
T12 0 46 0 0
T13 0 45 0 0
T14 1 0 0 0
T42 0 12 0 0
T43 0 1 0 0
T45 0 1 0 0

Line Coverage for Instance : tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T6
11CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT2,T3,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 23364 22859 0 0
selKnown1 3082 2577 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 23364 22859 0 0
T1 10 9 0 0
T2 371 370 0 0
T3 433 432 0 0
T4 5 4 0 0
T5 9 8 0 0
T6 68 67 0 0
T7 1 0 0 0
T8 16 15 0 0
T9 6 5 0 0
T10 1 0 0 0
T11 0 5 0 0
T14 0 8 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 3082 2577 0 0
T2 76 75 0 0
T3 67 66 0 0
T4 1 0 0 0
T5 1 0 0 0
T6 15 14 0 0
T7 1 0 0 0
T8 1 0 0 0
T9 2 1 0 0
T10 1 0 0 0
T11 0 1 0 0
T12 0 46 0 0
T13 0 45 0 0
T14 1 0 0 0
T42 0 12 0 0
T43 0 1 0 0
T45 0 1 0 0

Line Coverage for Instance : tb.dut.u_daon_por_usb.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_daon_por_usb.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T6
11CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT2,T3,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_daon_por_usb.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 8967 8462 0 0
selKnown1 3082 2577 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 8967 8462 0 0
T2 141 140 0 0
T3 145 144 0 0
T4 1 0 0 0
T5 8 7 0 0
T6 25 24 0 0
T7 1 0 0 0
T8 1 0 0 0
T9 2 1 0 0
T10 1 0 0 0
T11 0 1 0 0
T12 0 93 0 0
T13 0 90 0 0
T14 8 7 0 0
T70 0 7 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 3082 2577 0 0
T2 76 75 0 0
T3 67 66 0 0
T4 1 0 0 0
T5 1 0 0 0
T6 15 14 0 0
T7 1 0 0 0
T8 1 0 0 0
T9 2 1 0 0
T10 1 0 0 0
T11 0 1 0 0
T12 0 46 0 0
T13 0 45 0 0
T14 1 0 0 0
T42 0 12 0 0
T43 0 1 0 0
T45 0 1 0 0

Line Coverage for Instance : tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T6
11CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT2,T3,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 23364 22859 0 0
selKnown1 3082 2577 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 23364 22859 0 0
T1 10 9 0 0
T2 371 370 0 0
T3 433 432 0 0
T4 5 4 0 0
T5 9 8 0 0
T6 68 67 0 0
T7 1 0 0 0
T8 16 15 0 0
T9 6 5 0 0
T10 1 0 0 0
T11 0 5 0 0
T14 0 8 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 3082 2577 0 0
T2 76 75 0 0
T3 67 66 0 0
T4 1 0 0 0
T5 1 0 0 0
T6 15 14 0 0
T7 1 0 0 0
T8 1 0 0 0
T9 2 1 0 0
T10 1 0 0 0
T11 0 1 0 0
T12 0 46 0 0
T13 0 45 0 0
T14 1 0 0 0
T42 0 12 0 0
T43 0 1 0 0
T45 0 1 0 0

Line Coverage for Instance : tb.dut.u_daon_lc.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_daon_lc.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T6
11CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT2,T3,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_daon_lc.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 23314 22809 0 0
selKnown1 3082 2577 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 23314 22809 0 0
T1 10 9 0 0
T2 371 370 0 0
T3 433 432 0 0
T4 5 4 0 0
T5 8 7 0 0
T6 68 67 0 0
T7 1 0 0 0
T8 16 15 0 0
T9 6 5 0 0
T10 1 0 0 0
T11 0 5 0 0
T14 0 7 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 3082 2577 0 0
T2 76 75 0 0
T3 67 66 0 0
T4 1 0 0 0
T5 1 0 0 0
T6 15 14 0 0
T7 1 0 0 0
T8 1 0 0 0
T9 2 1 0 0
T10 1 0 0 0
T11 0 1 0 0
T12 0 46 0 0
T13 0 45 0 0
T14 1 0 0 0
T42 0 12 0 0
T43 0 1 0 0
T45 0 1 0 0

Line Coverage for Instance : tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T6
11CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT2,T3,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 23364 22859 0 0
selKnown1 3082 2577 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 23364 22859 0 0
T1 10 9 0 0
T2 371 370 0 0
T3 433 432 0 0
T4 5 4 0 0
T5 9 8 0 0
T6 68 67 0 0
T7 1 0 0 0
T8 16 15 0 0
T9 6 5 0 0
T10 1 0 0 0
T11 0 5 0 0
T14 0 8 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 3082 2577 0 0
T2 76 75 0 0
T3 67 66 0 0
T4 1 0 0 0
T5 1 0 0 0
T6 15 14 0 0
T7 1 0 0 0
T8 1 0 0 0
T9 2 1 0 0
T10 1 0 0 0
T11 0 1 0 0
T12 0 46 0 0
T13 0 45 0 0
T14 1 0 0 0
T42 0 12 0 0
T43 0 1 0 0
T45 0 1 0 0

Line Coverage for Instance : tb.dut.u_d0_lc.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_d0_lc.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T6
11CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT2,T3,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_lc.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 23314 22809 0 0
selKnown1 3082 2577 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 23314 22809 0 0
T1 10 9 0 0
T2 371 370 0 0
T3 433 432 0 0
T4 5 4 0 0
T5 8 7 0 0
T6 68 67 0 0
T7 1 0 0 0
T8 16 15 0 0
T9 6 5 0 0
T10 1 0 0 0
T11 0 5 0 0
T14 0 7 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 3082 2577 0 0
T2 76 75 0 0
T3 67 66 0 0
T4 1 0 0 0
T5 1 0 0 0
T6 15 14 0 0
T7 1 0 0 0
T8 1 0 0 0
T9 2 1 0 0
T10 1 0 0 0
T11 0 1 0 0
T12 0 46 0 0
T13 0 45 0 0
T14 1 0 0 0
T42 0 12 0 0
T43 0 1 0 0
T45 0 1 0 0

Line Coverage for Instance : tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T6
11CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT2,T3,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 23364 22859 0 0
selKnown1 3082 2577 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 23364 22859 0 0
T1 10 9 0 0
T2 371 370 0 0
T3 433 432 0 0
T4 5 4 0 0
T5 9 8 0 0
T6 68 67 0 0
T7 1 0 0 0
T8 16 15 0 0
T9 6 5 0 0
T10 1 0 0 0
T11 0 5 0 0
T14 0 8 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 3082 2577 0 0
T2 76 75 0 0
T3 67 66 0 0
T4 1 0 0 0
T5 1 0 0 0
T6 15 14 0 0
T7 1 0 0 0
T8 1 0 0 0
T9 2 1 0 0
T10 1 0 0 0
T11 0 1 0 0
T12 0 46 0 0
T13 0 45 0 0
T14 1 0 0 0
T42 0 12 0 0
T43 0 1 0 0
T45 0 1 0 0

Line Coverage for Instance : tb.dut.u_daon_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_daon_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T6
11CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT2,T3,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_daon_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 23314 22809 0 0
selKnown1 3082 2577 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 23314 22809 0 0
T1 10 9 0 0
T2 371 370 0 0
T3 433 432 0 0
T4 5 4 0 0
T5 8 7 0 0
T6 68 67 0 0
T7 1 0 0 0
T8 16 15 0 0
T9 6 5 0 0
T10 1 0 0 0
T11 0 5 0 0
T14 0 7 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 3082 2577 0 0
T2 76 75 0 0
T3 67 66 0 0
T4 1 0 0 0
T5 1 0 0 0
T6 15 14 0 0
T7 1 0 0 0
T8 1 0 0 0
T9 2 1 0 0
T10 1 0 0 0
T11 0 1 0 0
T12 0 46 0 0
T13 0 45 0 0
T14 1 0 0 0
T42 0 12 0 0
T43 0 1 0 0
T45 0 1 0 0

Line Coverage for Instance : tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T6
11CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT2,T3,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 23364 22859 0 0
selKnown1 3082 2577 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 23364 22859 0 0
T1 10 9 0 0
T2 371 370 0 0
T3 433 432 0 0
T4 5 4 0 0
T5 9 8 0 0
T6 68 67 0 0
T7 1 0 0 0
T8 16 15 0 0
T9 6 5 0 0
T10 1 0 0 0
T11 0 5 0 0
T14 0 8 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 3082 2577 0 0
T2 76 75 0 0
T3 67 66 0 0
T4 1 0 0 0
T5 1 0 0 0
T6 15 14 0 0
T7 1 0 0 0
T8 1 0 0 0
T9 2 1 0 0
T10 1 0 0 0
T11 0 1 0 0
T12 0 46 0 0
T13 0 45 0 0
T14 1 0 0 0
T42 0 12 0 0
T43 0 1 0 0
T45 0 1 0 0

Line Coverage for Instance : tb.dut.u_d0_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_d0_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T6
11CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT2,T3,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 23314 22809 0 0
selKnown1 3082 2577 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 23314 22809 0 0
T1 10 9 0 0
T2 371 370 0 0
T3 433 432 0 0
T4 5 4 0 0
T5 8 7 0 0
T6 68 67 0 0
T7 1 0 0 0
T8 16 15 0 0
T9 6 5 0 0
T10 1 0 0 0
T11 0 5 0 0
T14 0 7 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 3082 2577 0 0
T2 76 75 0 0
T3 67 66 0 0
T4 1 0 0 0
T5 1 0 0 0
T6 15 14 0 0
T7 1 0 0 0
T8 1 0 0 0
T9 2 1 0 0
T10 1 0 0 0
T11 0 1 0 0
T12 0 46 0 0
T13 0 45 0 0
T14 1 0 0 0
T42 0 12 0 0
T43 0 1 0 0
T45 0 1 0 0

Line Coverage for Instance : tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T6
11CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT2,T3,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 23364 22859 0 0
selKnown1 3082 2577 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 23364 22859 0 0
T1 10 9 0 0
T2 371 370 0 0
T3 433 432 0 0
T4 5 4 0 0
T5 9 8 0 0
T6 68 67 0 0
T7 1 0 0 0
T8 16 15 0 0
T9 6 5 0 0
T10 1 0 0 0
T11 0 5 0 0
T14 0 8 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 3082 2577 0 0
T2 76 75 0 0
T3 67 66 0 0
T4 1 0 0 0
T5 1 0 0 0
T6 15 14 0 0
T7 1 0 0 0
T8 1 0 0 0
T9 2 1 0 0
T10 1 0 0 0
T11 0 1 0 0
T12 0 46 0 0
T13 0 45 0 0
T14 1 0 0 0
T42 0 12 0 0
T43 0 1 0 0
T45 0 1 0 0

Line Coverage for Instance : tb.dut.u_daon_lc_aon.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_daon_lc_aon.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T6
11CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT2,T3,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_daon_lc_aon.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 23314 22809 0 0
selKnown1 3082 2577 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 23314 22809 0 0
T1 10 9 0 0
T2 371 370 0 0
T3 433 432 0 0
T4 5 4 0 0
T5 8 7 0 0
T6 68 67 0 0
T7 1 0 0 0
T8 16 15 0 0
T9 6 5 0 0
T10 1 0 0 0
T11 0 5 0 0
T14 0 7 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 3082 2577 0 0
T2 76 75 0 0
T3 67 66 0 0
T4 1 0 0 0
T5 1 0 0 0
T6 15 14 0 0
T7 1 0 0 0
T8 1 0 0 0
T9 2 1 0 0
T10 1 0 0 0
T11 0 1 0 0
T12 0 46 0 0
T13 0 45 0 0
T14 1 0 0 0
T42 0 12 0 0
T43 0 1 0 0
T45 0 1 0 0

Line Coverage for Instance : tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T6
11CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT2,T3,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 23248 22743 0 0
selKnown1 3082 2577 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 23248 22743 0 0
T1 10 9 0 0
T2 371 370 0 0
T3 433 432 0 0
T4 5 4 0 0
T5 7 6 0 0
T6 67 66 0 0
T7 1 0 0 0
T8 16 15 0 0
T9 6 5 0 0
T10 1 0 0 0
T11 0 5 0 0
T14 0 6 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 3082 2577 0 0
T2 76 75 0 0
T3 67 66 0 0
T4 1 0 0 0
T5 1 0 0 0
T6 15 14 0 0
T7 1 0 0 0
T8 1 0 0 0
T9 2 1 0 0
T10 1 0 0 0
T11 0 1 0 0
T12 0 46 0 0
T13 0 45 0 0
T14 1 0 0 0
T42 0 12 0 0
T43 0 1 0 0
T45 0 1 0 0

Line Coverage for Instance : tb.dut.u_daon_lc_io.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_daon_lc_io.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T6
11CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT2,T3,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_daon_lc_io.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 23314 22809 0 0
selKnown1 3082 2577 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 23314 22809 0 0
T1 10 9 0 0
T2 371 370 0 0
T3 433 432 0 0
T4 5 4 0 0
T5 8 7 0 0
T6 68 67 0 0
T7 1 0 0 0
T8 16 15 0 0
T9 6 5 0 0
T10 1 0 0 0
T11 0 5 0 0
T14 0 7 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 3082 2577 0 0
T2 76 75 0 0
T3 67 66 0 0
T4 1 0 0 0
T5 1 0 0 0
T6 15 14 0 0
T7 1 0 0 0
T8 1 0 0 0
T9 2 1 0 0
T10 1 0 0 0
T11 0 1 0 0
T12 0 46 0 0
T13 0 45 0 0
T14 1 0 0 0
T42 0 12 0 0
T43 0 1 0 0
T45 0 1 0 0

Line Coverage for Instance : tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T6
11CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT2,T3,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 23364 22859 0 0
selKnown1 3082 2577 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 23364 22859 0 0
T1 10 9 0 0
T2 371 370 0 0
T3 433 432 0 0
T4 5 4 0 0
T5 9 8 0 0
T6 68 67 0 0
T7 1 0 0 0
T8 16 15 0 0
T9 6 5 0 0
T10 1 0 0 0
T11 0 5 0 0
T14 0 8 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 3082 2577 0 0
T2 76 75 0 0
T3 67 66 0 0
T4 1 0 0 0
T5 1 0 0 0
T6 15 14 0 0
T7 1 0 0 0
T8 1 0 0 0
T9 2 1 0 0
T10 1 0 0 0
T11 0 1 0 0
T12 0 46 0 0
T13 0 45 0 0
T14 1 0 0 0
T42 0 12 0 0
T43 0 1 0 0
T45 0 1 0 0

Line Coverage for Instance : tb.dut.u_d0_lc_io.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_d0_lc_io.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T6
11CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT2,T3,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_lc_io.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 23314 22809 0 0
selKnown1 3082 2577 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 23314 22809 0 0
T1 10 9 0 0
T2 371 370 0 0
T3 433 432 0 0
T4 5 4 0 0
T5 8 7 0 0
T6 68 67 0 0
T7 1 0 0 0
T8 16 15 0 0
T9 6 5 0 0
T10 1 0 0 0
T11 0 5 0 0
T14 0 7 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 3082 2577 0 0
T2 76 75 0 0
T3 67 66 0 0
T4 1 0 0 0
T5 1 0 0 0
T6 15 14 0 0
T7 1 0 0 0
T8 1 0 0 0
T9 2 1 0 0
T10 1 0 0 0
T11 0 1 0 0
T12 0 46 0 0
T13 0 45 0 0
T14 1 0 0 0
T42 0 12 0 0
T43 0 1 0 0
T45 0 1 0 0

Line Coverage for Instance : tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T6
11CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT2,T3,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 23364 22859 0 0
selKnown1 3082 2577 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 23364 22859 0 0
T1 10 9 0 0
T2 371 370 0 0
T3 433 432 0 0
T4 5 4 0 0
T5 9 8 0 0
T6 68 67 0 0
T7 1 0 0 0
T8 16 15 0 0
T9 6 5 0 0
T10 1 0 0 0
T11 0 5 0 0
T14 0 8 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 3082 2577 0 0
T2 76 75 0 0
T3 67 66 0 0
T4 1 0 0 0
T5 1 0 0 0
T6 15 14 0 0
T7 1 0 0 0
T8 1 0 0 0
T9 2 1 0 0
T10 1 0 0 0
T11 0 1 0 0
T12 0 46 0 0
T13 0 45 0 0
T14 1 0 0 0
T42 0 12 0 0
T43 0 1 0 0
T45 0 1 0 0

Line Coverage for Instance : tb.dut.u_daon_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_daon_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T6
11CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT2,T3,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_daon_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 23314 22809 0 0
selKnown1 3082 2577 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 23314 22809 0 0
T1 10 9 0 0
T2 371 370 0 0
T3 433 432 0 0
T4 5 4 0 0
T5 8 7 0 0
T6 68 67 0 0
T7 1 0 0 0
T8 16 15 0 0
T9 6 5 0 0
T10 1 0 0 0
T11 0 5 0 0
T14 0 7 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 3082 2577 0 0
T2 76 75 0 0
T3 67 66 0 0
T4 1 0 0 0
T5 1 0 0 0
T6 15 14 0 0
T7 1 0 0 0
T8 1 0 0 0
T9 2 1 0 0
T10 1 0 0 0
T11 0 1 0 0
T12 0 46 0 0
T13 0 45 0 0
T14 1 0 0 0
T42 0 12 0 0
T43 0 1 0 0
T45 0 1 0 0

Line Coverage for Instance : tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T6
11CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT2,T3,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 23364 22859 0 0
selKnown1 3082 2577 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 23364 22859 0 0
T1 10 9 0 0
T2 371 370 0 0
T3 433 432 0 0
T4 5 4 0 0
T5 9 8 0 0
T6 68 67 0 0
T7 1 0 0 0
T8 16 15 0 0
T9 6 5 0 0
T10 1 0 0 0
T11 0 5 0 0
T14 0 8 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 3082 2577 0 0
T2 76 75 0 0
T3 67 66 0 0
T4 1 0 0 0
T5 1 0 0 0
T6 15 14 0 0
T7 1 0 0 0
T8 1 0 0 0
T9 2 1 0 0
T10 1 0 0 0
T11 0 1 0 0
T12 0 46 0 0
T13 0 45 0 0
T14 1 0 0 0
T42 0 12 0 0
T43 0 1 0 0
T45 0 1 0 0

Line Coverage for Instance : tb.dut.u_d0_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_d0_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T6
11CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT2,T3,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 23314 22809 0 0
selKnown1 3082 2577 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 23314 22809 0 0
T1 10 9 0 0
T2 371 370 0 0
T3 433 432 0 0
T4 5 4 0 0
T5 8 7 0 0
T6 68 67 0 0
T7 1 0 0 0
T8 16 15 0 0
T9 6 5 0 0
T10 1 0 0 0
T11 0 5 0 0
T14 0 7 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 3082 2577 0 0
T2 76 75 0 0
T3 67 66 0 0
T4 1 0 0 0
T5 1 0 0 0
T6 15 14 0 0
T7 1 0 0 0
T8 1 0 0 0
T9 2 1 0 0
T10 1 0 0 0
T11 0 1 0 0
T12 0 46 0 0
T13 0 45 0 0
T14 1 0 0 0
T42 0 12 0 0
T43 0 1 0 0
T45 0 1 0 0

Line Coverage for Instance : tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T6
11CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT2,T3,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 23364 22859 0 0
selKnown1 3082 2577 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 23364 22859 0 0
T1 10 9 0 0
T2 371 370 0 0
T3 433 432 0 0
T4 5 4 0 0
T5 9 8 0 0
T6 68 67 0 0
T7 1 0 0 0
T8 16 15 0 0
T9 6 5 0 0
T10 1 0 0 0
T11 0 5 0 0
T14 0 8 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 3082 2577 0 0
T2 76 75 0 0
T3 67 66 0 0
T4 1 0 0 0
T5 1 0 0 0
T6 15 14 0 0
T7 1 0 0 0
T8 1 0 0 0
T9 2 1 0 0
T10 1 0 0 0
T11 0 1 0 0
T12 0 46 0 0
T13 0 45 0 0
T14 1 0 0 0
T42 0 12 0 0
T43 0 1 0 0
T45 0 1 0 0

Line Coverage for Instance : tb.dut.u_daon_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_daon_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T6
11CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT2,T3,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_daon_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 23314 22809 0 0
selKnown1 3082 2577 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 23314 22809 0 0
T1 10 9 0 0
T2 371 370 0 0
T3 433 432 0 0
T4 5 4 0 0
T5 8 7 0 0
T6 68 67 0 0
T7 1 0 0 0
T8 16 15 0 0
T9 6 5 0 0
T10 1 0 0 0
T11 0 5 0 0
T14 0 7 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 3082 2577 0 0
T2 76 75 0 0
T3 67 66 0 0
T4 1 0 0 0
T5 1 0 0 0
T6 15 14 0 0
T7 1 0 0 0
T8 1 0 0 0
T9 2 1 0 0
T10 1 0 0 0
T11 0 1 0 0
T12 0 46 0 0
T13 0 45 0 0
T14 1 0 0 0
T42 0 12 0 0
T43 0 1 0 0
T45 0 1 0 0

Line Coverage for Instance : tb.dut.u_d0_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_d0_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T6
11CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT2,T3,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 23314 22809 0 0
selKnown1 3082 2577 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 23314 22809 0 0
T1 10 9 0 0
T2 371 370 0 0
T3 433 432 0 0
T4 5 4 0 0
T5 8 7 0 0
T6 68 67 0 0
T7 1 0 0 0
T8 16 15 0 0
T9 6 5 0 0
T10 1 0 0 0
T11 0 5 0 0
T14 0 7 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 3082 2577 0 0
T2 76 75 0 0
T3 67 66 0 0
T4 1 0 0 0
T5 1 0 0 0
T6 15 14 0 0
T7 1 0 0 0
T8 1 0 0 0
T9 2 1 0 0
T10 1 0 0 0
T11 0 1 0 0
T12 0 46 0 0
T13 0 45 0 0
T14 1 0 0 0
T42 0 12 0 0
T43 0 1 0 0
T45 0 1 0 0

Line Coverage for Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T6
11CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT2,T3,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 23314 22809 0 0
selKnown1 3082 2577 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 23314 22809 0 0
T1 10 9 0 0
T2 371 370 0 0
T3 433 432 0 0
T4 5 4 0 0
T5 8 7 0 0
T6 68 67 0 0
T7 1 0 0 0
T8 16 15 0 0
T9 6 5 0 0
T10 1 0 0 0
T11 0 5 0 0
T14 0 7 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 3082 2577 0 0
T2 76 75 0 0
T3 67 66 0 0
T4 1 0 0 0
T5 1 0 0 0
T6 15 14 0 0
T7 1 0 0 0
T8 1 0 0 0
T9 2 1 0 0
T10 1 0 0 0
T11 0 1 0 0
T12 0 46 0 0
T13 0 45 0 0
T14 1 0 0 0
T42 0 12 0 0
T43 0 1 0 0
T45 0 1 0 0

Line Coverage for Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T6
11CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT2,T3,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 23314 22809 0 0
selKnown1 3082 2577 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 23314 22809 0 0
T1 10 9 0 0
T2 371 370 0 0
T3 433 432 0 0
T4 5 4 0 0
T5 8 7 0 0
T6 68 67 0 0
T7 1 0 0 0
T8 16 15 0 0
T9 6 5 0 0
T10 1 0 0 0
T11 0 5 0 0
T14 0 7 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 3082 2577 0 0
T2 76 75 0 0
T3 67 66 0 0
T4 1 0 0 0
T5 1 0 0 0
T6 15 14 0 0
T7 1 0 0 0
T8 1 0 0 0
T9 2 1 0 0
T10 1 0 0 0
T11 0 1 0 0
T12 0 46 0 0
T13 0 45 0 0
T14 1 0 0 0
T42 0 12 0 0
T43 0 1 0 0
T45 0 1 0 0

Line Coverage for Instance : tb.dut.u_daon_lc_usb.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_daon_lc_usb.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T6
11CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT2,T3,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_daon_lc_usb.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 23314 22809 0 0
selKnown1 3082 2577 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 23314 22809 0 0
T1 10 9 0 0
T2 371 370 0 0
T3 433 432 0 0
T4 5 4 0 0
T5 8 7 0 0
T6 68 67 0 0
T7 1 0 0 0
T8 16 15 0 0
T9 6 5 0 0
T10 1 0 0 0
T11 0 5 0 0
T14 0 7 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 3082 2577 0 0
T2 76 75 0 0
T3 67 66 0 0
T4 1 0 0 0
T5 1 0 0 0
T6 15 14 0 0
T7 1 0 0 0
T8 1 0 0 0
T9 2 1 0 0
T10 1 0 0 0
T11 0 1 0 0
T12 0 46 0 0
T13 0 45 0 0
T14 1 0 0 0
T42 0 12 0 0
T43 0 1 0 0
T45 0 1 0 0

Line Coverage for Instance : tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T6
11CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT2,T3,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 23364 22859 0 0
selKnown1 3082 2577 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 23364 22859 0 0
T1 10 9 0 0
T2 371 370 0 0
T3 433 432 0 0
T4 5 4 0 0
T5 9 8 0 0
T6 68 67 0 0
T7 1 0 0 0
T8 16 15 0 0
T9 6 5 0 0
T10 1 0 0 0
T11 0 5 0 0
T14 0 8 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 3082 2577 0 0
T2 76 75 0 0
T3 67 66 0 0
T4 1 0 0 0
T5 1 0 0 0
T6 15 14 0 0
T7 1 0 0 0
T8 1 0 0 0
T9 2 1 0 0
T10 1 0 0 0
T11 0 1 0 0
T12 0 46 0 0
T13 0 45 0 0
T14 1 0 0 0
T42 0 12 0 0
T43 0 1 0 0
T45 0 1 0 0

Line Coverage for Instance : tb.dut.u_d0_lc_usb.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_d0_lc_usb.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T6
11CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT2,T3,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_lc_usb.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 23314 22809 0 0
selKnown1 3082 2577 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 23314 22809 0 0
T1 10 9 0 0
T2 371 370 0 0
T3 433 432 0 0
T4 5 4 0 0
T5 8 7 0 0
T6 68 67 0 0
T7 1 0 0 0
T8 16 15 0 0
T9 6 5 0 0
T10 1 0 0 0
T11 0 5 0 0
T14 0 7 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 3082 2577 0 0
T2 76 75 0 0
T3 67 66 0 0
T4 1 0 0 0
T5 1 0 0 0
T6 15 14 0 0
T7 1 0 0 0
T8 1 0 0 0
T9 2 1 0 0
T10 1 0 0 0
T11 0 1 0 0
T12 0 46 0 0
T13 0 45 0 0
T14 1 0 0 0
T42 0 12 0 0
T43 0 1 0 0
T45 0 1 0 0

Line Coverage for Instance : tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T6
11CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT2,T3,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 23364 22859 0 0
selKnown1 3082 2577 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 23364 22859 0 0
T1 10 9 0 0
T2 371 370 0 0
T3 433 432 0 0
T4 5 4 0 0
T5 9 8 0 0
T6 68 67 0 0
T7 1 0 0 0
T8 16 15 0 0
T9 6 5 0 0
T10 1 0 0 0
T11 0 5 0 0
T14 0 8 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 3082 2577 0 0
T2 76 75 0 0
T3 67 66 0 0
T4 1 0 0 0
T5 1 0 0 0
T6 15 14 0 0
T7 1 0 0 0
T8 1 0 0 0
T9 2 1 0 0
T10 1 0 0 0
T11 0 1 0 0
T12 0 46 0 0
T13 0 45 0 0
T14 1 0 0 0
T42 0 12 0 0
T43 0 1 0 0
T45 0 1 0 0

Line Coverage for Instance : tb.dut.u_d0_sys.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_d0_sys.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T6
11CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT2,T3,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_sys.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 23314 22809 0 0
selKnown1 3082 2577 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 23314 22809 0 0
T1 10 9 0 0
T2 371 370 0 0
T3 433 432 0 0
T4 5 4 0 0
T5 8 7 0 0
T6 68 67 0 0
T7 1 0 0 0
T8 16 15 0 0
T9 6 5 0 0
T10 1 0 0 0
T11 0 5 0 0
T14 0 7 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 3082 2577 0 0
T2 76 75 0 0
T3 67 66 0 0
T4 1 0 0 0
T5 1 0 0 0
T6 15 14 0 0
T7 1 0 0 0
T8 1 0 0 0
T9 2 1 0 0
T10 1 0 0 0
T11 0 1 0 0
T12 0 46 0 0
T13 0 45 0 0
T14 1 0 0 0
T42 0 12 0 0
T43 0 1 0 0
T45 0 1 0 0

Line Coverage for Instance : tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T6
11CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT2,T3,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 23364 22859 0 0
selKnown1 3082 2577 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 23364 22859 0 0
T1 10 9 0 0
T2 371 370 0 0
T3 433 432 0 0
T4 5 4 0 0
T5 9 8 0 0
T6 68 67 0 0
T7 1 0 0 0
T8 16 15 0 0
T9 6 5 0 0
T10 1 0 0 0
T11 0 5 0 0
T14 0 8 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 3082 2577 0 0
T2 76 75 0 0
T3 67 66 0 0
T4 1 0 0 0
T5 1 0 0 0
T6 15 14 0 0
T7 1 0 0 0
T8 1 0 0 0
T9 2 1 0 0
T10 1 0 0 0
T11 0 1 0 0
T12 0 46 0 0
T13 0 45 0 0
T14 1 0 0 0
T42 0 12 0 0
T43 0 1 0 0
T45 0 1 0 0

Line Coverage for Instance : tb.dut.u_daon_sys_io_div4.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_daon_sys_io_div4.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T6
11CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT2,T3,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_daon_sys_io_div4.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 23314 22809 0 0
selKnown1 3082 2577 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 23314 22809 0 0
T1 10 9 0 0
T2 371 370 0 0
T3 433 432 0 0
T4 5 4 0 0
T5 8 7 0 0
T6 68 67 0 0
T7 1 0 0 0
T8 16 15 0 0
T9 6 5 0 0
T10 1 0 0 0
T11 0 5 0 0
T14 0 7 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 3082 2577 0 0
T2 76 75 0 0
T3 67 66 0 0
T4 1 0 0 0
T5 1 0 0 0
T6 15 14 0 0
T7 1 0 0 0
T8 1 0 0 0
T9 2 1 0 0
T10 1 0 0 0
T11 0 1 0 0
T12 0 46 0 0
T13 0 45 0 0
T14 1 0 0 0
T42 0 12 0 0
T43 0 1 0 0
T45 0 1 0 0

Line Coverage for Instance : tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T6
11CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT2,T3,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 23364 22859 0 0
selKnown1 3082 2577 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 23364 22859 0 0
T1 10 9 0 0
T2 371 370 0 0
T3 433 432 0 0
T4 5 4 0 0
T5 9 8 0 0
T6 68 67 0 0
T7 1 0 0 0
T8 16 15 0 0
T9 6 5 0 0
T10 1 0 0 0
T11 0 5 0 0
T14 0 8 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 3082 2577 0 0
T2 76 75 0 0
T3 67 66 0 0
T4 1 0 0 0
T5 1 0 0 0
T6 15 14 0 0
T7 1 0 0 0
T8 1 0 0 0
T9 2 1 0 0
T10 1 0 0 0
T11 0 1 0 0
T12 0 46 0 0
T13 0 45 0 0
T14 1 0 0 0
T42 0 12 0 0
T43 0 1 0 0
T45 0 1 0 0

Line Coverage for Instance : tb.dut.u_d0_spi_device.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_d0_spi_device.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T6
11CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT2,T3,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_spi_device.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 24288 23783 0 0
selKnown1 3082 2577 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 24288 23783 0 0
T1 10 9 0 0
T2 383 382 0 0
T3 447 446 0 0
T4 5 4 0 0
T5 8 7 0 0
T6 71 70 0 0
T7 1 0 0 0
T8 16 15 0 0
T9 6 5 0 0
T10 8 7 0 0
T14 0 7 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 3082 2577 0 0
T2 76 75 0 0
T3 67 66 0 0
T4 1 0 0 0
T5 1 0 0 0
T6 15 14 0 0
T7 1 0 0 0
T8 1 0 0 0
T9 2 1 0 0
T10 1 0 0 0
T11 0 1 0 0
T12 0 46 0 0
T13 0 45 0 0
T14 1 0 0 0
T42 0 12 0 0
T43 0 1 0 0
T45 0 1 0 0

Line Coverage for Instance : tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T6
11CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT2,T3,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 23364 22859 0 0
selKnown1 3082 2577 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 23364 22859 0 0
T1 10 9 0 0
T2 371 370 0 0
T3 433 432 0 0
T4 5 4 0 0
T5 9 8 0 0
T6 68 67 0 0
T7 1 0 0 0
T8 16 15 0 0
T9 6 5 0 0
T10 1 0 0 0
T11 0 5 0 0
T14 0 8 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 3082 2577 0 0
T2 76 75 0 0
T3 67 66 0 0
T4 1 0 0 0
T5 1 0 0 0
T6 15 14 0 0
T7 1 0 0 0
T8 1 0 0 0
T9 2 1 0 0
T10 1 0 0 0
T11 0 1 0 0
T12 0 46 0 0
T13 0 45 0 0
T14 1 0 0 0
T42 0 12 0 0
T43 0 1 0 0
T45 0 1 0 0

Line Coverage for Instance : tb.dut.u_d0_spi_host0.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_d0_spi_host0.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T6
11CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT2,T3,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_spi_host0.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 24357 23852 0 0
selKnown1 3082 2577 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 24357 23852 0 0
T1 10 9 0 0
T2 382 381 0 0
T3 444 443 0 0
T4 5 4 0 0
T5 8 7 0 0
T6 73 72 0 0
T7 1 0 0 0
T8 16 15 0 0
T9 6 5 0 0
T10 9 8 0 0
T14 0 7 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 3082 2577 0 0
T2 76 75 0 0
T3 67 66 0 0
T4 1 0 0 0
T5 1 0 0 0
T6 15 14 0 0
T7 1 0 0 0
T8 1 0 0 0
T9 2 1 0 0
T10 1 0 0 0
T11 0 1 0 0
T12 0 46 0 0
T13 0 45 0 0
T14 1 0 0 0
T42 0 12 0 0
T43 0 1 0 0
T45 0 1 0 0

Line Coverage for Instance : tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T6
11CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT2,T3,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 23364 22859 0 0
selKnown1 3082 2577 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 23364 22859 0 0
T1 10 9 0 0
T2 371 370 0 0
T3 433 432 0 0
T4 5 4 0 0
T5 9 8 0 0
T6 68 67 0 0
T7 1 0 0 0
T8 16 15 0 0
T9 6 5 0 0
T10 1 0 0 0
T11 0 5 0 0
T14 0 8 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 3082 2577 0 0
T2 76 75 0 0
T3 67 66 0 0
T4 1 0 0 0
T5 1 0 0 0
T6 15 14 0 0
T7 1 0 0 0
T8 1 0 0 0
T9 2 1 0 0
T10 1 0 0 0
T11 0 1 0 0
T12 0 46 0 0
T13 0 45 0 0
T14 1 0 0 0
T42 0 12 0 0
T43 0 1 0 0
T45 0 1 0 0

Line Coverage for Instance : tb.dut.u_d0_spi_host1.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_d0_spi_host1.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T6
11CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT2,T3,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_spi_host1.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 24395 23890 0 0
selKnown1 3082 2577 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 24395 23890 0 0
T1 10 9 0 0
T2 381 380 0 0
T3 443 442 0 0
T4 5 4 0 0
T5 8 7 0 0
T6 70 69 0 0
T7 1 0 0 0
T8 16 15 0 0
T9 6 5 0 0
T10 9 8 0 0
T14 0 7 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 3082 2577 0 0
T2 76 75 0 0
T3 67 66 0 0
T4 1 0 0 0
T5 1 0 0 0
T6 15 14 0 0
T7 1 0 0 0
T8 1 0 0 0
T9 2 1 0 0
T10 1 0 0 0
T11 0 1 0 0
T12 0 46 0 0
T13 0 45 0 0
T14 1 0 0 0
T42 0 12 0 0
T43 0 1 0 0
T45 0 1 0 0

Line Coverage for Instance : tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T6
11CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT2,T3,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 23364 22859 0 0
selKnown1 3082 2577 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 23364 22859 0 0
T1 10 9 0 0
T2 371 370 0 0
T3 433 432 0 0
T4 5 4 0 0
T5 9 8 0 0
T6 68 67 0 0
T7 1 0 0 0
T8 16 15 0 0
T9 6 5 0 0
T10 1 0 0 0
T11 0 5 0 0
T14 0 8 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 3082 2577 0 0
T2 76 75 0 0
T3 67 66 0 0
T4 1 0 0 0
T5 1 0 0 0
T6 15 14 0 0
T7 1 0 0 0
T8 1 0 0 0
T9 2 1 0 0
T10 1 0 0 0
T11 0 1 0 0
T12 0 46 0 0
T13 0 45 0 0
T14 1 0 0 0
T42 0 12 0 0
T43 0 1 0 0
T45 0 1 0 0

Line Coverage for Instance : tb.dut.u_d0_usb.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_d0_usb.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T6
11CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT2,T3,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_usb.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 24465 23960 0 0
selKnown1 3082 2577 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 24465 23960 0 0
T1 10 9 0 0
T2 382 381 0 0
T3 445 444 0 0
T4 5 4 0 0
T5 8 7 0 0
T6 71 70 0 0
T7 1 0 0 0
T8 16 15 0 0
T9 7 6 0 0
T10 9 8 0 0
T14 0 7 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 3082 2577 0 0
T2 76 75 0 0
T3 67 66 0 0
T4 1 0 0 0
T5 1 0 0 0
T6 15 14 0 0
T7 1 0 0 0
T8 1 0 0 0
T9 2 1 0 0
T10 1 0 0 0
T11 0 1 0 0
T12 0 46 0 0
T13 0 45 0 0
T14 1 0 0 0
T42 0 12 0 0
T43 0 1 0 0
T45 0 1 0 0

Line Coverage for Instance : tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T6
11CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT2,T3,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 23364 22859 0 0
selKnown1 3082 2577 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 23364 22859 0 0
T1 10 9 0 0
T2 371 370 0 0
T3 433 432 0 0
T4 5 4 0 0
T5 9 8 0 0
T6 68 67 0 0
T7 1 0 0 0
T8 16 15 0 0
T9 6 5 0 0
T10 1 0 0 0
T11 0 5 0 0
T14 0 8 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 3082 2577 0 0
T2 76 75 0 0
T3 67 66 0 0
T4 1 0 0 0
T5 1 0 0 0
T6 15 14 0 0
T7 1 0 0 0
T8 1 0 0 0
T9 2 1 0 0
T10 1 0 0 0
T11 0 1 0 0
T12 0 46 0 0
T13 0 45 0 0
T14 1 0 0 0
T42 0 12 0 0
T43 0 1 0 0
T45 0 1 0 0

Line Coverage for Instance : tb.dut.u_d0_usb_aon.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_d0_usb_aon.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T6
11CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT2,T3,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_usb_aon.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 24500 23995 0 0
selKnown1 3082 2577 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 24500 23995 0 0
T1 10 9 0 0
T2 379 378 0 0
T3 445 444 0 0
T4 5 4 0 0
T5 8 7 0 0
T6 71 70 0 0
T7 1 0 0 0
T8 16 15 0 0
T9 6 5 0 0
T10 11 10 0 0
T14 0 7 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 3082 2577 0 0
T2 76 75 0 0
T3 67 66 0 0
T4 1 0 0 0
T5 1 0 0 0
T6 15 14 0 0
T7 1 0 0 0
T8 1 0 0 0
T9 2 1 0 0
T10 1 0 0 0
T11 0 1 0 0
T12 0 46 0 0
T13 0 45 0 0
T14 1 0 0 0
T42 0 12 0 0
T43 0 1 0 0
T45 0 1 0 0

Line Coverage for Instance : tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T6
11CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT2,T3,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 23248 22743 0 0
selKnown1 3082 2577 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 23248 22743 0 0
T1 10 9 0 0
T2 371 370 0 0
T3 433 432 0 0
T4 5 4 0 0
T5 7 6 0 0
T6 67 66 0 0
T7 1 0 0 0
T8 16 15 0 0
T9 6 5 0 0
T10 1 0 0 0
T11 0 5 0 0
T14 0 6 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 3082 2577 0 0
T2 76 75 0 0
T3 67 66 0 0
T4 1 0 0 0
T5 1 0 0 0
T6 15 14 0 0
T7 1 0 0 0
T8 1 0 0 0
T9 2 1 0 0
T10 1 0 0 0
T11 0 1 0 0
T12 0 46 0 0
T13 0 45 0 0
T14 1 0 0 0
T42 0 12 0 0
T43 0 1 0 0
T45 0 1 0 0

Line Coverage for Instance : tb.dut.u_d0_i2c0.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_d0_i2c0.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T6
11CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT2,T3,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_i2c0.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 24544 24039 0 0
selKnown1 3082 2577 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 24544 24039 0 0
T1 10 9 0 0
T2 383 382 0 0
T3 443 442 0 0
T4 5 4 0 0
T5 8 7 0 0
T6 73 72 0 0
T7 1 0 0 0
T8 16 15 0 0
T9 6 5 0 0
T10 11 10 0 0
T14 0 7 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 3082 2577 0 0
T2 76 75 0 0
T3 67 66 0 0
T4 1 0 0 0
T5 1 0 0 0
T6 15 14 0 0
T7 1 0 0 0
T8 1 0 0 0
T9 2 1 0 0
T10 1 0 0 0
T11 0 1 0 0
T12 0 46 0 0
T13 0 45 0 0
T14 1 0 0 0
T42 0 12 0 0
T43 0 1 0 0
T45 0 1 0 0

Line Coverage for Instance : tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T6
11CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT2,T3,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 23364 22859 0 0
selKnown1 3082 2577 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 23364 22859 0 0
T1 10 9 0 0
T2 371 370 0 0
T3 433 432 0 0
T4 5 4 0 0
T5 9 8 0 0
T6 68 67 0 0
T7 1 0 0 0
T8 16 15 0 0
T9 6 5 0 0
T10 1 0 0 0
T11 0 5 0 0
T14 0 8 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 3082 2577 0 0
T2 76 75 0 0
T3 67 66 0 0
T4 1 0 0 0
T5 1 0 0 0
T6 15 14 0 0
T7 1 0 0 0
T8 1 0 0 0
T9 2 1 0 0
T10 1 0 0 0
T11 0 1 0 0
T12 0 46 0 0
T13 0 45 0 0
T14 1 0 0 0
T42 0 12 0 0
T43 0 1 0 0
T45 0 1 0 0

Line Coverage for Instance : tb.dut.u_d0_i2c1.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_d0_i2c1.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T6
11CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT2,T3,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_i2c1.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 24614 24109 0 0
selKnown1 3082 2577 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 24614 24109 0 0
T1 10 9 0 0
T2 383 382 0 0
T3 446 445 0 0
T4 5 4 0 0
T5 8 7 0 0
T6 71 70 0 0
T7 1 0 0 0
T8 16 15 0 0
T9 6 5 0 0
T10 11 10 0 0
T14 0 7 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 3082 2577 0 0
T2 76 75 0 0
T3 67 66 0 0
T4 1 0 0 0
T5 1 0 0 0
T6 15 14 0 0
T7 1 0 0 0
T8 1 0 0 0
T9 2 1 0 0
T10 1 0 0 0
T11 0 1 0 0
T12 0 46 0 0
T13 0 45 0 0
T14 1 0 0 0
T42 0 12 0 0
T43 0 1 0 0
T45 0 1 0 0

Line Coverage for Instance : tb.dut.u_d0_i2c1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_d0_i2c1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T6
11CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT2,T3,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_i2c1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 23364 22859 0 0
selKnown1 3082 2577 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 23364 22859 0 0
T1 10 9 0 0
T2 371 370 0 0
T3 433 432 0 0
T4 5 4 0 0
T5 9 8 0 0
T6 68 67 0 0
T7 1 0 0 0
T8 16 15 0 0
T9 6 5 0 0
T10 1 0 0 0
T11 0 5 0 0
T14 0 8 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 3082 2577 0 0
T2 76 75 0 0
T3 67 66 0 0
T4 1 0 0 0
T5 1 0 0 0
T6 15 14 0 0
T7 1 0 0 0
T8 1 0 0 0
T9 2 1 0 0
T10 1 0 0 0
T11 0 1 0 0
T12 0 46 0 0
T13 0 45 0 0
T14 1 0 0 0
T42 0 12 0 0
T43 0 1 0 0
T45 0 1 0 0

Line Coverage for Instance : tb.dut.u_d0_i2c2.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_d0_i2c2.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T6
11CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT2,T3,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_i2c2.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 24656 24151 0 0
selKnown1 3082 2577 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 24656 24151 0 0
T1 10 9 0 0
T2 380 379 0 0
T3 443 442 0 0
T4 5 4 0 0
T5 8 7 0 0
T6 71 70 0 0
T7 1 0 0 0
T8 16 15 0 0
T9 6 5 0 0
T10 14 13 0 0
T14 0 7 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 3082 2577 0 0
T2 76 75 0 0
T3 67 66 0 0
T4 1 0 0 0
T5 1 0 0 0
T6 15 14 0 0
T7 1 0 0 0
T8 1 0 0 0
T9 2 1 0 0
T10 1 0 0 0
T11 0 1 0 0
T12 0 46 0 0
T13 0 45 0 0
T14 1 0 0 0
T42 0 12 0 0
T43 0 1 0 0
T45 0 1 0 0

Line Coverage for Instance : tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T6
11CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT2,T3,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 23364 22859 0 0
selKnown1 3082 2577 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 23364 22859 0 0
T1 10 9 0 0
T2 371 370 0 0
T3 433 432 0 0
T4 5 4 0 0
T5 9 8 0 0
T6 68 67 0 0
T7 1 0 0 0
T8 16 15 0 0
T9 6 5 0 0
T10 1 0 0 0
T11 0 5 0 0
T14 0 8 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 3082 2577 0 0
T2 76 75 0 0
T3 67 66 0 0
T4 1 0 0 0
T5 1 0 0 0
T6 15 14 0 0
T7 1 0 0 0
T8 1 0 0 0
T9 2 1 0 0
T10 1 0 0 0
T11 0 1 0 0
T12 0 46 0 0
T13 0 45 0 0
T14 1 0 0 0
T42 0 12 0 0
T43 0 1 0 0
T45 0 1 0 0

Line Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_root_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_root_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T6
11CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT2,T3,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_root_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 6884 6379 0 0
selKnown1 3082 2577 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 6884 6379 0 0
T2 66 65 0 0
T3 79 78 0 0
T4 1 0 0 0
T5 8 7 0 0
T6 11 10 0 0
T7 1 0 0 0
T8 1 0 0 0
T9 1 0 0 0
T10 1 0 0 0
T12 0 47 0 0
T13 0 45 0 0
T14 8 7 0 0
T70 0 7 0 0
T84 0 7 0 0
T85 0 7 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 3082 2577 0 0
T2 76 75 0 0
T3 67 66 0 0
T4 1 0 0 0
T5 1 0 0 0
T6 15 14 0 0
T7 1 0 0 0
T8 1 0 0 0
T9 2 1 0 0
T10 1 0 0 0
T11 0 1 0 0
T12 0 46 0 0
T13 0 45 0 0
T14 1 0 0 0
T42 0 12 0 0
T43 0 1 0 0
T45 0 1 0 0

Line Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_clean_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_clean_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T6
11CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT2,T3,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_clean_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 9421 8916 0 0
selKnown1 3082 2577 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 9421 8916 0 0
T2 141 140 0 0
T3 145 144 0 0
T4 1 0 0 0
T5 8 7 0 0
T6 25 24 0 0
T7 1 0 0 0
T8 1 0 0 0
T9 2 1 0 0
T10 1 0 0 0
T11 0 1 0 0
T12 0 93 0 0
T13 0 90 0 0
T14 8 7 0 0
T70 0 7 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 3082 2577 0 0
T2 76 75 0 0
T3 67 66 0 0
T4 1 0 0 0
T5 1 0 0 0
T6 15 14 0 0
T7 1 0 0 0
T8 1 0 0 0
T9 2 1 0 0
T10 1 0 0 0
T11 0 1 0 0
T12 0 46 0 0
T13 0 45 0 0
T14 1 0 0 0
T42 0 12 0 0
T43 0 1 0 0
T45 0 1 0 0

Line Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_out_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_out_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T6
11CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT2,T3,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_out_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 8967 8462 0 0
selKnown1 3082 2577 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 8967 8462 0 0
T2 141 140 0 0
T3 145 144 0 0
T4 1 0 0 0
T5 8 7 0 0
T6 25 24 0 0
T7 1 0 0 0
T8 1 0 0 0
T9 2 1 0 0
T10 1 0 0 0
T11 0 1 0 0
T12 0 93 0 0
T13 0 90 0 0
T14 8 7 0 0
T70 0 7 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 3082 2577 0 0
T2 76 75 0 0
T3 67 66 0 0
T4 1 0 0 0
T5 1 0 0 0
T6 15 14 0 0
T7 1 0 0 0
T8 1 0 0 0
T9 2 1 0 0
T10 1 0 0 0
T11 0 1 0 0
T12 0 46 0 0
T13 0 45 0 0
T14 1 0 0 0
T42 0 12 0 0
T43 0 1 0 0
T45 0 1 0 0

Line Coverage for Instance : tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T6
11CoveredT2,T3,T6

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT2,T3,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 8967 8462 0 0
selKnown1 3082 2577 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 8967 8462 0 0
T2 141 140 0 0
T3 145 144 0 0
T4 1 0 0 0
T5 8 7 0 0
T6 25 24 0 0
T7 1 0 0 0
T8 1 0 0 0
T9 2 1 0 0
T10 1 0 0 0
T11 0 1 0 0
T12 0 93 0 0
T13 0 90 0 0
T14 8 7 0 0
T70 0 7 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 3082 2577 0 0
T2 76 75 0 0
T3 67 66 0 0
T4 1 0 0 0
T5 1 0 0 0
T6 15 14 0 0
T7 1 0 0 0
T8 1 0 0 0
T9 2 1 0 0
T10 1 0 0 0
T11 0 1 0 0
T12 0 46 0 0
T13 0 45 0 0
T14 1 0 0 0
T42 0 12 0 0
T43 0 1 0 0
T45 0 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%