Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	13426987	15321	0	0
gen_assertions[0].RstEnOn_A	13426987	1149	0	0
gen_assertions[0].RstNOff_A	13426987	15321	0	0
gen_assertions[0].RstNOn_A	13426987	1149	0	0
gen_assertions[1].RstEnOff_A	53707812	13926	0	0
gen_assertions[1].RstEnOn_A	53707812	1126	0	0
gen_assertions[1].RstNOff_A	53707812	13926	0	0
gen_assertions[1].RstNOn_A	53707812	1126	0	0
gen_assertions[2].RstEnOff_A	26854629	13964	0	0
gen_assertions[2].RstEnOn_A	26854629	1128	0	0
gen_assertions[2].RstNOff_A	26854629	13964	0	0
gen_assertions[2].RstNOn_A	26854629	1128	0	0
gen_assertions[3].RstEnOff_A	26854640	14034	0	0
gen_assertions[3].RstEnOn_A	26854640	1191	0	0
gen_assertions[3].RstNOff_A	26854640	14034	0	0
gen_assertions[3].RstNOn_A	26854640	1191	0	0
gen_assertions[4].RstEnOff_A	1697868	23123	0	0
gen_assertions[4].RstEnOn_A	1697868	1243	0	0
gen_assertions[4].RstNOff_A	1697868	23123	0	0
gen_assertions[4].RstNOn_A	1697868	1243	0	0
gen_assertions[5].RstEnOff_A	13426987	15577	0	0
gen_assertions[5].RstEnOn_A	13426987	1274	0	0
gen_assertions[5].RstNOff_A	13426987	15577	0	0
gen_assertions[5].RstNOn_A	13426987	1274	0	0
gen_assertions[6].RstEnOff_A	13426987	15647	0	0
gen_assertions[6].RstEnOn_A	13426987	1342	0	0
gen_assertions[6].RstNOff_A	13426987	15647	0	0
gen_assertions[6].RstNOn_A	13426987	1342	0	0
gen_assertions[7].RstEnOff_A	13426987	15689	0	0
gen_assertions[7].RstEnOn_A	13426987	1386	0	0
gen_assertions[7].RstNOff_A	13426987	15689	0	0
gen_assertions[7].RstNOn_A	13426987	1386	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13426987	15321	0	0
T1	2595	9	0	0
T2	245768	242	0	0
T3	170382	302	0	0
T4	2026	4	0	0
T5	5837	0	0	0
T6	58137	46	0	0
T7	1842	0	0	0
T8	4654	15	0	0
T9	4608	4	0	0
T10	3329	7	0	0
T11	0	4	0	0
T12	0	173	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13426987	1149	0	0
T1	2595	6	0	0
T2	245768	14	0	0
T3	170382	16	0	0
T4	2026	1	0	0
T5	5837	0	0	0
T6	58137	3	0	0
T7	1842	0	0	0
T8	4654	2	0	0
T9	4608	0	0	0
T10	3329	7	0	0
T12	0	1	0	0
T13	0	29	0	0
T62	0	5	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13426987	15321	0	0
T1	2595	9	0	0
T2	245768	242	0	0
T3	170382	302	0	0
T4	2026	4	0	0
T5	5837	0	0	0
T6	58137	46	0	0
T7	1842	0	0	0
T8	4654	15	0	0
T9	4608	4	0	0
T10	3329	7	0	0
T11	0	4	0	0
T12	0	173	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13426987	1149	0	0
T1	2595	6	0	0
T2	245768	14	0	0
T3	170382	16	0	0
T4	2026	1	0	0
T5	5837	0	0	0
T6	58137	3	0	0
T7	1842	0	0	0
T8	4654	2	0	0
T9	4608	0	0	0
T10	3329	7	0	0
T12	0	1	0	0
T13	0	29	0	0
T62	0	5	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53707812	13926	0	0
T1	10388	9	0	0
T2	983065	216	0	0
T3	681589	255	0	0
T4	8113	4	0	0
T5	23362	0	0	0
T6	232559	42	0	0
T7	7370	0	0	0
T8	18619	12	0	0
T9	18444	4	0	0
T10	13325	8	0	0
T11	0	4	0	0
T12	0	154	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53707812	1126	0	0
T1	10388	2	0	0
T2	983065	13	0	0
T3	681589	12	0	0
T4	8113	0	0	0
T5	23362	0	0	0
T6	232559	5	0	0
T7	7370	0	0	0
T8	18619	0	0	0
T9	18444	0	0	0
T10	13325	8	0	0
T12	0	1	0	0
T13	0	28	0	0
T56	0	4	0	0
T58	0	1	0	0
T62	0	8	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53707812	13926	0	0
T1	10388	9	0	0
T2	983065	216	0	0
T3	681589	255	0	0
T4	8113	4	0	0
T5	23362	0	0	0
T6	232559	42	0	0
T7	7370	0	0	0
T8	18619	12	0	0
T9	18444	4	0	0
T10	13325	8	0	0
T11	0	4	0	0
T12	0	154	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53707812	1126	0	0
T1	10388	2	0	0
T2	983065	13	0	0
T3	681589	12	0	0
T4	8113	0	0	0
T5	23362	0	0	0
T6	232559	5	0	0
T7	7370	0	0	0
T8	18619	0	0	0
T9	18444	0	0	0
T10	13325	8	0	0
T12	0	1	0	0
T13	0	28	0	0
T56	0	4	0	0
T58	0	1	0	0
T62	0	8	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26854629	13964	0	0
T1	5193	9	0	0
T2	491510	215	0	0
T3	340771	254	0	0
T4	4056	4	0	0
T5	11682	0	0	0
T6	116278	39	0	0
T7	3683	0	0	0
T8	9309	12	0	0
T9	9219	4	0	0
T10	6661	8	0	0
T11	0	4	0	0
T12	0	154	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26854629	1128	0	0
T2	491510	11	0	0
T3	340771	11	0	0
T4	4056	0	0	0
T5	11682	0	0	0
T6	116278	2	0	0
T7	3683	0	0	0
T8	9309	0	0	0
T9	9219	0	0	0
T10	6661	8	0	0
T12	0	2	0	0
T13	0	21	0	0
T14	11626	0	0	0
T29	0	1	0	0
T45	0	1	0	0
T56	0	4	0	0
T62	0	8	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26854629	13964	0	0
T1	5193	9	0	0
T2	491510	215	0	0
T3	340771	254	0	0
T4	4056	4	0	0
T5	11682	0	0	0
T6	116278	39	0	0
T7	3683	0	0	0
T8	9309	12	0	0
T9	9219	4	0	0
T10	6661	8	0	0
T11	0	4	0	0
T12	0	154	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26854629	1128	0	0
T2	491510	11	0	0
T3	340771	11	0	0
T4	4056	0	0	0
T5	11682	0	0	0
T6	116278	2	0	0
T7	3683	0	0	0
T8	9309	0	0	0
T9	9219	0	0	0
T10	6661	8	0	0
T12	0	2	0	0
T13	0	21	0	0
T14	11626	0	0	0
T29	0	1	0	0
T45	0	1	0	0
T56	0	4	0	0
T62	0	8	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26854640	14034	0	0
T1	5194	9	0	0
T2	491541	216	0	0
T3	340793	256	0	0
T4	4056	4	0	0
T5	11677	0	0	0
T6	116275	40	0	0
T7	3684	0	0	0
T8	9309	12	0	0
T9	9218	5	0	0
T10	6662	8	0	0
T11	0	4	0	0
T12	0	153	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26854640	1191	0	0
T2	491541	13	0	0
T3	340793	13	0	0
T4	4056	0	0	0
T5	11677	0	0	0
T6	116275	3	0	0
T7	3684	0	0	0
T8	9309	0	0	0
T9	9218	1	0	0
T10	6662	8	0	0
T12	0	1	0	0
T13	0	21	0	0
T14	11619	0	0	0
T45	0	1	0	0
T56	0	5	0	0
T62	0	10	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26854640	14034	0	0
T1	5194	9	0	0
T2	491541	216	0	0
T3	340793	256	0	0
T4	4056	4	0	0
T5	11677	0	0	0
T6	116275	40	0	0
T7	3684	0	0	0
T8	9309	12	0	0
T9	9218	5	0	0
T10	6662	8	0	0
T11	0	4	0	0
T12	0	153	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26854640	1191	0	0
T2	491541	13	0	0
T3	340793	13	0	0
T4	4056	0	0	0
T5	11677	0	0	0
T6	116275	3	0	0
T7	3684	0	0	0
T8	9309	0	0	0
T9	9218	1	0	0
T10	6662	8	0	0
T12	0	1	0	0
T13	0	21	0	0
T14	11619	0	0	0
T45	0	1	0	0
T56	0	5	0	0
T62	0	10	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1697868	23123	0	0
T1	323	10	0	0
T2	31144	376	0	0
T3	21779	437	0	0
T4	253	5	0	0
T5	732	3	0	0
T6	7300	70	0	0
T7	229	1	0	0
T8	580	16	0	0
T9	574	6	0	0
T10	415	11	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1697868	1243	0	0
T2	31144	9	0	0
T3	21779	13	0	0
T4	253	0	0	0
T5	732	0	0	0
T6	7300	4	0	0
T7	229	0	0	0
T8	580	0	0	0
T9	574	0	0	0
T10	415	10	0	0
T13	0	26	0	0
T14	729	0	0	0
T56	0	7	0	0
T62	0	10	0	0
T87	0	9	0	0
T88	0	1	0	0
T89	0	1	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1697868	23123	0	0
T1	323	10	0	0
T2	31144	376	0	0
T3	21779	437	0	0
T4	253	5	0	0
T5	732	3	0	0
T6	7300	70	0	0
T7	229	1	0	0
T8	580	16	0	0
T9	574	6	0	0
T10	415	11	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1697868	1243	0	0
T2	31144	9	0	0
T3	21779	13	0	0
T4	253	0	0	0
T5	732	0	0	0
T6	7300	4	0	0
T7	229	0	0	0
T8	580	0	0	0
T9	574	0	0	0
T10	415	10	0	0
T13	0	26	0	0
T14	729	0	0	0
T56	0	7	0	0
T62	0	10	0	0
T87	0	9	0	0
T88	0	1	0	0
T89	0	1	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13426987	15577	0	0
T1	2595	9	0	0
T2	245768	242	0	0
T3	170382	298	0	0
T4	2026	4	0	0
T5	5837	0	0	0
T6	58137	48	0	0
T7	1842	0	0	0
T8	4654	15	0	0
T9	4608	4	0	0
T10	3329	10	0	0
T11	0	4	0	0
T12	0	173	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13426987	1274	0	0
T2	245768	14	0	0
T3	170382	12	0	0
T4	2026	0	0	0
T5	5837	0	0	0
T6	58137	5	0	0
T7	1842	0	0	0
T8	4654	0	0	0
T9	4608	0	0	0
T10	3329	10	0	0
T12	0	2	0	0
T13	0	26	0	0
T14	5807	0	0	0
T56	0	8	0	0
T58	0	1	0	0
T62	0	10	0	0
T87	0	8	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13426987	15577	0	0
T1	2595	9	0	0
T2	245768	242	0	0
T3	170382	298	0	0
T4	2026	4	0	0
T5	5837	0	0	0
T6	58137	48	0	0
T7	1842	0	0	0
T8	4654	15	0	0
T9	4608	4	0	0
T10	3329	10	0	0
T11	0	4	0	0
T12	0	173	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13426987	1274	0	0
T2	245768	14	0	0
T3	170382	12	0	0
T4	2026	0	0	0
T5	5837	0	0	0
T6	58137	5	0	0
T7	1842	0	0	0
T8	4654	0	0	0
T9	4608	0	0	0
T10	3329	10	0	0
T12	0	2	0	0
T13	0	26	0	0
T14	5807	0	0	0
T56	0	8	0	0
T58	0	1	0	0
T62	0	10	0	0
T87	0	8	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13426987	15647	0	0
T1	2595	9	0	0
T2	245768	242	0	0
T3	170382	301	0	0
T4	2026	4	0	0
T5	5837	0	0	0
T6	58137	46	0	0
T7	1842	0	0	0
T8	4654	15	0	0
T9	4608	4	0	0
T10	3329	10	0	0
T11	0	4	0	0
T12	0	173	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13426987	1342	0	0
T2	245768	12	0	0
T3	170382	15	0	0
T4	2026	0	0	0
T5	5837	0	0	0
T6	58137	3	0	0
T7	1842	0	0	0
T8	4654	0	0	0
T9	4608	0	0	0
T10	3329	10	0	0
T12	0	2	0	0
T13	0	27	0	0
T14	5807	0	0	0
T29	0	1	0	0
T56	0	10	0	0
T62	0	11	0	0
T87	0	10	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13426987	15647	0	0
T1	2595	9	0	0
T2	245768	242	0	0
T3	170382	301	0	0
T4	2026	4	0	0
T5	5837	0	0	0
T6	58137	46	0	0
T7	1842	0	0	0
T8	4654	15	0	0
T9	4608	4	0	0
T10	3329	10	0	0
T11	0	4	0	0
T12	0	173	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13426987	1342	0	0
T2	245768	12	0	0
T3	170382	15	0	0
T4	2026	0	0	0
T5	5837	0	0	0
T6	58137	3	0	0
T7	1842	0	0	0
T8	4654	0	0	0
T9	4608	0	0	0
T10	3329	10	0	0
T12	0	2	0	0
T13	0	27	0	0
T14	5807	0	0	0
T29	0	1	0	0
T56	0	10	0	0
T62	0	11	0	0
T87	0	10	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13426987	15689	0	0
T1	2595	9	0	0
T2	245768	239	0	0
T3	170382	298	0	0
T4	2026	4	0	0
T5	5837	0	0	0
T6	58137	46	0	0
T7	1842	0	0	0
T8	4654	15	0	0
T9	4608	4	0	0
T10	3329	13	0	0
T11	0	4	0	0
T12	0	172	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13426987	1386	0	0
T2	245768	11	0	0
T3	170382	11	0	0
T4	2026	0	0	0
T5	5837	0	0	0
T6	58137	3	0	0
T7	1842	0	0	0
T8	4654	0	0	0
T9	4608	0	0	0
T10	3329	13	0	0
T12	0	2	0	0
T13	0	23	0	0
T14	5807	0	0	0
T56	0	11	0	0
T62	0	13	0	0
T87	0	12	0	0
T90	0	11	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13426987	15689	0	0
T1	2595	9	0	0
T2	245768	239	0	0
T3	170382	298	0	0
T4	2026	4	0	0
T5	5837	0	0	0
T6	58137	46	0	0
T7	1842	0	0	0
T8	4654	15	0	0
T9	4608	4	0	0
T10	3329	13	0	0
T11	0	4	0	0
T12	0	172	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13426987	1386	0	0
T2	245768	11	0	0
T3	170382	11	0	0
T4	2026	0	0	0
T5	5837	0	0	0
T6	58137	3	0	0
T7	1842	0	0	0
T8	4654	0	0	0
T9	4608	0	0	0
T10	3329	13	0	0
T12	0	2	0	0
T13	0	23	0	0
T14	5807	0	0	0
T56	0	11	0	0
T62	0	13	0	0
T87	0	12	0	0
T90	0	11	0	0