Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_mubi4_sender
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_daon_por.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_daon_por_io.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_daon_por_io_div2.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_daon_por_io_div4.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_daon_por_usb.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_daon_lc.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_d0_lc.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_daon_lc_shadowed.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_d0_lc_shadowed.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_daon_lc_aon.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_daon_lc_io.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_d0_lc_io.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_daon_lc_io_div2.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_d0_lc_io_div2.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_daon_lc_io_div4.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_d0_lc_io_div4.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_daon_lc_io_div4_shadowed.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_d0_lc_io_div4_shadowed.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_daon_lc_usb.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_d0_lc_usb.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_d0_sys.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_daon_sys_io_div4.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_d0_spi_device.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_d0_spi_host0.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_d0_spi_host1.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_d0_usb.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_d0_usb_aon.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_d0_i2c0.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_d0_i2c1.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_d0_i2c2.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_prim_mubi4_sender 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_por.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_por


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_por_io.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_por_io


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_por_io_div2.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_por_io_div2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_por_io_div4.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_por_io_div4


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_por_usb.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_por_usb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_lc.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_lc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_lc.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_d0_lc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_lc_shadowed.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_lc_shadowed


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_lc_shadowed.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_d0_lc_shadowed


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_lc_aon.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_lc_aon


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_lc_io.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_lc_io


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_lc_io.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_d0_lc_io


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_lc_io_div2.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_lc_io_div2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_lc_io_div2.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_d0_lc_io_div2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_lc_io_div4.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_daon_lc_io_div4


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_lc_io_div4.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_d0_lc_io_div4


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_daon_lc_io_div4_shadowed


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_d0_lc_io_div4_shadowed


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_lc_usb.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_lc_usb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_lc_usb.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_d0_lc_usb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_sys.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_d0_sys


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_sys_io_div4.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_sys_io_div4


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_spi_device.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.67 100.00 90.00 100.00 u_d0_spi_device


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_spi_host0.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.67 100.00 90.00 100.00 u_d0_spi_host0


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_spi_host1.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.67 100.00 90.00 100.00 u_d0_spi_host1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_usb.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.67 100.00 90.00 100.00 u_d0_usb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_usb_aon.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_d0_usb_aon


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_i2c0.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.67 100.00 90.00 100.00 u_d0_i2c0


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_i2c1.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.67 100.00 90.00 100.00 u_d0_i2c1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_i2c2.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.67 100.00 90.00 100.00 u_d0_i2c2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.55 100.00 98.21 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.55 100.00 98.21 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00

Line Coverage for Module : prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Module : prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 906413556 493107671 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 906413556 493107671 0 0
T1 175274 95599 0 0
T2 11061090 10607763 0 0
T3 11503368 4903574 0 0
T4 136878 73549 0 0
T5 394174 41350 0 0
T6 3924470 2827102 0 0
T7 124346 79896 0 0
T8 314178 210500 0 0
T9 311154 239384 0 0
T10 224822 176828 0 0

Line Coverage for Instance : tb.dut.u_daon_por.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_daon_por.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 55947315 34259557 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55947315 34259557 0 0
T1 10822 8112 0 0
T2 102395 724111 0 0
T3 709970 390830 0 0
T4 8451 5771 0 0
T5 24332 2879 0 0
T6 242242 190398 0 0
T7 7677 4971 0 0
T8 19395 16675 0 0
T9 19209 15195 0 0
T10 13880 11168 0 0

Line Coverage for Instance : tb.dut.u_daon_por_io.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_daon_por_io.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 53707812 32887321 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 53707812 32887321 0 0
T1 10388 7787 0 0
T2 983065 695147 0 0
T3 681589 375200 0 0
T4 8113 5540 0 0
T5 23362 2763 0 0
T6 232559 182789 0 0
T7 7370 4772 0 0
T8 18619 16007 0 0
T9 18444 14589 0 0
T10 13325 10722 0 0

Line Coverage for Instance : tb.dut.u_daon_por_io_div2.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_daon_por_io_div2.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 26854629 16440033 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26854629 16440033 0 0
T1 5193 3893 0 0
T2 491510 347503 0 0
T3 340771 187501 0 0
T4 4056 2770 0 0
T5 11682 1376 0 0
T6 116278 91379 0 0
T7 3683 2385 0 0
T8 9309 8003 0 0
T9 9219 7291 0 0
T10 6661 5361 0 0

Line Coverage for Instance : tb.dut.u_daon_por_io_div4.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_daon_por_io_div4.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 13426987 8216769 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 13426987 8216769 0 0
T1 2595 1946 0 0
T2 245768 173707 0 0
T3 170382 93720 0 0
T4 2026 1384 0 0
T5 5837 684 0 0
T6 58137 45690 0 0
T7 1842 1193 0 0
T8 4654 4001 0 0
T9 4608 3645 0 0
T10 3329 2680 0 0

Line Coverage for Instance : tb.dut.u_daon_por_usb.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_daon_por_usb.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 26854640 16439927 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26854640 16439927 0 0
T1 5194 3893 0 0
T2 491541 347518 0 0
T3 340793 187522 0 0
T4 4056 2770 0 0
T5 11677 1376 0 0
T6 116275 91379 0 0
T7 3684 2385 0 0
T8 9309 8003 0 0
T9 9218 7291 0 0
T10 6662 5361 0 0

Line Coverage for Instance : tb.dut.u_daon_lc.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_daon_lc.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 55947315 30169538 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55947315 30169538 0 0
T1 10822 5480 0 0
T2 102395 648239 0 0
T3 709970 290841 0 0
T4 8451 4314 0 0
T5 24332 2794 0 0
T6 242242 172686 0 0
T7 7677 4966 0 0
T8 19395 12257 0 0
T9 19209 14806 0 0
T10 13880 11164 0 0

Line Coverage for Instance : tb.dut.u_d0_lc.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_d0_lc.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 55947315 29422876 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55947315 29422876 0 0
T1 10822 5339 0 0
T2 102395 636910 0 0
T3 709970 278747 0 0
T4 8451 4215 0 0
T5 24332 2303 0 0
T6 242242 170655 0 0
T7 7677 4899 0 0
T8 19395 12064 0 0
T9 19209 14641 0 0
T10 13880 11097 0 0

Line Coverage for Instance : tb.dut.u_daon_lc_shadowed.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_daon_lc_shadowed.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 55947315 30169573 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55947315 30169573 0 0
T1 10822 5480 0 0
T2 102395 648239 0 0
T3 709970 290841 0 0
T4 8451 4314 0 0
T5 24332 2794 0 0
T6 242242 172686 0 0
T7 7677 4966 0 0
T8 19395 12257 0 0
T9 19209 14806 0 0
T10 13880 11164 0 0

Line Coverage for Instance : tb.dut.u_d0_lc_shadowed.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_d0_lc_shadowed.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 55947315 29424097 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55947315 29424097 0 0
T1 10822 5339 0 0
T2 102395 636910 0 0
T3 709970 278747 0 0
T4 8451 4215 0 0
T5 24332 2303 0 0
T6 242242 170655 0 0
T7 7677 4899 0 0
T8 19395 12064 0 0
T9 19209 14641 0 0
T10 13880 11097 0 0

Line Coverage for Instance : tb.dut.u_daon_lc_aon.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_daon_lc_aon.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 1697868 897198 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1697868 897198 0 0
T1 323 155 0 0
T2 31144 19442 0 0
T3 21779 8710 0 0
T4 253 126 0 0
T5 732 74 0 0
T6 7300 5135 0 0
T7 229 148 0 0
T8 580 352 0 0
T9 574 437 0 0
T10 415 334 0 0

Line Coverage for Instance : tb.dut.u_daon_lc_io.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_daon_lc_io.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 53707812 28962949 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 53707812 28962949 0 0
T1 10388 5262 0 0
T2 983065 622303 0 0
T3 681589 279181 0 0
T4 8113 4142 0 0
T5 23362 2721 0 0
T6 232559 165785 0 0
T7 7370 4768 0 0
T8 18619 11766 0 0
T9 18444 14217 0 0
T10 13325 10717 0 0

Line Coverage for Instance : tb.dut.u_d0_lc_io.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_d0_lc_io.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 53707812 28243971 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 53707812 28243971 0 0
T1 10388 5126 0 0
T2 983065 611439 0 0
T3 681589 267597 0 0
T4 8113 4046 0 0
T5 23362 2209 0 0
T6 232559 163841 0 0
T7 7370 4704 0 0
T8 18619 11582 0 0
T9 18444 14057 0 0
T10 13325 10653 0 0

Line Coverage for Instance : tb.dut.u_daon_lc_io_div2.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_daon_lc_io_div2.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 26854629 14470383 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26854629 14470383 0 0
T1 5193 2626 0 0
T2 491510 310965 0 0
T3 340771 139349 0 0
T4 4056 2069 0 0
T5 11682 1360 0 0
T6 116278 82857 0 0
T7 3683 2383 0 0
T8 9309 5875 0 0
T9 9219 7103 0 0
T10 6661 5359 0 0

Line Coverage for Instance : tb.dut.u_d0_lc_io_div2.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_d0_lc_io_div2.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 26854629 14111063 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26854629 14111063 0 0
T1 5193 2558 0 0
T2 491510 305533 0 0
T3 340771 133557 0 0
T4 4056 2021 0 0
T5 11682 1104 0 0
T6 116278 81885 0 0
T7 3683 2351 0 0
T8 9309 5783 0 0
T9 9219 7023 0 0
T10 6661 5327 0 0

Line Coverage for Instance : tb.dut.u_daon_lc_io_div4.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_daon_lc_io_div4.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 13426987 7205781 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 13426987 7205781 0 0
T1 2595 1298 0 0
T2 245768 155021 0 0
T3 170382 69150 0 0
T4 2026 1027 0 0
T5 5837 658 0 0
T6 58137 41347 0 0
T7 1842 1191 0 0
T8 4654 2914 0 0
T9 4608 3544 0 0
T10 3329 2678 0 0

Line Coverage for Instance : tb.dut.u_d0_lc_io_div4.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_d0_lc_io_div4.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 13426987 7026024 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 13426987 7026024 0 0
T1 2595 1264 0 0
T2 245768 152305 0 0
T3 170382 66254 0 0
T4 2026 1003 0 0
T5 5837 530 0 0
T6 58137 40861 0 0
T7 1842 1175 0 0
T8 4654 2868 0 0
T9 4608 3504 0 0
T10 3329 2662 0 0

Line Coverage for Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 13426987 7205781 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 13426987 7205781 0 0
T1 2595 1298 0 0
T2 245768 155021 0 0
T3 170382 69150 0 0
T4 2026 1027 0 0
T5 5837 658 0 0
T6 58137 41347 0 0
T7 1842 1191 0 0
T8 4654 2914 0 0
T9 4608 3544 0 0
T10 3329 2678 0 0

Line Coverage for Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 13426987 7026024 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 13426987 7026024 0 0
T1 2595 1264 0 0
T2 245768 152305 0 0
T3 170382 66254 0 0
T4 2026 1003 0 0
T5 5837 530 0 0
T6 58137 40861 0 0
T7 1842 1175 0 0
T8 4654 2868 0 0
T9 4608 3504 0 0
T10 3329 2662 0 0

Line Coverage for Instance : tb.dut.u_daon_lc_usb.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_daon_lc_usb.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 26854640 14470541 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26854640 14470541 0 0
T1 5194 2626 0 0
T2 491541 310979 0 0
T3 340793 139369 0 0
T4 4056 2069 0 0
T5 11677 1360 0 0
T6 116275 82857 0 0
T7 3684 2383 0 0
T8 9309 5875 0 0
T9 9218 7103 0 0
T10 6662 5359 0 0

Line Coverage for Instance : tb.dut.u_d0_lc_usb.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_d0_lc_usb.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 26854640 14110891 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26854640 14110891 0 0
T1 5194 2558 0 0
T2 491541 305547 0 0
T3 340793 133577 0 0
T4 4056 2021 0 0
T5 11677 1104 0 0
T6 116275 81885 0 0
T7 3684 2351 0 0
T8 9309 5783 0 0
T9 9218 7023 0 0
T10 6662 5327 0 0

Line Coverage for Instance : tb.dut.u_d0_sys.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_d0_sys.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 55947315 29095606 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55947315 29095606 0 0
T1 10822 5156 0 0
T2 102395 631549 0 0
T3 709970 272332 0 0
T4 8451 4135 0 0
T5 24332 2303 0 0
T6 242242 169760 0 0
T7 7677 4899 0 0
T8 19395 11786 0 0
T9 19209 14599 0 0
T10 13880 11097 0 0

Line Coverage for Instance : tb.dut.u_daon_sys_io_div4.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_daon_sys_io_div4.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 13426987 7127397 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 13426987 7127397 0 0
T1 2595 1254 0 0
T2 245768 153732 0 0
T3 170382 67609 0 0
T4 2026 1008 0 0
T5 5837 668 0 0
T6 58137 41132 0 0
T7 1842 1191 0 0
T8 4654 2847 0 0
T9 4608 3534 0 0
T10 3329 2678 0 0

Line Coverage for Instance : tb.dut.u_d0_spi_device.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_d0_spi_device.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 13426987 6875306 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 13426987 6875306 0 0
T1 2595 1231 0 0
T2 245768 148806 0 0
T3 170382 64528 0 0
T4 2026 995 0 0
T5 5837 540 0 0
T6 58137 40043 0 0
T7 1842 1175 0 0
T8 4654 2857 0 0
T9 4608 3504 0 0
T10 3329 2309 0 0

Line Coverage for Instance : tb.dut.u_d0_spi_host0.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_d0_spi_host0.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 53707812 27639760 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 53707812 27639760 0 0
T1 10388 5109 0 0
T2 983065 599100 0 0
T3 681589 262824 0 0
T4 8113 4046 0 0
T5 23362 2209 0 0
T6 232559 160124 0 0
T7 7370 4704 0 0
T8 18619 11582 0 0
T9 18444 14057 0 0
T10 13325 9684 0 0

Line Coverage for Instance : tb.dut.u_d0_spi_host1.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_d0_spi_host1.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 26854629 13815629 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26854629 13815629 0 0
T1 5193 2558 0 0
T2 491510 301528 0 0
T3 340771 131505 0 0
T4 4056 2021 0 0
T5 11682 1104 0 0
T6 116278 81015 0 0
T7 3683 2351 0 0
T8 9309 5783 0 0
T9 9219 7023 0 0
T10 6661 4726 0 0

Line Coverage for Instance : tb.dut.u_d0_usb.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_d0_usb.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 26854640 13810459 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26854640 13810459 0 0
T1 5194 2558 0 0
T2 491541 300336 0 0
T3 340793 131759 0 0
T4 4056 2021 0 0
T5 11677 1104 0 0
T6 116275 80942 0 0
T7 3684 2351 0 0
T8 9309 5783 0 0
T9 9218 6848 0 0
T10 6662 4654 0 0

Line Coverage for Instance : tb.dut.u_d0_usb_aon.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_d0_usb_aon.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 1697868 856744 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1697868 856744 0 0
T1 323 151 0 0
T2 31144 18874 0 0
T3 21779 8220 0 0
T4 253 121 0 0
T5 732 58 0 0
T6 7300 5000 0 0
T7 229 146 0 0
T8 580 347 0 0
T9 574 433 0 0
T10 415 292 0 0

Line Coverage for Instance : tb.dut.u_d0_i2c0.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_d0_i2c0.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 13426987 6879422 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 13426987 6879422 0 0
T1 2595 1264 0 0
T2 245768 149459 0 0
T3 170382 64806 0 0
T4 2026 1003 0 0
T5 5837 540 0 0
T6 58137 40066 0 0
T7 1842 1175 0 0
T8 4654 2868 0 0
T9 4608 3504 0 0
T10 3329 2358 0 0

Line Coverage for Instance : tb.dut.u_d0_i2c1.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_d0_i2c1.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 13426987 6881561 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 13426987 6881561 0 0
T1 2595 1264 0 0
T2 245768 151072 0 0
T3 170382 64496 0 0
T4 2026 1003 0 0
T5 5837 540 0 0
T6 58137 40225 0 0
T7 1842 1175 0 0
T8 4654 2868 0 0
T9 4608 3504 0 0
T10 3329 2426 0 0

Line Coverage for Instance : tb.dut.u_d0_i2c2.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_d0_i2c2.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 13426987 6884291 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 13426987 6884291 0 0
T1 2595 1264 0 0
T2 245768 150061 0 0
T3 170382 65208 0 0
T4 2026 1003 0 0
T5 5837 540 0 0
T6 58137 40355 0 0
T7 1842 1175 0 0
T8 4654 2868 0 0
T9 4608 3504 0 0
T10 3329 2364 0 0

Line Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 1697868 1050041 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1697868 1050041 0 0
T1 323 244 0 0
T2 31144 22192 0 0
T3 21779 12240 0 0
T4 253 174 0 0
T5 732 90 0 0
T6 7300 5756 0 0
T7 229 150 0 0
T8 580 501 0 0
T9 574 457 0 0
T10 415 336 0 0

Line Coverage for Instance : tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 1697868 1031158 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1697868 1031158 0 0
T1 323 242 0 0
T2 31144 21910 0 0
T3 21779 11950 0 0
T4 253 172 0 0
T5 732 74 0 0
T6 7300 5706 0 0
T7 229 148 0 0
T8 580 499 0 0
T9 574 453 0 0
T10 415 334 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%