Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12528607	9113	0	0
alert_regwen_rd_A	12528607	5866	0	0
cpu_regwen_rd_A	12528607	5906	0	0
sw_rst_ctrl_n_0_rd_A	12528607	9884	0	0
sw_rst_ctrl_n_1_rd_A	12528607	9710	0	0
sw_rst_ctrl_n_2_rd_A	12528607	9785	0	0
sw_rst_ctrl_n_3_rd_A	12528607	9725	0	0
sw_rst_ctrl_n_4_rd_A	12528607	9679	0	0
sw_rst_ctrl_n_5_rd_A	12528607	10038	0	0
sw_rst_ctrl_n_6_rd_A	12528607	9774	0	0
sw_rst_ctrl_n_7_rd_A	12528607	9761	0	0
sw_rst_regwen_0_rd_A	12528607	5992	0	0
sw_rst_regwen_1_rd_A	12528607	6175	0	0
sw_rst_regwen_2_rd_A	12528607	6264	0	0
sw_rst_regwen_3_rd_A	12528607	6114	0	0
sw_rst_regwen_4_rd_A	12528607	6043	0	0
sw_rst_regwen_5_rd_A	12528607	6033	0	0
sw_rst_regwen_6_rd_A	12528607	5985	0	0
sw_rst_regwen_7_rd_A	12528607	6143	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12528607	9113	0	0
T65	10861	2	0	0
T66	2788	9	0	0
T67	3047	22	0	0
T68	16998	5	0	0
T69	4900	610	0	0
T86	21362	2	0	0
T91	3763	358	0	0
T92	2789	4	0	0
T93	0	343	0	0
T97	4293	0	0	0
T124	4051	16	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12528607	5866	0	0
T6	51987	110	0	0
T7	1775	0	0	0
T8	3641	0	0	0
T9	4515	0	0	0
T10	3312	0	0	0
T11	2104	0	0	0
T12	85811	0	0	0
T13	179535	205	0	0
T14	5456	0	0	0
T30	0	45	0	0
T63	0	13	0	0
T70	5680	0	0	0
T101	0	19	0	0
T104	0	207	0	0
T106	0	178	0	0
T125	0	52	0	0
T126	0	26	0	0
T127	0	4	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12528607	5906	0	0
T6	51987	62	0	0
T7	1775	0	0	0
T8	3641	0	0	0
T9	4515	0	0	0
T10	3312	0	0	0
T11	2104	0	0	0
T12	85811	0	0	0
T13	179535	161	0	0
T14	5456	0	0	0
T30	0	26	0	0
T63	0	15	0	0
T70	5680	0	0	0
T101	0	21	0	0
T104	0	220	0	0
T106	0	104	0	0
T125	0	73	0	0
T126	0	21	0	0
T127	0	8	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12528607	9884	0	0
T6	51987	149	0	0
T7	1775	0	0	0
T8	3641	0	0	0
T9	4515	0	0	0
T10	3312	0	0	0
T11	2104	0	0	0
T12	85811	0	0	0
T13	179535	394	0	0
T14	5456	0	0	0
T30	0	43	0	0
T62	0	166	0	0
T70	5680	0	0	0
T101	0	39	0	0
T104	0	487	0	0
T106	0	290	0	0
T125	0	57	0	0
T128	0	63	0	0
T129	0	121	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12528607	9710	0	0
T6	51987	132	0	0
T7	1775	0	0	0
T8	3641	0	0	0
T9	4515	0	0	0
T10	3312	0	0	0
T11	2104	0	0	0
T12	85811	0	0	0
T13	179535	372	0	0
T14	5456	0	0	0
T30	0	26	0	0
T62	0	193	0	0
T70	5680	0	0	0
T101	0	63	0	0
T104	0	567	0	0
T106	0	261	0	0
T125	0	67	0	0
T128	0	65	0	0
T129	0	109	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12528607	9785	0	0
T6	51987	114	0	0
T7	1775	0	0	0
T8	3641	0	0	0
T9	4515	0	0	0
T10	3312	0	0	0
T11	2104	0	0	0
T12	85811	0	0	0
T13	179535	292	0	0
T14	5456	0	0	0
T30	0	29	0	0
T62	0	184	0	0
T70	5680	0	0	0
T101	0	37	0	0
T104	0	546	0	0
T106	0	291	0	0
T125	0	61	0	0
T128	0	52	0	0
T129	0	111	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12528607	9725	0	0
T6	51987	150	0	0
T7	1775	0	0	0
T8	3641	0	0	0
T9	4515	0	0	0
T10	3312	0	0	0
T11	2104	0	0	0
T12	85811	0	0	0
T13	179535	325	0	0
T14	5456	0	0	0
T30	0	51	0	0
T62	0	191	0	0
T70	5680	0	0	0
T101	0	44	0	0
T104	0	469	0	0
T106	0	273	0	0
T125	0	35	0	0
T128	0	51	0	0
T129	0	90	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12528607	9679	0	0
T6	51987	161	0	0
T7	1775	0	0	0
T8	3641	0	0	0
T9	4515	0	0	0
T10	3312	0	0	0
T11	2104	0	0	0
T12	85811	0	0	0
T13	179535	318	0	0
T14	5456	0	0	0
T30	0	46	0	0
T62	0	164	0	0
T70	5680	0	0	0
T101	0	33	0	0
T104	0	556	0	0
T106	0	259	0	0
T125	0	58	0	0
T128	0	72	0	0
T129	0	111	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12528607	10038	0	0
T6	51987	122	0	0
T7	1775	0	0	0
T8	3641	0	0	0
T9	4515	0	0	0
T10	3312	0	0	0
T11	2104	0	0	0
T12	85811	0	0	0
T13	179535	345	0	0
T14	5456	0	0	0
T30	0	41	0	0
T62	0	172	0	0
T70	5680	0	0	0
T101	0	40	0	0
T104	0	528	0	0
T106	0	316	0	0
T125	0	46	0	0
T128	0	83	0	0
T129	0	180	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12528607	9774	0	0
T6	51987	146	0	0
T7	1775	0	0	0
T8	3641	0	0	0
T9	4515	0	0	0
T10	3312	0	0	0
T11	2104	0	0	0
T12	85811	0	0	0
T13	179535	402	0	0
T14	5456	0	0	0
T30	0	29	0	0
T62	0	189	0	0
T70	5680	0	0	0
T101	0	42	0	0
T104	0	541	0	0
T106	0	227	0	0
T125	0	53	0	0
T128	0	57	0	0
T129	0	95	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12528607	9761	0	0
T6	51987	128	0	0
T7	1775	0	0	0
T8	3641	0	0	0
T9	4515	0	0	0
T10	3312	0	0	0
T11	2104	0	0	0
T12	85811	0	0	0
T13	179535	369	0	0
T14	5456	0	0	0
T30	0	37	0	0
T62	0	170	0	0
T70	5680	0	0	0
T101	0	66	0	0
T104	0	497	0	0
T106	0	321	0	0
T125	0	71	0	0
T128	0	66	0	0
T129	0	111	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12528607	5992	0	0
T6	51987	95	0	0
T7	1775	0	0	0
T8	3641	0	0	0
T9	4515	0	0	0
T10	3312	0	0	0
T11	2104	0	0	0
T12	85811	0	0	0
T13	179535	186	0	0
T14	5456	0	0	0
T30	0	56	0	0
T62	0	41	0	0
T70	5680	0	0	0
T101	0	31	0	0
T104	0	242	0	0
T106	0	98	0	0
T125	0	36	0	0
T126	0	40	0	0
T129	0	18	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12528607	6175	0	0
T6	51987	97	0	0
T7	1775	0	0	0
T8	3641	0	0	0
T9	4515	0	0	0
T10	3312	0	0	0
T11	2104	0	0	0
T12	85811	0	0	0
T13	179535	136	0	0
T14	5456	0	0	0
T30	0	39	0	0
T62	0	33	0	0
T70	5680	0	0	0
T101	0	28	0	0
T104	0	238	0	0
T106	0	150	0	0
T125	0	50	0	0
T126	0	33	0	0
T129	0	28	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12528607	6264	0	0
T6	51987	64	0	0
T7	1775	0	0	0
T8	3641	0	0	0
T9	4515	0	0	0
T10	3312	0	0	0
T11	2104	0	0	0
T12	85811	0	0	0
T13	179535	163	0	0
T14	5456	0	0	0
T30	0	36	0	0
T62	0	22	0	0
T70	5680	0	0	0
T101	0	33	0	0
T104	0	229	0	0
T106	0	110	0	0
T125	0	53	0	0
T126	0	43	0	0
T129	0	8	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12528607	6114	0	0
T6	51987	87	0	0
T7	1775	0	0	0
T8	3641	0	0	0
T9	4515	0	0	0
T10	3312	0	0	0
T11	2104	0	0	0
T12	85811	0	0	0
T13	179535	170	0	0
T14	5456	0	0	0
T30	0	46	0	0
T62	0	43	0	0
T70	5680	0	0	0
T101	0	28	0	0
T104	0	222	0	0
T106	0	93	0	0
T125	0	50	0	0
T126	0	39	0	0
T129	0	19	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12528607	6043	0	0
T6	51987	110	0	0
T7	1775	0	0	0
T8	3641	0	0	0
T9	4515	0	0	0
T10	3312	0	0	0
T11	2104	0	0	0
T12	85811	0	0	0
T13	179535	141	0	0
T14	5456	0	0	0
T30	0	28	0	0
T62	0	41	0	0
T70	5680	0	0	0
T101	0	49	0	0
T104	0	215	0	0
T106	0	93	0	0
T125	0	48	0	0
T126	0	30	0	0
T129	0	28	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12528607	6033	0	0
T6	51987	79	0	0
T7	1775	0	0	0
T8	3641	0	0	0
T9	4515	0	0	0
T10	3312	0	0	0
T11	2104	0	0	0
T12	85811	0	0	0
T13	179535	135	0	0
T14	5456	0	0	0
T30	0	34	0	0
T62	0	35	0	0
T70	5680	0	0	0
T101	0	51	0	0
T104	0	246	0	0
T106	0	97	0	0
T125	0	43	0	0
T126	0	32	0	0
T129	0	15	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12528607	5985	0	0
T6	51987	84	0	0
T7	1775	0	0	0
T8	3641	0	0	0
T9	4515	0	0	0
T10	3312	0	0	0
T11	2104	0	0	0
T12	85811	0	0	0
T13	179535	151	0	0
T14	5456	0	0	0
T30	0	34	0	0
T62	0	28	0	0
T70	5680	0	0	0
T101	0	48	0	0
T104	0	214	0	0
T106	0	139	0	0
T125	0	52	0	0
T126	0	10	0	0
T129	0	4	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12528607	6143	0	0
T6	51987	90	0	0
T7	1775	0	0	0
T8	3641	0	0	0
T9	4515	0	0	0
T10	3312	0	0	0
T11	2104	0	0	0
T12	85811	0	0	0
T13	179535	187	0	0
T14	5456	0	0	0
T30	0	37	0	0
T62	0	19	0	0
T70	5680	0	0	0
T101	0	41	0	0
T104	0	228	0	0
T106	0	135	0	0
T125	0	43	0	0
T126	0	21	0	0
T129	0	22	0	0