Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T2,T3,T5

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	11790944	14347	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	11790944	132100	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	11790944	7033226	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	11790944	210656	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	11790944	14347	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	11790944	132100	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	11790944	7033226	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	11790944	210656	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11790944	14347	0	0
T1	2006	9	0	0
T2	214513	230	0	0
T3	133798	288	0	0
T4	1674	4	0	0
T5	5294	0	0	0
T6	51987	43	0	0
T7	1775	0	0	0
T8	3641	15	0	0
T9	4515	4	0	0
T10	3312	0	0	0
T11	0	4	0	0
T12	0	172	0	0
T13	0	154	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11790944	132100	0	0
T1	2006	81	0	0
T2	214513	2109	0	0
T3	133798	2610	0	0
T4	1674	36	0	0
T5	5294	0	0	0
T6	51987	389	0	0
T7	1775	0	0	0
T8	3641	135	0	0
T9	4515	37	0	0
T10	3312	0	0	0
T11	0	38	0	0
T12	0	1581	0	0
T13	0	1410	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11790944	7033226	0	0
T1	2006	1259	0	0
T2	214513	152371	0	0
T3	133798	66333	0	0
T4	1674	1003	0	0
T5	5294	571	0	0
T6	51987	40880	0	0
T7	1775	1177	0	0
T8	3641	2862	0	0
T9	4515	3516	0	0
T10	3312	2664	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11790944	210656	0	0
T1	2006	125	0	0
T2	214513	3398	0	0
T3	133798	4151	0	0
T4	1674	55	0	0
T5	5294	0	0	0
T6	51987	604	0	0
T7	1775	0	0	0
T8	3641	202	0	0
T9	4515	47	0	0
T10	3312	0	0	0
T11	0	53	0	0
T12	0	2500	0	0
T13	0	2229	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11790944	14347	0	0
T1	2006	9	0	0
T2	214513	230	0	0
T3	133798	288	0	0
T4	1674	4	0	0
T5	5294	0	0	0
T6	51987	43	0	0
T7	1775	0	0	0
T8	3641	15	0	0
T9	4515	4	0	0
T10	3312	0	0	0
T11	0	4	0	0
T12	0	172	0	0
T13	0	154	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11790944	132100	0	0
T1	2006	81	0	0
T2	214513	2109	0	0
T3	133798	2610	0	0
T4	1674	36	0	0
T5	5294	0	0	0
T6	51987	389	0	0
T7	1775	0	0	0
T8	3641	135	0	0
T9	4515	37	0	0
T10	3312	0	0	0
T11	0	38	0	0
T12	0	1581	0	0
T13	0	1410	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11790944	7033226	0	0
T1	2006	1259	0	0
T2	214513	152371	0	0
T3	133798	66333	0	0
T4	1674	1003	0	0
T5	5294	571	0	0
T6	51987	40880	0	0
T7	1775	1177	0	0
T8	3641	2862	0	0
T9	4515	3516	0	0
T10	3312	2664	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11790944	210656	0	0
T1	2006	125	0	0
T2	214513	3398	0	0
T3	133798	4151	0	0
T4	1674	55	0	0
T5	5294	0	0	0
T6	51987	604	0	0
T7	1775	0	0	0
T8	3641	202	0	0
T9	4515	47	0	0
T10	3312	0	0	0
T11	0	53	0	0
T12	0	2500	0	0
T13	0	2229	0	0