Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T6
0	1	Covered	T2,T3,T6
1	0	Covered	T2,T3,T6

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T2,T3,T6
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	55947315	8967	0	0
CascadeEffAonToRstPorAboveRise_A	55947315	8967	0	0
CascadeEffAonToRstPorIoAboveFall_A	53707812	8967	0	0
CascadeEffAonToRstPorIoAboveRise_A	53707812	8967	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	26854629	8967	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	26854629	8967	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	13426987	8967	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	13426987	8967	0	0
CascadeEffAonToRstPorUcbAboveFall_A	26854640	8967	0	0
CascadeEffAonToRstPorUcbAboveRise_A	26854640	8967	0	0
CascadeLcToLcAboveFall_A	55947315	23314	0	0
CascadeLcToLcAboveRise_A	55947315	23314	0	0
CascadeLcToLcAonAboveFall_A	1697868	23314	0	0
CascadeLcToLcAonAboveRise_A	1697868	23314	0	0
CascadeLcToLcShadowedAboveFall_A	55947315	23314	0	0
CascadeLcToLcShadowedAboveRise_A	55947315	23314	0	0
CascadePorToAonAboveFall_A	1697868	6902	0	0
CascadeSysToSysAboveFall_A	55947315	23314	0	0
CascadeSysToSysAboveRise_A	55947315	23314	0	0
ScanRstToAonRise_A	1697868	241	0	0
StablePorToAonRise_A	1697868	8967	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	11790944	23314	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	11790944	23314	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	11790944	23314	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	11790944	23314	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	13426987	23314	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	13426987	23314	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	11790944	23314	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	11790944	23314	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	11790944	23314	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	11790944	23314	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55947315	8967	0	0
T1	10822	1	0	0
T2	102395	141	0	0
T3	709970	145	0	0
T4	8451	1	0	0
T5	24332	8	0	0
T6	242242	25	0	0
T7	7677	1	0	0
T8	19395	1	0	0
T9	19209	2	0	0
T10	13880	1	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55947315	8967	0	0
T1	10822	1	0	0
T2	102395	141	0	0
T3	709970	145	0	0
T4	8451	1	0	0
T5	24332	8	0	0
T6	242242	25	0	0
T7	7677	1	0	0
T8	19395	1	0	0
T9	19209	2	0	0
T10	13880	1	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53707812	8967	0	0
T1	10388	1	0	0
T2	983065	141	0	0
T3	681589	145	0	0
T4	8113	1	0	0
T5	23362	8	0	0
T6	232559	25	0	0
T7	7370	1	0	0
T8	18619	1	0	0
T9	18444	2	0	0
T10	13325	1	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53707812	8967	0	0
T1	10388	1	0	0
T2	983065	141	0	0
T3	681589	145	0	0
T4	8113	1	0	0
T5	23362	8	0	0
T6	232559	25	0	0
T7	7370	1	0	0
T8	18619	1	0	0
T9	18444	2	0	0
T10	13325	1	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26854629	8967	0	0
T1	5193	1	0	0
T2	491510	141	0	0
T3	340771	145	0	0
T4	4056	1	0	0
T5	11682	8	0	0
T6	116278	25	0	0
T7	3683	1	0	0
T8	9309	1	0	0
T9	9219	2	0	0
T10	6661	1	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26854629	8967	0	0
T1	5193	1	0	0
T2	491510	141	0	0
T3	340771	145	0	0
T4	4056	1	0	0
T5	11682	8	0	0
T6	116278	25	0	0
T7	3683	1	0	0
T8	9309	1	0	0
T9	9219	2	0	0
T10	6661	1	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13426987	8967	0	0
T1	2595	1	0	0
T2	245768	141	0	0
T3	170382	145	0	0
T4	2026	1	0	0
T5	5837	8	0	0
T6	58137	25	0	0
T7	1842	1	0	0
T8	4654	1	0	0
T9	4608	2	0	0
T10	3329	1	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13426987	8967	0	0
T1	2595	1	0	0
T2	245768	141	0	0
T3	170382	145	0	0
T4	2026	1	0	0
T5	5837	8	0	0
T6	58137	25	0	0
T7	1842	1	0	0
T8	4654	1	0	0
T9	4608	2	0	0
T10	3329	1	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26854640	8967	0	0
T1	5194	1	0	0
T2	491541	141	0	0
T3	340793	145	0	0
T4	4056	1	0	0
T5	11677	8	0	0
T6	116275	25	0	0
T7	3684	1	0	0
T8	9309	1	0	0
T9	9218	2	0	0
T10	6662	1	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26854640	8967	0	0
T1	5194	1	0	0
T2	491541	141	0	0
T3	340793	145	0	0
T4	4056	1	0	0
T5	11677	8	0	0
T6	116275	25	0	0
T7	3684	1	0	0
T8	9309	1	0	0
T9	9218	2	0	0
T10	6662	1	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55947315	23314	0	0
T1	10822	10	0	0
T2	102395	371	0	0
T3	709970	433	0	0
T4	8451	5	0	0
T5	24332	8	0	0
T6	242242	68	0	0
T7	7677	1	0	0
T8	19395	16	0	0
T9	19209	6	0	0
T10	13880	1	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55947315	23314	0	0
T1	10822	10	0	0
T2	102395	371	0	0
T3	709970	433	0	0
T4	8451	5	0	0
T5	24332	8	0	0
T6	242242	68	0	0
T7	7677	1	0	0
T8	19395	16	0	0
T9	19209	6	0	0
T10	13880	1	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1697868	23314	0	0
T1	323	10	0	0
T2	31144	371	0	0
T3	21779	433	0	0
T4	253	5	0	0
T5	732	8	0	0
T6	7300	68	0	0
T7	229	1	0	0
T8	580	16	0	0
T9	574	6	0	0
T10	415	1	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1697868	23314	0	0
T1	323	10	0	0
T2	31144	371	0	0
T3	21779	433	0	0
T4	253	5	0	0
T5	732	8	0	0
T6	7300	68	0	0
T7	229	1	0	0
T8	580	16	0	0
T9	574	6	0	0
T10	415	1	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55947315	23314	0	0
T1	10822	10	0	0
T2	102395	371	0	0
T3	709970	433	0	0
T4	8451	5	0	0
T5	24332	8	0	0
T6	242242	68	0	0
T7	7677	1	0	0
T8	19395	16	0	0
T9	19209	6	0	0
T10	13880	1	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55947315	23314	0	0
T1	10822	10	0	0
T2	102395	371	0	0
T3	709970	433	0	0
T4	8451	5	0	0
T5	24332	8	0	0
T6	242242	68	0	0
T7	7677	1	0	0
T8	19395	16	0	0
T9	19209	6	0	0
T10	13880	1	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1697868	6902	0	0
T1	323	1	0	0
T2	31144	66	0	0
T3	21779	79	0	0
T4	253	1	0	0
T5	732	8	0	0
T6	7300	11	0	0
T7	229	1	0	0
T8	580	1	0	0
T9	574	1	0	0
T10	415	1	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55947315	23314	0	0
T1	10822	10	0	0
T2	102395	371	0	0
T3	709970	433	0	0
T4	8451	5	0	0
T5	24332	8	0	0
T6	242242	68	0	0
T7	7677	1	0	0
T8	19395	16	0	0
T9	19209	6	0	0
T10	13880	1	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55947315	23314	0	0
T1	10822	10	0	0
T2	102395	371	0	0
T3	709970	433	0	0
T4	8451	5	0	0
T5	24332	8	0	0
T6	242242	68	0	0
T7	7677	1	0	0
T8	19395	16	0	0
T9	19209	6	0	0
T10	13880	1	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1697868	241	0	0
T2	31144	7	0	0
T3	21779	5	0	0
T4	253	0	0	0
T5	732	0	0	0
T6	7300	3	0	0
T7	229	0	0	0
T8	580	0	0	0
T9	574	0	0	0
T10	415	0	0	0
T12	0	9	0	0
T13	0	5	0	0
T14	729	0	0	0
T25	0	1	0	0
T42	0	2	0	0
T46	0	1	0	0
T57	0	3	0	0
T58	0	1	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1697868	8967	0	0
T1	323	1	0	0
T2	31144	141	0	0
T3	21779	145	0	0
T4	253	1	0	0
T5	732	8	0	0
T6	7300	25	0	0
T7	229	1	0	0
T8	580	1	0	0
T9	574	2	0	0
T10	415	1	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11790944	23314	0	0
T1	2006	10	0	0
T2	214513	371	0	0
T3	133798	433	0	0
T4	1674	5	0	0
T5	5294	8	0	0
T6	51987	68	0	0
T7	1775	1	0	0
T8	3641	16	0	0
T9	4515	6	0	0
T10	3312	1	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11790944	23314	0	0
T1	2006	10	0	0
T2	214513	371	0	0
T3	133798	433	0	0
T4	1674	5	0	0
T5	5294	8	0	0
T6	51987	68	0	0
T7	1775	1	0	0
T8	3641	16	0	0
T9	4515	6	0	0
T10	3312	1	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11790944	23314	0	0
T1	2006	10	0	0
T2	214513	371	0	0
T3	133798	433	0	0
T4	1674	5	0	0
T5	5294	8	0	0
T6	51987	68	0	0
T7	1775	1	0	0
T8	3641	16	0	0
T9	4515	6	0	0
T10	3312	1	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11790944	23314	0	0
T1	2006	10	0	0
T2	214513	371	0	0
T3	133798	433	0	0
T4	1674	5	0	0
T5	5294	8	0	0
T6	51987	68	0	0
T7	1775	1	0	0
T8	3641	16	0	0
T9	4515	6	0	0
T10	3312	1	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13426987	23314	0	0
T1	2595	10	0	0
T2	245768	371	0	0
T3	170382	433	0	0
T4	2026	5	0	0
T5	5837	8	0	0
T6	58137	68	0	0
T7	1842	1	0	0
T8	4654	16	0	0
T9	4608	6	0	0
T10	3329	1	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13426987	23314	0	0
T1	2595	10	0	0
T2	245768	371	0	0
T3	170382	433	0	0
T4	2026	5	0	0
T5	5837	8	0	0
T6	58137	68	0	0
T7	1842	1	0	0
T8	4654	16	0	0
T9	4608	6	0	0
T10	3329	1	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11790944	23314	0	0
T1	2006	10	0	0
T2	214513	371	0	0
T3	133798	433	0	0
T4	1674	5	0	0
T5	5294	8	0	0
T6	51987	68	0	0
T7	1775	1	0	0
T8	3641	16	0	0
T9	4515	6	0	0
T10	3312	1	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11790944	23314	0	0
T1	2006	10	0	0
T2	214513	371	0	0
T3	133798	433	0	0
T4	1674	5	0	0
T5	5294	8	0	0
T6	51987	68	0	0
T7	1775	1	0	0
T8	3641	16	0	0
T9	4515	6	0	0
T10	3312	1	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11790944	23314	0	0
T1	2006	10	0	0
T2	214513	371	0	0
T3	133798	433	0	0
T4	1674	5	0	0
T5	5294	8	0	0
T6	51987	68	0	0
T7	1775	1	0	0
T8	3641	16	0	0
T9	4515	6	0	0
T10	3312	1	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11790944	23314	0	0
T1	2006	10	0	0
T2	214513	371	0	0
T3	133798	433	0	0
T4	1674	5	0	0
T5	5294	8	0	0
T6	51987	68	0	0
T7	1775	1	0	0
T8	3641	16	0	0
T9	4515	6	0	0
T10	3312	1	0	0