V1 |
smoke |
rstmgr_smoke |
1.660s |
260.699us |
50 |
50 |
100.00 |
V1 |
csr_hw_reset |
rstmgr_csr_hw_reset |
1.020s |
152.486us |
5 |
5 |
100.00 |
V1 |
csr_rw |
rstmgr_csr_rw |
0.850s |
85.277us |
20 |
20 |
100.00 |
V1 |
csr_bit_bash |
rstmgr_csr_bit_bash |
9.320s |
2.291ms |
5 |
5 |
100.00 |
V1 |
csr_aliasing |
rstmgr_csr_aliasing |
2.550s |
344.031us |
5 |
5 |
100.00 |
V1 |
csr_mem_rw_with_rand_reset |
rstmgr_csr_mem_rw_with_rand_reset |
1.360s |
204.873us |
20 |
20 |
100.00 |
V1 |
regwen_csr_and_corresponding_lockable_csr |
rstmgr_csr_rw |
0.850s |
85.277us |
20 |
20 |
100.00 |
|
|
rstmgr_csr_aliasing |
2.550s |
344.031us |
5 |
5 |
100.00 |
V1 |
|
TOTAL |
|
|
105 |
105 |
100.00 |
V2 |
reset_stretcher |
rstmgr_por_stretcher |
0.920s |
149.535us |
50 |
50 |
100.00 |
V2 |
sw_rst |
rstmgr_sw_rst |
2.850s |
544.953us |
50 |
50 |
100.00 |
V2 |
sw_rst_reset_race |
rstmgr_sw_rst_reset_race |
1.490s |
263.823us |
50 |
50 |
100.00 |
V2 |
reset_info |
rstmgr_reset |
8.620s |
2.088ms |
50 |
50 |
100.00 |
V2 |
cpu_info |
rstmgr_reset |
8.620s |
2.088ms |
50 |
50 |
100.00 |
V2 |
alert_info |
rstmgr_reset |
8.620s |
2.088ms |
50 |
50 |
100.00 |
V2 |
reset_info_capture |
rstmgr_reset |
8.620s |
2.088ms |
50 |
50 |
100.00 |
V2 |
stress_all |
rstmgr_stress_all |
1.021m |
18.551ms |
50 |
50 |
100.00 |
V2 |
alert_test |
rstmgr_alert_test |
0.910s |
172.242us |
50 |
50 |
100.00 |
V2 |
tl_d_oob_addr_access |
rstmgr_tl_errors |
3.680s |
621.542us |
20 |
20 |
100.00 |
V2 |
tl_d_illegal_access |
rstmgr_tl_errors |
3.680s |
621.542us |
20 |
20 |
100.00 |
V2 |
tl_d_outstanding_access |
rstmgr_csr_hw_reset |
1.020s |
152.486us |
5 |
5 |
100.00 |
|
|
rstmgr_csr_rw |
0.850s |
85.277us |
20 |
20 |
100.00 |
|
|
rstmgr_csr_aliasing |
2.550s |
344.031us |
5 |
5 |
100.00 |
|
|
rstmgr_same_csr_outstanding |
1.540s |
225.195us |
20 |
20 |
100.00 |
V2 |
tl_d_partial_access |
rstmgr_csr_hw_reset |
1.020s |
152.486us |
5 |
5 |
100.00 |
|
|
rstmgr_csr_rw |
0.850s |
85.277us |
20 |
20 |
100.00 |
|
|
rstmgr_csr_aliasing |
2.550s |
344.031us |
5 |
5 |
100.00 |
|
|
rstmgr_same_csr_outstanding |
1.540s |
225.195us |
20 |
20 |
100.00 |
V2 |
|
TOTAL |
|
|
340 |
340 |
100.00 |
V2S |
tl_intg_err |
rstmgr_sec_cm |
33.160s |
16.525ms |
5 |
5 |
100.00 |
|
|
rstmgr_tl_intg_err |
3.340s |
894.044us |
20 |
20 |
100.00 |
V2S |
prim_count_check |
rstmgr_sec_cm |
33.160s |
16.525ms |
5 |
5 |
100.00 |
V2S |
prim_fsm_check |
rstmgr_sec_cm |
33.160s |
16.525ms |
5 |
5 |
100.00 |
V2S |
sec_cm_bus_integrity |
rstmgr_tl_intg_err |
3.340s |
894.044us |
20 |
20 |
100.00 |
V2S |
sec_cm_scan_intersig_mubi |
rstmgr_sec_cm_scan_intersig_mubi |
1.180s |
175.368us |
50 |
50 |
100.00 |
V2S |
sec_cm_leaf_rst_bkgn_chk |
rstmgr_leaf_rst_cnsty |
9.310s |
2.356ms |
50 |
50 |
100.00 |
V2S |
sec_cm_leaf_rst_shadow |
rstmgr_leaf_rst_shadow_attack |
1.210s |
243.570us |
50 |
50 |
100.00 |
V2S |
sec_cm_leaf_fsm_sparse |
rstmgr_sec_cm |
33.160s |
16.525ms |
5 |
5 |
100.00 |
V2S |
sec_cm_sw_rst_config_regwen |
rstmgr_csr_rw |
0.850s |
85.277us |
20 |
20 |
100.00 |
V2S |
sec_cm_dump_ctrl_config_regwen |
rstmgr_csr_rw |
0.850s |
85.277us |
20 |
20 |
100.00 |
V2S |
|
TOTAL |
|
|
175 |
175 |
100.00 |
V3 |
stress_all_with_rand_reset |
rstmgr_stress_all_with_rand_reset |
|
|
0 |
0 |
-- |
V3 |
|
TOTAL |
|
|
0 |
0 |
-- |
|
|
TOTAL |
|
|
620 |
620 |
100.00 |