Summary for Variable enable
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1600 |
1 |
|
|
T10 |
32 |
|
T61 |
32 |
|
T65 |
32 |
auto[1] |
4392 |
1 |
|
|
T3 |
3 |
|
T8 |
23 |
|
T10 |
26 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1600 |
1 |
|
|
T10 |
32 |
|
T61 |
32 |
|
T65 |
32 |
auto[1] |
4392 |
1 |
|
|
T3 |
3 |
|
T8 |
23 |
|
T10 |
26 |
Summary for Variable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1737 |
1 |
|
|
T8 |
4 |
|
T10 |
12 |
|
T12 |
12 |
auto[1] |
4255 |
1 |
|
|
T3 |
3 |
|
T8 |
19 |
|
T10 |
46 |
Summary for Variable rst_n_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1737 |
1 |
|
|
T8 |
4 |
|
T10 |
12 |
|
T12 |
12 |
auto[1] |
4255 |
1 |
|
|
T3 |
3 |
|
T8 |
19 |
|
T10 |
46 |
Summary for Cross sw_rst_cross
Samples crossed: enable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for sw_rst_cross
Bins
enable | rst_n | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
400 |
1 |
|
|
T10 |
8 |
|
T61 |
8 |
|
T65 |
8 |
auto[0] |
auto[1] |
1200 |
1 |
|
|
T10 |
24 |
|
T61 |
24 |
|
T65 |
24 |
auto[1] |
auto[0] |
1337 |
1 |
|
|
T8 |
4 |
|
T10 |
4 |
|
T12 |
12 |
auto[1] |
auto[1] |
3055 |
1 |
|
|
T3 |
3 |
|
T8 |
19 |
|
T10 |
22 |
Summary for Variable enable
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1469 |
1 |
|
|
T10 |
28 |
|
T61 |
28 |
|
T46 |
3 |
auto[1] |
4316 |
1 |
|
|
T3 |
3 |
|
T8 |
14 |
|
T10 |
30 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1469 |
1 |
|
|
T10 |
28 |
|
T61 |
28 |
|
T46 |
3 |
auto[1] |
4316 |
1 |
|
|
T3 |
3 |
|
T8 |
14 |
|
T10 |
30 |
Summary for Variable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1623 |
1 |
|
|
T10 |
17 |
|
T12 |
5 |
|
T61 |
15 |
auto[1] |
4162 |
1 |
|
|
T3 |
3 |
|
T8 |
14 |
|
T10 |
41 |
Summary for Variable rst_n_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1623 |
1 |
|
|
T10 |
17 |
|
T12 |
5 |
|
T61 |
15 |
auto[1] |
4162 |
1 |
|
|
T3 |
3 |
|
T8 |
14 |
|
T10 |
41 |
Summary for Cross sw_rst_cross
Samples crossed: enable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for sw_rst_cross
Bins
enable | rst_n | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
381 |
1 |
|
|
T10 |
7 |
|
T61 |
7 |
|
T46 |
1 |
auto[0] |
auto[1] |
1088 |
1 |
|
|
T10 |
21 |
|
T61 |
21 |
|
T46 |
2 |
auto[1] |
auto[0] |
1242 |
1 |
|
|
T10 |
10 |
|
T12 |
5 |
|
T61 |
8 |
auto[1] |
auto[1] |
3074 |
1 |
|
|
T3 |
3 |
|
T8 |
14 |
|
T10 |
20 |
Summary for Variable enable
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1278 |
1 |
|
|
T3 |
3 |
|
T10 |
24 |
|
T61 |
24 |
auto[1] |
4417 |
1 |
|
|
T8 |
14 |
|
T10 |
34 |
|
T12 |
22 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1278 |
1 |
|
|
T3 |
3 |
|
T10 |
24 |
|
T61 |
24 |
auto[1] |
4417 |
1 |
|
|
T8 |
14 |
|
T10 |
34 |
|
T12 |
22 |
Summary for Variable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1591 |
1 |
|
|
T3 |
1 |
|
T10 |
17 |
|
T12 |
1 |
auto[1] |
4104 |
1 |
|
|
T3 |
2 |
|
T8 |
14 |
|
T10 |
41 |
Summary for Variable rst_n_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1591 |
1 |
|
|
T3 |
1 |
|
T10 |
17 |
|
T12 |
1 |
auto[1] |
4104 |
1 |
|
|
T3 |
2 |
|
T8 |
14 |
|
T10 |
41 |
Summary for Cross sw_rst_cross
Samples crossed: enable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for sw_rst_cross
Bins
enable | rst_n | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
341 |
1 |
|
|
T3 |
1 |
|
T10 |
6 |
|
T61 |
6 |
auto[0] |
auto[1] |
937 |
1 |
|
|
T3 |
2 |
|
T10 |
18 |
|
T61 |
18 |
auto[1] |
auto[0] |
1250 |
1 |
|
|
T10 |
11 |
|
T12 |
1 |
|
T61 |
14 |
auto[1] |
auto[1] |
3167 |
1 |
|
|
T8 |
14 |
|
T10 |
23 |
|
T12 |
21 |
Summary for Variable enable
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1072 |
1 |
|
|
T3 |
3 |
|
T10 |
20 |
|
T61 |
20 |
auto[1] |
4604 |
1 |
|
|
T8 |
14 |
|
T10 |
38 |
|
T12 |
20 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1072 |
1 |
|
|
T3 |
3 |
|
T10 |
20 |
|
T61 |
20 |
auto[1] |
4604 |
1 |
|
|
T8 |
14 |
|
T10 |
38 |
|
T12 |
20 |
Summary for Variable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1612 |
1 |
|
|
T3 |
2 |
|
T10 |
18 |
|
T61 |
18 |
auto[1] |
4064 |
1 |
|
|
T3 |
1 |
|
T8 |
14 |
|
T10 |
40 |
Summary for Variable rst_n_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1612 |
1 |
|
|
T3 |
2 |
|
T10 |
18 |
|
T61 |
18 |
auto[1] |
4064 |
1 |
|
|
T3 |
1 |
|
T8 |
14 |
|
T10 |
40 |
Summary for Cross sw_rst_cross
Samples crossed: enable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for sw_rst_cross
Bins
enable | rst_n | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
286 |
1 |
|
|
T3 |
2 |
|
T10 |
5 |
|
T61 |
5 |
auto[0] |
auto[1] |
786 |
1 |
|
|
T3 |
1 |
|
T10 |
15 |
|
T61 |
15 |
auto[1] |
auto[0] |
1326 |
1 |
|
|
T10 |
13 |
|
T61 |
13 |
|
T65 |
15 |
auto[1] |
auto[1] |
3278 |
1 |
|
|
T8 |
14 |
|
T10 |
25 |
|
T12 |
20 |
Summary for Variable enable
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
878 |
1 |
|
|
T10 |
16 |
|
T61 |
16 |
|
T22 |
3 |
auto[1] |
4798 |
1 |
|
|
T3 |
3 |
|
T8 |
14 |
|
T10 |
42 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
878 |
1 |
|
|
T10 |
16 |
|
T61 |
16 |
|
T22 |
3 |
auto[1] |
4798 |
1 |
|
|
T3 |
3 |
|
T8 |
14 |
|
T10 |
42 |
Summary for Variable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1629 |
1 |
|
|
T10 |
17 |
|
T61 |
20 |
|
T22 |
1 |
auto[1] |
4047 |
1 |
|
|
T3 |
3 |
|
T8 |
14 |
|
T10 |
41 |
Summary for Variable rst_n_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1629 |
1 |
|
|
T10 |
17 |
|
T61 |
20 |
|
T22 |
1 |
auto[1] |
4047 |
1 |
|
|
T3 |
3 |
|
T8 |
14 |
|
T10 |
41 |
Summary for Cross sw_rst_cross
Samples crossed: enable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for sw_rst_cross
Bins
enable | rst_n | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
238 |
1 |
|
|
T10 |
4 |
|
T61 |
4 |
|
T22 |
1 |
auto[0] |
auto[1] |
640 |
1 |
|
|
T10 |
12 |
|
T61 |
12 |
|
T22 |
2 |
auto[1] |
auto[0] |
1391 |
1 |
|
|
T10 |
13 |
|
T61 |
16 |
|
T46 |
1 |
auto[1] |
auto[1] |
3407 |
1 |
|
|
T3 |
3 |
|
T8 |
14 |
|
T10 |
29 |
Summary for Variable enable
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
669 |
1 |
|
|
T3 |
3 |
|
T10 |
12 |
|
T61 |
12 |
auto[1] |
5007 |
1 |
|
|
T8 |
14 |
|
T10 |
46 |
|
T12 |
20 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
669 |
1 |
|
|
T3 |
3 |
|
T10 |
12 |
|
T61 |
12 |
auto[1] |
5007 |
1 |
|
|
T8 |
14 |
|
T10 |
46 |
|
T12 |
20 |
Summary for Variable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1588 |
1 |
|
|
T3 |
2 |
|
T10 |
13 |
|
T61 |
17 |
auto[1] |
4088 |
1 |
|
|
T3 |
1 |
|
T8 |
14 |
|
T10 |
45 |
Summary for Variable rst_n_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1588 |
1 |
|
|
T3 |
2 |
|
T10 |
13 |
|
T61 |
17 |
auto[1] |
4088 |
1 |
|
|
T3 |
1 |
|
T8 |
14 |
|
T10 |
45 |
Summary for Cross sw_rst_cross
Samples crossed: enable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for sw_rst_cross
Bins
enable | rst_n | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
186 |
1 |
|
|
T3 |
2 |
|
T10 |
3 |
|
T61 |
3 |
auto[0] |
auto[1] |
483 |
1 |
|
|
T3 |
1 |
|
T10 |
9 |
|
T61 |
9 |
auto[1] |
auto[0] |
1402 |
1 |
|
|
T10 |
10 |
|
T61 |
14 |
|
T22 |
1 |
auto[1] |
auto[1] |
3605 |
1 |
|
|
T8 |
14 |
|
T10 |
36 |
|
T12 |
20 |
Summary for Variable enable
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
466 |
1 |
|
|
T10 |
8 |
|
T61 |
8 |
|
T65 |
8 |
auto[1] |
5210 |
1 |
|
|
T3 |
3 |
|
T8 |
14 |
|
T10 |
50 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
466 |
1 |
|
|
T10 |
8 |
|
T61 |
8 |
|
T65 |
8 |
auto[1] |
5210 |
1 |
|
|
T3 |
3 |
|
T8 |
14 |
|
T10 |
50 |
Summary for Variable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1601 |
1 |
|
|
T3 |
1 |
|
T10 |
13 |
|
T61 |
18 |
auto[1] |
4075 |
1 |
|
|
T3 |
2 |
|
T8 |
14 |
|
T10 |
45 |
Summary for Variable rst_n_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1601 |
1 |
|
|
T3 |
1 |
|
T10 |
13 |
|
T61 |
18 |
auto[1] |
4075 |
1 |
|
|
T3 |
2 |
|
T8 |
14 |
|
T10 |
45 |
Summary for Cross sw_rst_cross
Samples crossed: enable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for sw_rst_cross
Bins
enable | rst_n | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
134 |
1 |
|
|
T10 |
2 |
|
T61 |
2 |
|
T65 |
2 |
auto[0] |
auto[1] |
332 |
1 |
|
|
T10 |
6 |
|
T61 |
6 |
|
T65 |
6 |
auto[1] |
auto[0] |
1467 |
1 |
|
|
T3 |
1 |
|
T10 |
11 |
|
T61 |
16 |
auto[1] |
auto[1] |
3743 |
1 |
|
|
T3 |
2 |
|
T8 |
14 |
|
T10 |
39 |
Summary for Variable enable
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
272 |
1 |
|
|
T10 |
4 |
|
T61 |
4 |
|
T22 |
3 |
auto[1] |
5404 |
1 |
|
|
T3 |
3 |
|
T8 |
14 |
|
T10 |
54 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
272 |
1 |
|
|
T10 |
4 |
|
T61 |
4 |
|
T22 |
3 |
auto[1] |
5404 |
1 |
|
|
T3 |
3 |
|
T8 |
14 |
|
T10 |
54 |
Summary for Variable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1616 |
1 |
|
|
T10 |
15 |
|
T61 |
13 |
|
T22 |
1 |
auto[1] |
4060 |
1 |
|
|
T3 |
3 |
|
T8 |
14 |
|
T10 |
43 |
Summary for Variable rst_n_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1616 |
1 |
|
|
T10 |
15 |
|
T61 |
13 |
|
T22 |
1 |
auto[1] |
4060 |
1 |
|
|
T3 |
3 |
|
T8 |
14 |
|
T10 |
43 |
Summary for Cross sw_rst_cross
Samples crossed: enable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for sw_rst_cross
Bins
enable | rst_n | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
84 |
1 |
|
|
T10 |
1 |
|
T61 |
1 |
|
T22 |
1 |
auto[0] |
auto[1] |
188 |
1 |
|
|
T10 |
3 |
|
T61 |
3 |
|
T22 |
2 |
auto[1] |
auto[0] |
1532 |
1 |
|
|
T10 |
14 |
|
T61 |
12 |
|
T65 |
20 |
auto[1] |
auto[1] |
3872 |
1 |
|
|
T3 |
3 |
|
T8 |
14 |
|
T10 |
40 |